A comparator and analog-to-digital converter

Abstract

The application relates to a comparison device and an analog-to-digital converter. The comparison device comprises a successive approximation circuit, a latch comparator, a first positive input end of the latch comparator receiving a first signal, a second negative input end of the latch comparator receiving a second signal, and the latch comparator being capable of being switched between a calibration mode and a comparison mode. In the calibration mode, both the first positive input end and the first negative input end of the latch comparator receive a reference voltage or an input voltage, the successive approximation circuit successively approximates the first and second signals according to a comparison result of the latch comparator until the comparison result of the latch comparator changes, and an input mismatch voltage is adjusted. In the comparison mode, one of the first positive input end and the first negative input end of the latch comparator receives an input voltage, and the other receives a reference voltage. The successive approximation circuit keeps outputting the first and second signals which make the comparison result change, so that the latch comparator compares the input voltage and the reference voltage based on the adjusted input mismatch voltage and outputs a comparison result. The application can reduce the input mismatch voltage of the latch comparator and is beneficial to realizing high precision.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a comparison device and an analog-to-digital converter. Background Technology

[0002] Comparators are used in various analog-to-digital converters, such as successive approximation analog-to-digital converters (SAR ADCs). To improve the operating speed of the analog-to-digital converter, fast latch comparators are often used. However, like other comparators, latch comparators suffer from input mismatch voltage (i.e., there is a mismatch deviation during manufacturing, which can be understood as the two inputs of the comparator not being perfectly symmetrical, equivalent to a difference between the two input terminals, leading to inaccurate comparison).

[0003] To achieve high accuracy, input mismatch voltage needs to be eliminated. Existing solutions involve operating the comparator in two phases: comparator mode and buffer mode. In comparator mode, a reference voltage is latched; in the other mode, the input voltage is compared with the latched reference voltage. Since both modes are equally affected by input mismatch voltage, the effect of canceling out the input mismatch voltage is achieved, thus preventing it from affecting accuracy. However, latched comparators cannot switch to buffer mode, therefore, a solution operating in both modes cannot be used to eliminate input mismatch voltage. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned technical problems and provide a comparison device and an analog-to-digital converter that can reduce or eliminate the input mismatch voltage of the latch comparator in the comparison device, which is beneficial to achieving high accuracy.

[0005] To achieve the above objectives, the present invention provides a comparison device comprising a first successive approximation circuit and a latch comparator. The latch comparator has a first positive input terminal, a first negative input terminal, a second positive input terminal, and a second negative input terminal. The second positive input terminal receives a first signal of a differential signal, and the second negative input terminal receives a second signal of the differential signal. The latch comparator is capable of switching between a calibration mode and a comparison mode. In the calibration mode, both the first positive input terminal and the first negative input terminal receive a reference voltage or both receive an input voltage. The first successive approximation circuit outputs a voltage based on the output of the latch comparator. The comparison results are successively approximated by the output of the first signal and the second signal until the comparison result of the latch comparator changes, thereby adjusting the input mismatch voltage of the latch comparator. In the comparison mode, one of the first positive input terminal and the first negative input terminal receives the input voltage, and the other of the first positive input terminal and the first negative input terminal receives the reference voltage. The first successive approximation circuit maintains the output of the first signal and the second signal that change the comparison result of the latch comparator in the calibration mode, so that the latch comparator can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result.

[0006] Optionally, the first successive approximation circuit is configured to successively increase or decrease the first signal by predetermined steps when performing successive approximation; and / or, the first successive approximation circuit is configured to successively decrease or increase the second signal by predetermined steps when performing successive approximation.

[0007] Optionally, the comparison result of the latch comparator includes a logic high level and a logic low level. In the calibration mode: initially, the comparison result output by the output terminal of the latch comparator is the logic low level. The first successive approximation circuit successively increases the first signal or successively decreases the second signal by the predetermined step until the comparison result output by the output terminal of the latch comparator becomes the logic high level, at which point the adjustment stops; or, initially, the comparison result output by the output terminal of the latch comparator is the logic high level. The first successive approximation circuit successively decreases the first signal or successively increases the second signal by the predetermined step until the comparison result output by the output terminal of the latch comparator becomes the logic low level, at which point the adjustment stops.

[0008] Optionally, the latch comparator includes: a differential input stage, comprising a current source and a differential input circuit, one end of the current source being grounded and the other end being coupled to a first terminal of the differential input circuit, the first input terminal of the differential input circuit being a first positive input terminal and the second input terminal being a first negative input terminal, the differential input circuit being used to shunt the current provided by the current source based on the voltages input to the first positive input terminal and the first negative input terminal respectively, to output a first control signal and a second control signal; and an output stage, the first terminal of the output stage being grounded, and the second terminal of the output stage being coupled to a second terminal of the differential input circuit. The output stage is coupled to the output of the latch comparator. The output stage is used to pull up the output of the latch comparator to output a logic high level or pull down to output a logic low level based on the first control signal and the second control signal. The adjustment circuit has a first input terminal as the second positive input terminal and a second input terminal as the second negative input terminal. The adjustment circuit is used to adjust the current of at least one of the differential input stage and the output stage by changing the received first signal and / or the second signal, thereby changing the comparison result output by the output of the latch comparator.

[0009] Optionally, the differential input circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the substrates of the first NMOS transistor and the second NMOS transistor are coupled to their respective sources and to a first terminal of the differential input circuit; the gate of the first NMOS transistor is the first positive input terminal, the gate of the second NMOS transistor is the first negative input terminal, the drains of the first NMOS transistor, the drains of the first PMOS transistor, and the gates of the second PMOS transistor are coupled to a first output terminal of the differential input circuit, and the first output terminal of the differential input circuit is used to output the first control signal; the drains of the second NMOS transistor, the drains of the second PMOS transistor, and the gate of the first PMOS transistor are coupled to a second output terminal of the differential input circuit, and the second output terminal of the differential input circuit is used to output the second control signal; the substrates of the first PMOS transistor and the second PMOS transistor are coupled to their respective sources and to a second terminal of the differential input circuit.

[0010] Optionally, the adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor, wherein the gate of the fifth NMOS transistor is the second positive input terminal, and the gate of the sixth NMOS transistor is the second negative input terminal; the substrates of the fifth NMOS transistor and the sixth NMOS transistor are coupled to their respective sources and to the first terminal of the differential input circuit, the drain of the fifth NMOS transistor is coupled to the drain of the first NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the second NMOS transistor; or, the adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor; the gate of the eighth PMOS transistor is the second positive input terminal, the gate of the seventh PMOS transistor is the second negative input terminal, the substrates of the seventh PMOS transistor and the eighth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit, the drain of the seventh PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the first PMOS transistor.

[0011] Optionally, the latch comparator further includes an initialization circuit for activating the latch comparator in an initial state. The initialization circuit includes a third PMOS transistor and a fourth PMOS transistor. The substrates of the third PMOS transistor and the fourth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit. The drain of the third PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is coupled to the drain of the first PMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are used to receive initialization control signals so that the output terminal of the differential input circuit outputs the first control signal and the second control signal that activate the output stage in an initial state.

[0012] Optionally, the output stage includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the substrates of the fifth PMOS transistor and the sixth PMOS transistor are coupled to their respective sources and to a second terminal of the output stage; the gate of the fifth PMOS transistor is used to receive the second control signal; the gate of the sixth PMOS transistor is used to receive the first control signal; the drain of the fifth PMOS transistor is coupled to the drain of the third NMOS transistor and to the gate of the fourth NMOS transistor; the drains of the sixth PMOS transistor, the fourth NMOS transistor, and the third NMOS transistor are coupled to the output terminal of the latch comparator; and the substrates of the third NMOS transistor and the fourth NMOS transistor are coupled to their respective sources and to a first terminal of the output stage.

[0013] Optionally, the adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor, wherein the gate of the sixth NMOS transistor is the second positive input terminal, the gate of the fifth NMOS transistor is the second negative input terminal, the substrates of the fifth and sixth NMOS transistors are coupled to their respective sources and to the first terminal of the output stage, the drain of the fifth NMOS transistor is coupled to the drain of the fourth NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the third NMOS transistor; or, the adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor, wherein the gate of the seventh PMOS transistor is the second positive input terminal, the gate of the eighth PMOS transistor is the second negative input terminal, the substrates of the seventh and eighth PMOS transistors are coupled to their respective sources and to the second terminal of the output stage, the drain of the seventh PMOS transistor is coupled to the drain of the fifth PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the sixth PMOS transistor.

[0014] Optionally, the comparison device further includes a first switching device and a second switching device. One end of the second switching device is coupled to a voltage input terminal, and the other end is coupled to the first positive input terminal. The voltage input terminal is used to receive the input voltage. One end of the first switching device is coupled to the other end of the second switching device, and the other end of the first switching device is coupled to the first negative input terminal and a reference terminal. The reference terminal is used to receive the reference voltage. In the calibration mode, the first switching device is closed, the second switching device is open, and both the first positive input terminal and the first negative input terminal receive the reference voltage. In the comparison mode, the first switching device is open, and the first... When two switching devices are closed, the first positive input terminal receives the input voltage, and the first negative input terminal receives the reference voltage; and / or, the first successive approximation circuit includes a controller, a first digital-to-analog converter (DAC), and a second DAC. The controller is used to successively approximate and output a first group of multi-bit digital signals and a second group of multi-bit digital signals according to the comparison result of the latch comparator. The first DAC is used to convert the first group of multi-bit digital signals into the first signal and output the first signal to the second positive input terminal. The second DAC is used to convert the second group of multi-bit digital signals into the second signal and output the second signal to the second negative input terminal.

[0015] A second aspect of the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising: a comparison device provided in the first aspect above; and a second successive approximation circuit, configured to output a reference voltage to the comparison device by successive approximation through its first output terminal based on the comparison result output by the output terminal of the latch comparator of the comparison device, and to output a multi-bit digital signal through its second output terminal.

[0016] In the above scheme, since the voltages received at the first positive and first negative input terminals of the latch comparator are the same in calibration mode, the latch comparator actually compares the input mismatch voltage with zero and then outputs the comparison result. The first successive approximation circuit successively approximates the output of the first and second signals, that is, it successively adjusts at least one of the first and second signals according to the comparison result, which can gradually reduce the input mismatch voltage and make it gradually approach zero. When the output result of the latch comparator changes, for example from the output logic high level to the output logic low level or from the output logic low level to the output logic high level, the input mismatch voltage is reduced to near zero, and the adjustment is completed. Then, in comparison mode, one of the first positive and first negative input terminals receives the input voltage, and the other receives the reference voltage. The first successive approximation circuit can keep the output of the adjusted first and second signals unchanged, so that the latch comparator can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result. This reduces or eliminates the input mismatch voltage of the latch comparator, which can make the accuracy of the comparison result output by the latch comparator higher and helps to achieve high precision.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a comparator capable of eliminating input mismatch voltage.

[0020] Figure 2 A schematic diagram of the structure of the comparison device provided in the embodiments of this application;

[0021] Figure 3 for Figure 2 A schematic diagram of the first circuit structure of the latch comparator in the comparison device shown;

[0022] Figure 4 for Figure 2 A schematic diagram of the second circuit structure of the latch comparator in the comparison device shown;

[0023] Figure 5 for Figure 2 A schematic diagram of the third circuit structure of the latch comparator in the comparison device shown;

[0024] Figure 6 for Figure 2 A schematic diagram of the fourth circuit structure of the latch comparator in the comparison device shown;

[0025] Figure 7 This is a schematic diagram of the circuit structure of an analog-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that the term "coupled" as used in this text includes both direct connections between two or more circuit objects without any intervening circuit objects, and indirect connections between two or more circuit objects achieved through one or more intervening circuit objects. For example, two circuit objects directly connected to each other are said to be "coupled" to each other. Similarly, two circuit objects connected by one or more intervening circuit objects are also said to be "coupled" to each other. In other words, "coupled" can be a direct electrical connection or an indirect electrical connection, where there are other components in between, such as resistors or capacitors.

[0028] Figure 1 This is a schematic diagram of a comparator capable of eliminating input mismatch voltage. (Example) Figure 1 As shown, the comparator includes an operational amplifier OP, a capacitor C1, switches S1, S2, and S3, and inverters INV1 and INV2. Clock signal CK2 controls the opening and closing of switch S1, and clock signal CK1 simultaneously controls the opening and closing of switches S2 and S3. Inverters INV1 and INV2 function as shapers, specifically shortening the rise and fall times of the output pulse signal OC.

[0029] The comparator operates in two phases. Specifically, CK1 and CK2 are non-overlapping clock signals; that is, when CK1 is logic high, CK2 is logic low, and vice versa. In one example, when CK1 is logic high and CK2 is logic low, switches S2 and S3 are on, and switch S1 is off. The operational amplifier (OP) operates in buffer mode, storing the reference voltage REF and the comparator's input mismatch voltage in capacitor C1. When CK1 is logic low and CK2 is logic high, switches S2 and S3 are off, and switch S1 is on. The OP operates in comparator mode, comparing the input voltage at the positive input terminal (input from the VIN terminal and affected by the input mismatch voltage) with the reference voltage REF and the comparator's input mismatch voltage stored in capacitor C1. Since the stored reference voltage and the input voltage are both connected to the same terminal of the OP (the positive input terminal), they are equally affected by the input mismatch voltage, thus canceling out the influence of the input mismatch voltage during comparison.

[0030] However, the latch comparator cannot switch to buffer mode, so it is not possible to use a scheme that operates in both modes to eliminate input mismatch voltage.

[0031] In view of this, embodiments of this application provide a comparison device and an analog-to-digital converter including the comparison device. The latch comparator of the comparison device has a calibration mode and a comparison mode. In the calibration mode, the input mismatch voltage can be adjusted to approach zero. Then, in the comparison mode, the input voltage and the reference voltage can be compared based on the adjusted input mismatch voltage approaching zero, and the comparison result is output. This can reduce or eliminate the input mismatch voltage of the latch comparator, making the accuracy of the comparison result output by the latch comparator higher, which helps to achieve high precision.

[0032] Figure 2 This is a schematic diagram of the comparison device provided in an embodiment of this application. Figure 2 As shown, the comparison device includes a first successive approximation circuit and a latch comparator CMP. The first output terminal of the first successive approximation circuit (i.e., the output terminal of the first digital-to-analog converter DACX, which will be described below) is used to successively approximate the first signal of the differential signal output. The second output terminal (i.e., the output terminal of the second digital-to-analog converter DACY, which will be described below) is used to successively approximate the second signal of the differential signal output. The latch comparator CMP has a first positive input terminal VP1, a first negative input terminal VN1, a second positive input terminal VP2, and a second negative input terminal VN2; that is, the latch comparator CMP is a four-terminal input comparator. The second positive input terminal VP2 is used to receive the first signal, and the second negative input terminal VN2 is used to receive the second signal.

[0033] Specifically, the first successive approximation circuit may include a controller CTRL, a first digital-to-analog converter (DACX), and a second digital-to-analog converter (DACY). The output of the first DACX is the first output of the first successive approximation circuit, and the output of the second DACY is the second output of the first successive approximation circuit. The controller CTRL is used to successively approximate and output a first set of multi-bit digital signals DX1-DXn and a second set of multi-bit digital signals DY1-DYn according to the comparison result of the latch comparator CMP. The first DACX is used to convert the first set of multi-bit digital signals DX1-DXn into a first signal and output the first signal to the second positive input terminal VP2. The second DACY is used to convert the second set of multi-bit digital signals DY1-DYn into a second signal and output the second signal to the second negative input terminal VN2.

[0034] Furthermore, the latch comparator CMP can switch between calibration mode and comparison mode. In calibration mode, both the first positive input terminal VP1 and the first negative input terminal VN1 receive a reference voltage or both receive an input voltage. The first successive approximation circuit successively approximates the comparison result output by the output terminal of the latch comparator CMP by outputting a first signal and a second signal until the comparison result of the latch comparator CMP changes, thereby adjusting the input mismatch voltage of the latch comparator CMP. In comparison mode, one of the first positive input terminal VP1 and the first negative input terminal VN1 receives the input voltage, and the other of the first positive input terminal VP1 and the first negative input terminal VN1 receives the reference voltage. The first successive approximation circuit maintains the first signal and the second signal that change the comparison result of the latch comparator CMP in the calibration mode, so that the latch comparator CMP can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result.

[0035] In the above scheme, since the voltages received at the first positive input terminal VP1 and the first negative input terminal VN1 of the latch comparator CMP in calibration mode are the same, the latch comparator CMP actually compares the input mismatch voltage with zero and then outputs the comparison result. The first successive approximation circuit successively approximates the output of the first signal and the second signal, that is, it successively adjusts at least one of the first signal and the second signal according to the comparison result, which can gradually reduce the input mismatch voltage and make it gradually approach zero. When the output result of the latch comparator CMP changes, for example from the output logic high level to the output logic low level or from the output logic low level to the output logic high level, the input mismatch voltage is reduced to near zero, and the adjustment is completed. Then, in comparison mode, one of the first positive input terminal and the first negative input terminal receives the input voltage, and the other receives the reference voltage. The first successive approximation circuit can keep the adjusted first signal and the second signal unchanged, so that the latch comparator CMP can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result. This can reduce or eliminate the input mismatch voltage of the latch comparator CMP and help to achieve high accuracy.

[0036] Specifically, to reduce or eliminate the input mismatch voltage of the latch comparator CMP, the first successive approximation circuit can be configured to successively increase or decrease the first signal in predetermined steps during successive approximation. The first successive approximation circuit can also be configured to successively decrease or increase the second signal in predetermined steps during successive approximation. For example, the first successive approximation circuit can be configured to successively increase the first signal in predetermined steps and decrease the second signal in predetermined steps during successive approximation. Alternatively, the first successive approximation circuit can be configured to successively decrease the first signal in predetermined steps and increase the second signal in predetermined steps during successive approximation. Here, the "predetermined step" can be the minimum step or a multiple of the minimum step.

[0037] Furthermore, the comparison result of the latch comparator can include logic high level and logic low level. In calibration mode, the comparison result of the latch comparator can change in the following two ways, but is not limited to:

[0038] In the first scenario, initially, the output of the latch comparator CMP is at a logic low level. The first successive approximation circuit then successively raises the first signal or lowers the second signal by a predetermined step. Specifically, when the latch comparator CMP outputs a logic low level, the controller CTRL controls the first digital-to-analog converter DACX to raise its output by a predetermined step or lower its output by a predetermined step until the output of the latch comparator CMP becomes a logic high level, at which point the adjustment stops.

[0039] In the second scenario, initially, the output of the latch comparator CMP is at a logic high level. The first successive approximation circuit gradually lowers the first signal or gradually raises the second signal by a predetermined step. Specifically, when the latch comparator CMP outputs a logic high level, the controller CTRL controls the first digital-to-analog converter DACX to either lower the DACX output or raise the DACY output by a predetermined step until the output of the latch comparator CMP becomes a logic low level, at which point the adjustment stops.

[0040] Furthermore, such as Figure 2 As shown, the comparator may further include a first switching device S1 and a second switching device S2. One end of the second switching device S2 is coupled to a voltage input terminal VIN, and the other end is coupled to a first positive input terminal VP1. The voltage input terminal VIN is used to receive the input voltage. One end of the first switching device S1 is coupled to the other end of the second switching device S2, and the other end of the first switching device S1 is coupled to a first negative input terminal VN1 and a reference terminal REF. The reference terminal REF is used to receive a reference voltage. In calibration mode, the first switching device S1 is closed and the second switching device S2 is open, so that both the first positive input terminal and the first negative input terminal receive the reference voltage input from the reference terminal REF. In comparator mode, the first switching device S1 is open and the second switching device S2 is closed, so that the first positive input terminal receives the input voltage input from the voltage input terminal VIN, and the first negative input terminal receives the reference voltage input from the reference terminal REF.

[0041] Alternatively, in calibration mode, other switching devices can be configured so that both the first positive input terminal and the first negative input terminal receive the input voltage from the voltage input terminal VIN. In comparison mode, the positions of the voltage input terminal VIN and the reference terminal REF can also be interchanged. That is, one end of the second switching device S2 is coupled to the reference terminal REF, and the other end is coupled to the first positive input terminal VP1. One end of the first switching device S1 is coupled to the other end of the second switching device S2, and the other end of the first switching device S1 is coupled to the first negative input terminal VN1 and the voltage input terminal VIN.

[0042] In other words, the comparator works alternately in two time periods. The first time period is the calibration period. During this period, CK1 can be at a logic high level, the first switching device S1 is closed, CK2 can be at a logic low level, the second switching device S2 is open, and the voltages of the first positive input terminal VP1 and the first negative input terminal VN1 are equal to the reference voltage input at the reference terminal REF. Input mismatch voltage calibration can be performed. The controller CTRL controls DX1~DXn and DY1~DYn according to the output result CMPO of the comparator. If the comparator output CMPO is logic low, the controller CTRL gradually increases the output voltage VP2 of DACX by increasing DX1 to DXn in predetermined steps (e.g., the minimum step), or gradually decreases the output voltage VN2 of DCY by decreasing DY1 to DYn in predetermined steps (e.g., the minimum step), until the comparator output CMPO changes from logic low to logic high, at which point the adjustment stops. This effectively reduces the input mismatch voltage of the comparator. Conversely, if the comparator output CMPO is logic high, the controller CTRL gradually decreases the output voltage VP2 of DACX by decreasing DX1 to DXn in predetermined steps (e.g., the minimum step), or gradually increases the output voltage VN2 of DCY by increasing DY1 to DYn in predetermined steps (e.g., the minimum step), until the comparator output CMPO changes from logic high to logic low, at which point the adjustment stops. This effectively reduces the input mismatch voltage of the comparator.

[0043] Figure 3 for Figure 2 The diagram shows a first circuit structure of the latch comparator in the comparison device. Figure 4 for Figure 2 The diagram shows a second circuit structure of the latch comparator in the comparison device. Figure 5 for Figure 2 The diagram shows a third circuit structure of the latch comparator in the comparison device. Figure 6 for Figure 2 The diagram shows a fourth circuit structure of the latch comparator in the comparison device. The following is an example of... Figure 3 For example, Figure 3As shown, the latch comparator CMP may include a differential input stage, an output stage, and an adjustment circuit. The differential input stage includes a current source I1 and a differential input circuit. One end of the current source I1 is grounded, and the other end is coupled to the first terminal of the differential input circuit. The first input terminal of the differential input circuit is the first positive input terminal VP1, and the second input terminal is the first negative input terminal VN1. The differential input circuit is used to shunt the current provided by the current source I1 based on the voltages input to the first positive input terminal VP1 and the first negative input terminal VN1, so as to output a first control signal and a second control signal. The first control signal can be sent to the sixth PMOS transistor of the output stage, which will be described below; the second control signal can be sent to the fifth PMOS transistor of the output stage, which will be described below.

[0044] The first terminal of the output stage is grounded, and the second terminal of the output stage is coupled to the second terminal of the differential input circuit. The output terminal OUT of the output stage is the output terminal of the latch comparator CMP. The output stage is used to pull up the output terminal of the latch comparator CMP to output a logic high level or pull down to output a logic low level based on the first control signal and the second control signal.

[0045] The first input terminal of the adjustment circuit is the second positive input terminal VP2, and the second input terminal is the second negative input terminal VN2. The adjustment circuit is used to adjust the current of at least one of the differential input stage and output stage by changing the received first signal and / or the second signal, thereby changing the comparison result output by the output terminal of the latch comparator CMP, that is, changing the comparison result of the output terminal of the latch comparator from logic high level to logic low level or from logic low level to logic high level.

[0046] Specifically, in the latch comparator of the comparison device in this application embodiment, the adjustment circuit can have, but is not limited to, the following four schemes:

[0047] like Figures 3-6As shown, the differential input circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The first and second NMOS transistors are a differential pair. The substrates of the first and second NMOS transistors are coupled to their respective sources and are also coupled to one end of the first terminal of the differential input circuit. The gate of the first NMOS transistor is the first positive input terminal VP1, and the gate of the second NMOS transistor is the first negative input terminal VN1. The drains of the first NMOS transistor, the drains of the first PMOS transistor, and the gates of the second PMOS transistor are coupled and are also coupled to the first output terminal of the differential input circuit, which outputs a first control signal. The drains of the second NMOS transistor, the drains of the second PMOS transistor, and the gates of the first PMOS transistor are coupled and are also coupled to the second output terminal of the differential input circuit, which outputs a second control signal. The substrates of the first and second PMOS transistors are coupled to their respective sources and are also coupled to the second terminal of the differential input circuit. In this case, the adjustment circuit can have the following two schemes:

[0048] Option 1 - as Figure 3 As shown, the adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The gate of the fifth NMOS transistor is the second positive input terminal VP2, and the gate of the sixth NMOS transistor is the second negative input terminal VN2. The substrates of the fifth and sixth NMOS transistors are coupled to their respective sources and to the first terminal of the differential input circuit. The drain of the fifth NMOS transistor is coupled to the drain of the first NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the second NMOS transistor.

[0049] Option 2 - as Figure 4 As shown, the adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor; the gate of the eighth PMOS transistor is the second positive input terminal VP2, and the gate of the seventh PMOS transistor is the second negative input terminal VN2. The substrates of the seventh PMOS transistor and the eighth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit. The drain of the seventh PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the first PMOS transistor.

[0050] Furthermore, the latch comparator CMP may also include an initialization circuit for activating the latch comparator CMP in an initial state. The initialization circuit includes a third PMOS transistor and a fourth PMOS transistor. The substrates of the third PMOS transistor and the fourth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit. The drain of the third PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is coupled to the drain of the first PMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are used to receive initialization control signals so that the output terminal of the differential input circuit outputs a first control signal and a second control signal that activate the output stage in an initial state.

[0051] like Figures 3-6 As shown, the output stage includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The substrates of the fifth and sixth PMOS transistors are coupled to their respective sources and to the second terminal of the output stage. The gate of the fifth PMOS transistor receives a second control signal, and the gate of the sixth PMOS transistor receives a first control signal. The drain of the fifth PMOS transistor is coupled to the drain of the third NMOS transistor and to the gate of the fourth NMOS transistor. The drains of the sixth PMOS transistor, the fourth NMOS transistor, and the gate of the third NMOS transistor are coupled and to the output terminal of the latch comparator CMP. The substrates of the third and fourth NMOS transistors are coupled to their respective sources and to the first terminal of the output stage. In this case, the adjustment circuit can have the following two schemes:

[0052] Option 3 – such as Figure 5 As shown, the adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The gate of the sixth NMOS transistor is the second positive input terminal VP2, and the gate of the fifth NMOS transistor is the second negative input terminal VN2. The substrates of the fifth and sixth NMOS transistors are coupled to their respective sources and to the first terminal of the output stage. The drain of the fifth NMOS transistor is coupled to the drain of the fourth NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the third NMOS transistor.

[0053] Option 4 – such as Figure 6 As shown, the adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor; the gate of the seventh PMOS transistor is the second positive input terminal VP2, and the gate of the eighth PMOS transistor is the second negative input terminal VN2. The substrates of the seventh PMOS transistor and the eighth PMOS transistor are coupled to their respective sources and to the second terminal of the output stage. The drain of the seventh PMOS transistor is coupled to the drain of the fifth PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the sixth PMOS transistor.

[0054] In other words, Figures 3-6In the four-terminal input comparator CMP, the differential input stage and output stage have the same circuit structure, but the adjustment circuit structure is different. Specifically:

[0055] Figure 3 The four-terminal input comparator shown includes NMOS transistors MN1 to MN6, PMOS transistors MP1 to MP6, and current source I1. The adjustment circuit uses MN5 and MN6 to affect the voltage of the drains of MN1 and MN2 to generate mismatch control. By changing the voltage difference between the second differential input received at the second positive input terminal VP2 and the second negative input terminal VN2, the input mismatch voltage equivalent to the first differential input at the first positive input terminal VP1 and the first negative input terminal VN1 can be canceled.

[0056] Figure 4 The four-terminal input comparator shown includes NMOS transistors MN1-MN4, PMOS transistors MP1-MP8, and a current source I1. Figure 3 The difference between the four-terminal input comparators shown is that... Figure 4 The adjustment circuit uses MP7 and MP8 to affect the voltage of the drains of MP2 and MP1 respectively to generate mismatch control, so as to reduce and cancel the input mismatch voltage equivalent to the first differential input at the first positive input terminal VP1 and the first negative input terminal VN1.

[0057] Figure 5 The four-terminal input comparator shown includes NMOS transistors MN1-MN6, PMOS transistors MP1-MP6, and a current source I1. Figure 3 The difference between the four-terminal input comparators shown is that... Figure 5 The adjustment circuit uses MN5 and MN6 to affect the voltage of the drains of MN4 and MN3 respectively to generate mismatch control, so as to reduce and cancel the input mismatch voltage equivalent to the first differential input at the first positive input terminal VP1 and the first negative input terminal VN1.

[0058] Figure 6 The four-terminal input comparator shown includes NMOS transistors MN1-MN4, PMOS transistors MP1-MP8, and a current source I1. Figure 3 The difference between the four-terminal input comparators shown is that... Figure 6 The system uses MP7 and MP8 to affect the voltage of the drains of MP5 and MP6 respectively to generate mismatch control, thereby reducing and offsetting the input mismatch voltage equivalent to the first differential input at the first positive input terminal VP1 and the first negative input terminal VN1.

[0059] Furthermore, in Figures 3-6 In the diagram, the gates of MP1 and MP2 are cross-coupled to form positive feedback, and the gates of MN3 and MN4 are also cross-coupled to form positive feedback, which helps to accelerate the response speed of the comparator. The following section uses... Figure 3 Let's take an example to give a detailed introduction.

[0060] exist Figure 3 In the process, the CK signal is used to initialize the initial state of the latch comparator. When CK is low, the latch comparator CMP is initialized. MP3 and MP4 are turned on, which initializes the internal nodes (gates of MP5 and MP6) of the latch comparator CMP to high level. When the CK signal goes high, the latch comparator CMP performs the comparison function normally.

[0061] If we disregard the input mismatch voltage, and VP2 and VN2 are equal, and VP1 is higher than VN1, MN1 will receive more current than MN2 (when VP1 equals VN1, the drain currents of MN1 and MN2 are equal because they are perfectly symmetrical. The differential input pair works by dividing the current source I1). Therefore, the drain voltage of MN1 will be lower than the drain voltage of MN2 (the positive feedback formed by MP1 and MP2 will further enhance this effect; specifically, a decrease in the drain voltage of MN1 means a decrease in the gate voltage of MP2, leading to a decrease in the drain voltage of MP2). The increase in drain current further leads to an increase in the drain voltage of MN2 (i.e., the drain voltage of MP2), which in turn leads to an increase in the gate voltage of MP1. This causes a decrease in the drain current of MP1, resulting in a lower drain voltage of MN1 compared to the drain voltage of MN2. The gate voltage of MP6 will be lower than the gate voltage of MP5, and the drain current of MP6 will be greater than the drain current of MP5. Therefore, the output OUT will be pulled up. The drain current of MN3 will increase (because the gate voltage of MN3 increases), causing the gate voltage of MN4 to decrease. The positive feedback formed by MN3 and MN4 causes the output OUT to rise further and become high.

[0062] If we disregard the input mismatch voltage, and VP2 and VN2 are equal, if VP1 is lower than VN1, MN1 will receive less current than MN2 (when VP1 equals VN1, the drain currents of MN1 and MN2 are equal because they are perfectly symmetrical. The working principle of the differential input pair is to divide the current source I1). Therefore, the drain voltage of MN1 will be higher than that of MN2, the gate voltage of MP6 will be higher than that of MP5, and the drain current of MP6 will be less than that of MP5. Consequently, the output OUT will be pulled down, the drain current of MN3 will decrease (because the gate voltage of MN3 drops), causing the gate voltage of MN4 to rise. The positive feedback formed by MN3 and MN4 causes the output OUT to drop further and become low.

[0063] Further considering the input mismatch voltage, when the voltages VP2 and VN2 are not equal, the deviation will disrupt the aforementioned current balance (i.e., the drain currents of MN5 and MN6 are not equal). This current deviation will effectively affect the topping point of the latch comparator CMP inputs VP1 and VN1. In this embodiment, by introducing such a deviation and adjusting it to an appropriate value, the impact of the input mismatch voltage caused during production is offset.

[0064] Figure 7 This is a schematic diagram of the circuit structure of an analog-to-digital converter provided in an embodiment of this application. Figure 7 As shown, the analog-to-digital converter includes the aforementioned comparator Comp and the second successive approximation circuit. The second successive approximation circuit is used to successively approximate the reference voltage VREF to the comparator Comp through its first output terminal (i.e., the output terminal of the DAC, which will be introduced below, and also the reference terminal) based on the comparison result output from the output terminal of the latch comparator CMP of the comparator Comp, and to output a multi-bit digital signal, such as a 10-bit digital signal D0-D9, through its second output terminal.

[0065] The second successive approximation circuit may include a successive approximation logic (SAR Logic) and a digital-to-analog converter (DAC). The DAC may also include a reset unit (not shown), an indicator unit (not shown), and an oscillator (OSC). The reset unit receives a reset signal RST, which resets the SAR Logic to its initial state before it begins operation. The indicator unit outputs a termination signal Term; for example, when the termination signal Term changes from low to high, it indicates the end of one analog-to-digital conversion process by the SAR Logic. The oscillator (OSC) generates a clock signal CK3, causing the SAR Logic to output a digital signal, such as the tens-bit digital signal D9-D0, based on the comparison result CMPO output by the latch comparator CMP of the comparator Comp. The DAC converts the digital signal output by the SAR Logic, such as the tens-bit digital signal D9-D0, into an analog signal, i.e., a reference voltage VREF, and outputs the reference voltage VREF to the comparator Comp.

[0066] In other words, Figure 7 The analog-to-digital converter shown may include a comparator Comp, an analog-to-digital converter (DAC), an oscillator (OSC), and successive approximation logic (SAR). The comparator Comp is... Figure 2 The structure shown indicates that the latch comparator CMP of the comparator Comp can be adopted. Figures 3-6The implementation shown in the diagram is used to cancel and reduce the equivalent input mismatch voltage. The oscillator OSC generates the clock signal CK3. The successive approximation logic (SAR) generates successive approximation digital signals D9-D0 based on the output of the comparator CMPO. The digital-to-analog converter (DAC) generates a reference voltage VREF based on the digital signals D9-D0. During the successive approximation comparison process, the reference voltage VREF gradually approaches the input signal VIN. After nine comparisons, a termination signal Term is generated, and the digital signals D9-D0 are output, thus realizing a 10-bit successive approximation DAC.

[0067] and, Figure 7 The oscillator OSC shown can also generate Figure 2 The clock signals CK1, CK2 and Figures 3-6 The clock signal CK in; or, Figure 2 The clock signals CK1, CK2 and Figures 3-6 The clock signal CK can also be generated by another oscillator or by multiple other oscillators, depending on the specific needs.

[0068] In summary, in this application, since the voltages received at the first positive and first negative input terminals of the calibration mode latch comparator are the same, the latch comparator actually compares the input mismatch voltage with zero, and then outputs the comparison result. The first successive approximation circuit successively approximates the output of the first and second signals (i.e., adjusting at least one of the first and second signals according to the comparison result), which can gradually reduce the input mismatch voltage, making it gradually approach zero. When the output result of the latch comparator changes, for example from a logic high level to a logic low level or from a logic low level to a logic high level... When the output logic is high, the input mismatch voltage decreases to near zero, thus completing the adjustment. Next, in comparison mode, one of the first positive input terminal and the first negative input terminal receives the input voltage, and the other receives the reference voltage. The first successive approximation circuit can keep the first and second signals after the output adjustment unchanged, so that the latch comparator can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result. This reduces or eliminates the input mismatch voltage of the latch comparator, which can make the comparison result output by the latch comparator more accurate and help to achieve high precision.

[0069] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0070] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A comparison device, characterized by The circuit includes a first successive approximation circuit and a latch comparator. The latch comparator has a first positive input, a first negative input, a second positive input, and a second negative input. The second positive input receives a first signal of the differential signal, and the second negative input receives a second signal of the differential signal. The latch comparator can switch between a calibration mode and a comparison mode. In the calibration mode, both the first positive input terminal and the first negative input terminal receive a reference voltage or both receive an input voltage. The first successive approximation circuit successively approximates and outputs the first signal and the second signal according to the comparison result output by the output terminal of the latch comparator until the comparison result of the latch comparator changes, so as to adjust the input mismatch voltage of the latch comparator. In the comparison mode, one of the first positive input terminal and the first negative input terminal receives the input voltage, and the other of the first positive input terminal and the first negative input terminal receives the reference voltage. The first successive approximation circuit maintains the first signal and the second signal that change the comparison result of the latch comparator in the calibration mode, so that the latch comparator can compare the input voltage and the reference voltage based on the adjusted input mismatch voltage and output the comparison result. The latch comparator includes a differential input stage, comprising a current source and a differential input circuit. One end of the current source is grounded, and the other end is coupled to a first end of the differential input circuit. The first input end of the differential input circuit is the first positive input end, and the second input end is the first negative input end. The differential input circuit is used to shunt the current provided by the current source based on the voltages input to the first positive input end and the first negative input end, respectively, to output a first control signal and a second control signal. The output stage has a first terminal grounded and a second terminal coupled to the second terminal of the differential input circuit. The output terminal of the output stage is the output terminal of the latch comparator. The output stage is used to pull up the output terminal of the latch comparator to output a logic high level or pull down to output a logic low level based on the first control signal and the second control signal. An adjustment circuit, wherein its first input terminal is the second positive input terminal and its second input terminal is the second negative input terminal, is used to adjust the current of at least one of the differential input stage and the output stage by changing the received first signal and / or the second signal, thereby changing the comparison result output by the output terminal of the latch comparator.

2. The comparison device according to claim 1, characterized in that: The first successive approximation circuit is configured to successively increase or decrease the first signal in predetermined steps during successive approximation; and / or, The first successive approximation circuit is configured to successively lower or raise the second signal in predetermined steps during successive approximation.

3. The comparison device of claim 2, wherein, The comparison result of the latch comparator includes a logic high level and a logic low level, in the calibration mode: Initially, the comparison result output by the latch comparator is a logic low level. The first successive approximation circuit successively increases the first signal or successively decreases the second signal in predetermined steps until the comparison result output by the latch comparator becomes a logic high level, at which point the adjustment stops; or, Initially, the comparison result output by the latch comparator is a logic high level. The first successive approximation circuit successively lowers the first signal or successively raises the second signal by the predetermined step until the comparison result output by the latch comparator becomes a logic low level, at which point the adjustment stops.

4. The comparison device of claim 1, wherein, The differential input circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The substrates of the first NMOS transistor and the second NMOS transistor are coupled to their respective sources and to the first terminal of the differential input circuit; the gate of the first NMOS transistor is the first positive input terminal, the gate of the second NMOS transistor is the first negative input terminal, the drain of the first NMOS transistor, the drain of the first PMOS transistor, and the gate of the second PMOS transistor are coupled to the first output terminal of the differential input circuit, and the first output terminal of the differential input circuit is used to output the first control signal; The drain of the second NMOS transistor, the drain of the second PMOS transistor, and the gate of the first PMOS transistor are coupled together and coupled to the second output terminal of the differential input circuit. The second output terminal of the differential input circuit is used to output the second control signal. The substrates of the first PMOS transistor and the second PMOS transistor are coupled together with their respective sources and coupled to the second terminal of the differential input circuit.

5. The comparison device according to claim 4, characterized in that: The adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The gate of the fifth NMOS transistor is the second positive input terminal, and the gate of the sixth NMOS transistor is the second negative input terminal. The substrates of the fifth and sixth NMOS transistors are coupled to their respective sources and to the first terminal of the differential input circuit. The drain of the fifth NMOS transistor is coupled to the drain of the first NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the second NMOS transistor. The adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor; the gate of the eighth PMOS transistor is the second positive input terminal, the gate of the seventh PMOS transistor is the second negative input terminal, the substrates of the seventh PMOS transistor and the eighth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit, the drain of the seventh PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the first PMOS transistor.

6. The comparison device of claim 4, wherein, The latch comparator further includes an initialization circuit, which is used to put the latch comparator into an initial state. The initialization circuit includes a third PMOS transistor and a fourth PMOS transistor. The substrates of the third PMOS transistor and the fourth PMOS transistor are coupled to their respective sources and to the second terminal of the differential input circuit. The drain of the third PMOS transistor is coupled to the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is coupled to the drain of the first PMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are used to receive initialization control signals so that the output terminal of the differential input circuit outputs the first control signal and the second control signal to initialize the output stage.

7. The comparison device of claim 1, wherein, The output stage includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The substrates of the fifth PMOS transistor and the sixth PMOS transistor are coupled to their respective sources and to the second terminal of the output stage. The gate of the fifth PMOS transistor is used to receive the second control signal, and the gate of the sixth PMOS transistor is used to receive the first control signal. The drain of the fifth PMOS transistor is coupled to the drain of the third NMOS transistor and to the gate of the fourth NMOS transistor. The drains of the sixth PMOS transistor, the fourth NMOS transistor, and the third NMOS transistor are coupled to the output terminal of the latch comparator. The substrates of the third NMOS transistor and the fourth NMOS transistor are coupled to their respective sources and to the first terminal of the output stage.

8. The comparison device according to claim 7, characterized in that: The adjustment circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The gate of the sixth NMOS transistor is the second positive input terminal, and the gate of the fifth NMOS transistor is the second negative input terminal. The substrates of the fifth and sixth NMOS transistors are coupled to their respective sources and to the first terminal of the output stage. The drain of the fifth NMOS transistor is coupled to the drain of the fourth NMOS transistor, and the drain of the sixth NMOS transistor is coupled to the drain of the third NMOS transistor; or, The adjustment circuit includes a seventh PMOS transistor and an eighth PMOS transistor; the gate of the seventh PMOS transistor is the second positive input terminal, and the gate of the eighth PMOS transistor is the second negative input terminal. The substrates of the seventh PMOS transistor and the eighth PMOS transistor are coupled to their respective sources and to the second terminal of the output stage. The drain of the seventh PMOS transistor is coupled to the drain of the fifth PMOS transistor, and the drain of the eighth PMOS transistor is coupled to the drain of the sixth PMOS transistor.

9. The comparison device according to any one of claims 1-8, characterized in that: The comparison device further includes a first switching device and a second switching device, one end of the second switching device is used to be coupled to a voltage input terminal, and the other end is coupled to the first positive input terminal, the voltage input terminal is used to receive the input voltage; One end of the first switching device is coupled to the other end of the second switching device, and the other end of the first switching device is coupled to the first negative input terminal and a reference terminal, wherein the reference terminal is used to receive the reference voltage; wherein: in the calibration mode, the first switching device is closed, the second switching device is open, and both the first positive input terminal and the first negative input terminal receive the reference voltage; in the comparison mode, the first switching device is open, the second switching device is closed, the first positive input terminal receives the input voltage, and the first negative input terminal receives the reference voltage; and / or The first successive approximation circuit includes a controller, a first digital-to-analog converter (DAC), and a second DAC. The controller is used to successively approximate and output a first group of multi-bit digital signals and a second group of multi-bit digital signals according to the comparison result of the latch comparator. The first DAC is used to convert the first group of multi-bit digital signals into the first signal and output the first signal to the second positive input terminal. The second DAC is used to convert the second group of multi-bit digital signals into the second signal and output the second signal to the second negative input terminal.

10. An analog-to-digital converter, characterized by include: The comparison apparatus according to any one of claims 1-9; The second successive approximation circuit is used to output a reference voltage to the comparator by successive approximation through its first output terminal based on the comparison result output by the output terminal of the latch comparator of the comparator, and to output a multi-bit digital signal through its second output terminal.

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