IC voltage abnormality processing method and device, storage medium, and terminal

Abstract

A method and apparatus, storage medium, and terminal for handling voltage anomalies in an integrated circuit (IC). The IC includes a detectable node and an undetectable node, wherein the undetectable node is coupled to the detectable node. The method comprises: reading the current value of a status register at predetermined intervals, wherein the current value is correlated with the voltage of the detectable node; comparing the current value with the initial value of the status register; and restarting the IC if the current value differs from the initial value. This allows the voltage of the predetermined node to be detected to be converted into a TE signal, allowing the host ESD detection process to overcome the anomaly and ensure normal operation of the IC.

Description

Technical Field

[0001] The present invention relates to the application field of microelectronic devices, and in particular to a method and device for processing abnormal voltage of an IC, a storage medium, and a terminal. Background Art

[0002] When using microelectronic devices (Integrated Circuit Chips, ICs) multiple voltages exist at different potentials. Electrostatic discharge (ESD) or IC latch-up can cause some IC voltages to become abnormal. For example, some IC voltages may not rise partially or completely, or even be pulled too high.

[0003] Among them, the main method currently in the market for voltage anomalies caused by the locking effect is to prevent the locking effect from occurring by adding Schottky diode clamping. This method requires accurate positioning of the path and principle of the locking effect, and cannot resolve the locking effect for voltage anomalies that are not located.

[0004] IC abnormality detection and recovery are usually performed through the device host ESD detection process. However, existing abnormality detection and recovery methods are not accurate, which may cause some voltage abnormalities to go undetected and affect the normal operation of the IC. Summary of the Invention

[0005] The technical problem solved by the present invention is how to comprehensively and accurately detect IC voltage anomalies and recover from the anomalies to ensure the normal operation of the IC.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for handling voltage anomalies in an IC, wherein the IC includes a detectable node and an undetectable node, and the undetectable node is coupled to the detectable node. The method includes: reading the current value of a status register at preset time intervals, wherein the current value is related to the voltage of the detectable node; comparing the current value with the initial value of the status register; and restarting the IC if the current value is different from the initial value.

[0007] Optionally, if the voltage of the undetectable node is abnormal, the voltage of the detectable node is changed.

[0008] Optionally, after the voltage of the detectable node is changed, the current value is adjusted so that the current value is different from the initial value.

[0009] Optionally, after the voltage of the detectable point is changed, the current value cannot be read, or an error is reported when reading the current value.

[0010] Optionally, the undetectable node is an abnormal node that is pre-located when the IC is running.

[0011] Optionally, the undetectable node is coupled to the detectable node via a level conversion module.

[0012] Optionally, the level conversion module includes one or more resistors.

[0013] An embodiment of the present invention also provides a voltage anomaly processing device for an IC, wherein the IC includes a detectable node and an undetectable node, wherein the undetectable node is coupled to the detectable node, and the device includes: a timing detection module, configured to read the current value of a status register at preset time intervals, wherein the current value is related to the voltage of the detectable node; a comparison module, configured to compare the current value with the initial value of the status register; and an initialization module, configured to restart the IC if the current value is different from the initial value.

[0014] An embodiment of the present invention further provides a storage medium having a computer program stored thereon, wherein the computer program implements the steps of any one of the methods when executed by a processor.

[0015] An embodiment of the present invention also provides a terminal, including an IC, a memory and a processor, wherein the IC includes a detectable node and an undetectable node, the undetectable node is coupled to the detectable node, the memory stores a computer program, and the processor implements the steps of any one of the methods when executing the computer program.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] An embodiment of the present invention provides a method for handling voltage anomalies in an IC. The IC includes a detectable node and an undetectable node, wherein the undetectable node is coupled to the detectable node. The method comprises: reading a current value of a status register at predetermined intervals, wherein the current value is correlated with the voltage of the detectable node; comparing the current value with an initial value of the status register; and restarting the IC if the current value differs from the initial value. Compared to existing technologies, this method, which correlates the voltage of the undetectable node with the voltage of the detectable node, allows a host to read the current value of the status register, detect voltage anomalies in the undetectable node, and overcome the anomaly through the host's ESD detection process, thereby ensuring normal operation of the IC.

[0018] Furthermore, the undetectable node is coupled to the detectable node via a level conversion module, and the level conversion module includes one or more resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a host ESD detection process in the prior art;

[0020] Figure 2 This is a waveform diagram of a normal TE signal in the prior art;

[0021] Figure 3 This is a schematic diagram of the connection between a host and a Driver IC in the prior art;

[0022] Figure 4 1 is a flow chart of a method for handling abnormal voltage of an IC according to an embodiment of the present invention;

[0023] Figure 5 A circuit diagram of a method for handling abnormal voltage of an IC according to an embodiment of the present invention;

[0024] Figure 6 The figure is a schematic structural diagram of a device for handling abnormal voltage of an IC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Specifically, see Figure 1 , Figure 1 This is a schematic diagram of the host ESD detection process in the prior art. Two traditional detection methods are generally used: Method 1, also known as the "status register read method," involves the host periodically reading the status register value. Method 1 includes the following steps:

[0026] Step S111, storing the initial value of the status register of the driver IC;

[0027] Step S112: The host periodically reads the value of the IC status register and compares it with the initial value;

[0028] If the value read in step S112 is the same as the initial value, step S1113 is executed, and the host does not take any action; the host ESD detection process ends.

[0029] If the value read in step S112 is different from the initial value, step S114 is executed, and the host calls the process of "host IC power supply disconnection + reset + IC initialization code" to initialize the IC. The host ESD detection process ends. Enter the next detection, such as Figure 1 "Start next cycle at a fixed time"

[0030] For example, see Table 1, which provides an example of the content of each bit value of a status register:

[0031] Table 1

[0032]

[0033]

[0034] Among them, Write represents the "write" operation, Read represents the "read" operation, Default represents the default value, Booster represents the "boost voltage", and Idle represents the "idle state".

[0035] Table 2 provides an explanation of some of the bit values ​​in Table 1.

[0036]

[0037] The host reads the value of the Driver IC's status register as "0x0A" (hexadecimal). The initial value of this status register is "0x08." When ESD causes the voltage of the module covered by the Bit 7 Booster to become abnormal, and this abnormality causes Bit D7 to change (from 0 to 1), the value changes to "0x88." Because the initial value of 0x08 differs from the value 0x88 read by the timing loop, the host interprets this as an abnormality and initiates a "host IC power disconnect, reset, and IC initialization code" sequence to restore the IC to a normal state. This traditional principle is based on the discrepancy between register values.

[0038] Method 2 is also called "TE detection method", where the host periodically detects the TE signal. Method 2 includes the following steps:

[0039] Step S121, the host detects the TE signal;

[0040] If the detection result of step S121 is abnormal, the process jumps to step S114, and the host calls the process of "host IC power off + reset + IC initialization code" to initialize the IC. The host ESD detection process ends.

[0041] If the detection result of step S121 is normal, step S122 is executed, and the host does not take any action. The host ESD detection process ends.

[0042] Enter the next test, such as Figure 1 "Start next cycle at a fixed time"

[0043] The host detects the edge of the TE signal, that is, if it detects a low level and a high level, it considers the TE signal to be normal. Figure 2 , Figure 2 This is a waveform diagram of a normal TE signal in the prior art. The high level amplitude of the TE signal is H, and the low level amplitude is L. When the level detected by the host is higher than 80% H, the high level is considered normal; when the low level amplitude detected is lower than 30%, the low level is considered normal. When both are normal, the TE signal is considered normal. Figure 3 , Figure 3 This is a diagram of a host and Driver IC connection in the prior art. The host supplies power to the Driver IC via power supplies A and B, and can send a reset signal to the Driver IC to reset it. The host can also interact with the Driver IC via a data line. Currently, the power supply for the TE signal used in the market is typically the interface power supply (IOVCC), such as IOVCC = 1.8V, without an analog power supply. Therefore, if the analog power supply fails, the TE signal will not fail. Therefore, the motherboard cannot determine whether the TE signal is abnormal and initiate the "host IC power disconnection + reset + IC initialization code" process to restore the Driver IC to a normal state.

[0044] Among them, the host calls the steps of "host IC power supply disconnect + reset + send IC initialization code": the host originally has the corresponding statements and functions to control the above three actions. "Host IC power supply disconnect" is to use the function to Figure 3 The power supply A / B in the program is disconnected and no power is supplied to the Driver IC; "Reset" means that the host sends a reset command to reset the Driver IC through a statement; "Send IC initialization code" means that the host initializes the Driver IC by calling the initialization function.

[0045] However, as mentioned in the background art, the abnormality detection and recovery methods in the prior art are not accurate, which may cause some voltage abnormalities to go undetected, thereby affecting the normal operation of the IC.

[0046] To solve the above problems, an embodiment of the present invention provides a method for handling voltage anomalies in an IC, wherein the IC includes a detectable node and an undetectable node, and the undetectable node is coupled to the detectable node. The method includes: reading the current value of a status register at preset time intervals, wherein the current value is related to the voltage of the detectable node; comparing the current value with the initial value of the status register; and restarting the IC if the current value is different from the initial value.

[0047] In this way, the voltage of the preset node to be tested can be converted into a TE signal, and the abnormality can be overcome through the host ESD detection process to ensure the normal operation of the IC.

[0048] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] See Figure 4 , Figure 4The present invention is a flowchart of a method for handling voltage anomalies in an IC, wherein the IC includes a detectable node and an undetectable node, wherein the undetectable node is coupled to the detectable node. The method for handling voltage anomalies in the IC specifically includes the following steps:

[0050] Step S401, reading a current value of a status register at a preset time interval, wherein the current value is related to the voltage of the detectable node;

[0051] Step S402, comparing the current value with the initial value of the status register;

[0052] Step S403: If the current value is different from the initial value, restart the IC.

[0053] Please see again Figure 1 , Figure 1 In step S112, the host periodically reads the value of the status register of the IC as the current value.

[0054] The IC may be a liquid crystal display module (LCM or LCD module) IC or the like.

[0055] The status register is a register within the IC that stores a status value, at least a portion of which is related to the voltage values ​​of certain nodes within the IC. For a node within the IC, if its voltage value is related to the status value stored in the status register, the node is a detectable node; otherwise, the node is an undetectable node. By coupling a detectable node with an undetectable node, the voltage of the undetectable node can be correlated with the current value obtained when a host reads the status register.

[0056] The initial value is a preset value corresponding to the status value of the status register. When the status value of the status register is read as the initial value, it indicates that the IC is operating normally. The initial value can be stored in a preset location for the host to obtain.

[0057] pass Figure 1 Method 1 completes the above steps S401 to S403. When the current value read is different from the initial value of the status register, the host calls the process of "host IC power supply disconnection + reset + IC initialization code transmission" to initialize the IC, that is, restart the IC.

[0058] In addition, if the current value is the same as the initial value, the host does not operate and the IC operates normally.

[0059] Optionally, if the voltage of the undetectable node is abnormal, the voltage of the detectable node is changed.

[0060] Optionally, after the voltage of the detectable node is changed, the current value is adjusted so that the current value is different from the initial value.

[0061] If the current value is different from the initial value, it indicates that a voltage anomaly exists in the undetectable node. This anomaly may be caused by ESD or latch-up. In this case, the voltage of the undetectable node is higher or lower than its normal operating voltage.

[0062] pass Figure 4 The method is executed by a terminal such as a mobile phone, and can associate the voltage of an undetectable node with the voltage of a detectable node, so that the host can read the current value of the status register to detect the voltage anomaly of the undetectable node, and overcome the anomaly through the host ESD detection process to ensure the normal operation of the IC.

[0063] In one embodiment, after the voltage of the detectable point is changed, the current value cannot be read, or an error is reported when the current value is read.

[0064] If the host cannot read the current value of the status register or an error occurs during reading, the current value will be different from the initial value.

[0065] Optionally, the undetectable node is an abnormal node that is pre-located when the IC is running.

[0066] Abnormal nodes are nodes in the IC that may have abnormal voltages due to ESD or latch-up. These nodes are pre-located, and undetectable nodes are coupled to detectable nodes. Alternatively, abnormal nodes can be identified as undetectable nodes through experimental detection, and the IC circuitry can be modified to couple the undetectable nodes to detectable nodes.

[0067] Optionally, if multiple abnormal nodes are located, the node with the highest abnormal frequency among the multiple abnormal nodes may be coupled to the detectable node to avoid abnormal operation of the IC as much as possible.

[0068] Optionally, if multiple abnormal nodes are located, the multiple abnormal nodes can be treated as undetectable nodes respectively, and the multiple undetectable nodes can be coupled to different detectable nodes that affect the current value of the status register. If the voltage of one of the undetectable nodes is abnormal, it will affect the current value of the status register.

[0069] In one embodiment, the undetectable node is coupled to the detectable node via a level conversion module.

[0070] Optionally, the level conversion module is used to increase or decrease the voltage of the undetectable node.

[0071] Optionally, the level conversion module includes one or more resistors.

[0072] If the IC does not have an internal related circuit design, it is necessary to use a peripheral circuit. The design example is as follows: Figure 5 , Figure 5 This is a circuit diagram of a method for handling abnormal voltage of an IC according to an embodiment of the present invention. The undetectable node V1 is converted by a level conversion module ( Figure 5 A single resistor R is coupled to the detectable node DVDD. If the voltage affecting IC reading is the DVDD register voltage, DVDD = 1.5 volts (V) under normal circumstances.

[0073] The selection of R must meet the following requirements: 1. When V1 is normal, DVDD will not be significantly affected; that is, R's resistance must be large enough. 2. When V1 is abnormal, it should cause a millivolt (mV) voltage drop on DVDD. That is, when V1 is normal, DVDD = 1.5V, and the motherboard can read the status register without any problems. However, when V1 is abnormal, it pulls the DVDD voltage down (for example, DVDD = 1.0V), and the digital circuitry within the Driver IC will be unable to determine whether the status register value is 0 or 1. Therefore, when the host reads the status register, it will inevitably read an incorrect value. Therefore, the host will invoke the "host IC power off + reset + IC initialization code" procedure to restore the IC to a normal state.

[0074] See Figure 6 An embodiment of the present invention further provides a device for handling voltage anomalies in an IC, wherein the IC includes a detectable node and an undetectable node, wherein the undetectable node is coupled to the detectable node, and the device includes:

[0075] A timing detection module 601 is configured to read a current value of a status register at a preset time interval, where the current value is related to the voltage of the detectable node;

[0076] A comparison module 602 is configured to compare the current value with an initial value of the status register;

[0077] The initialization module 603 is configured to restart the IC if the current value is different from the initial value.

[0078] For more information about the working principle and working mode of the IC voltage abnormality processing device 60, please refer to the above Figure 4 and Figure 5 The description of the method for handling IC voltage anomalies in the previous section will not be repeated here.

[0079] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.

[0080] The term "plurality" used in the embodiments of the present application refers to two or more.

[0081] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0082] The "connection" appearing in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for handling abnormal voltage of an IC, characterized in that: The IC includes a detectable node and an undetectable node, the undetectable node is coupled to the detectable node, and the method includes: Reading a current value of a status register at every preset time, wherein the current value is related to the voltage of the detectable node and the voltage of the undetectable node; comparing the current value with the initial value of the status register; If the current value is different from the initial value, the IC is restarted.

2. The method according to claim 1, characterized in that If the voltage of the undetectable node is abnormal, the voltage of the detectable node is changed.

3. The method according to claim 2, characterized in that After the voltage of the detectable node is changed, the current value is adjusted so that the current value is different from the initial value.

4. The method according to claim 2, characterized in that After the voltage of the detectable node is changed, the current value cannot be read, or an error is reported when reading the current value.

5. The method according to claim 1, wherein The undetectable node is an abnormal node that is pre-located when the IC is running.

6. The method according to claim 1, characterized in that The undetectable node is coupled to the detectable node through a level conversion module.

7. The method according to claim 6, characterized in that The level conversion module includes one or more resistors.

8. An IC voltage abnormality processing device, characterized in that: The IC includes a detectable node and an undetectable node, the undetectable node is coupled to the detectable node, and the apparatus includes: a timing detection module, configured to read a current value of a status register at a preset time interval, wherein the current value is related to the voltage of the detectable node and the voltage of the undetectable node; a comparison module, configured to compare the current value with an initial value of the status register; An initialization module is configured to restart the IC if the current value is different from the initial value.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A terminal comprising an IC, a memory, and a processor, wherein the IC comprises a detectable node and an undetectable node, the undetectable node is coupled to the detectable node, and the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

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