Systems for executing new instructions and methods for executing new instructions

Abstract

This invention relates to a system and method for executing new instructions. The method includes: receiving an instruction; determining whether the received instruction is a new instruction based on its opcode; and when the received instruction is a new instruction: storing basic decoding information of the received instruction into a private register, wherein the basic decoding information includes the opcode; and entering a system management mode, and simulating the execution of the received instruction in the system management mode based on the basic decoding information stored in the private register. Therefore, without modifying the processor's microarchitecture, instructions newly supported by a later-generation processor can be implemented on a previous-generation processor, greatly reducing the workload for design, testing, and other tasks, thus saving significant costs.

Description

Technical Field

[0001] The present invention relates to a method and system for executing instructions, and more particularly to a method and system for executing newly added instructions. Background Technology

[0002] As processor capabilities increase, later generations of processors often add new instructions based on their predecessors. Implementing these new instructions on top of the earlier ones usually requires modifying the microarchitecture of the earlier processor. Modifying the microarchitecture involves extensive design and testing, resulting in extremely high costs.

[0003] Therefore, how to implement the new instructions supported by the next generation of processors without modifying the microarchitecture of the previous generation has become a problem that needs to be solved in this field. Summary of the Invention

[0004] To address the aforementioned problems, the present invention provides a method and a system for executing new instructions.

[0005] The present invention provides a method for executing a new instruction, comprising: receiving an instruction; determining whether the received instruction is a new instruction based on the opcode of the received instruction; and when the received instruction is a new instruction: storing basic decoding information of the received instruction into a private register, wherein the basic decoding information includes the opcode; and entering a system management mode, and simulating the execution of the received instruction in the system management mode based on the basic decoding information stored in the private register.

[0006] This invention provides a system for executing new instructions, comprising: an instruction monitoring unit that receives an instruction and determines whether the received instruction is a new instruction based on the opcode of the received instruction; an instruction decoding unit that, when the received instruction is a new instruction, stores basic decoding information of the received instruction in a private register; the system for executing new instructions enters a system management mode and, in the system management mode, simulates the execution of the received instruction based on the basic decoding information stored in the private register, wherein the basic decoding information includes the opcode.

[0007] The method and system for executing new instructions provided by this invention allow for the implementation of newly added instructions in later-generation processors on previous-generation processors without modifying the processor's microarchitecture. This significantly reduces the workload for design, testing, and other tasks, thus saving substantial costs. Attached Figure Description

[0008] Figure 1 This is a schematic diagram showing a system for executing new instructions according to an embodiment of the present invention.

[0009] Figure 2A This is a structural diagram showing the processor according to the first embodiment of the present invention.

[0010] Figure 2B This is a structural diagram showing the processor according to the second embodiment of the present invention.

[0011] Figure 2B1 This is a structural diagram showing the instruction monitoring unit according to the second embodiment of the present invention.

[0012] Figure 2C This is a structural diagram showing the processor according to the third embodiment of the present invention.

[0013] Figure 2D This is a structural diagram showing the processor according to the fourth embodiment of the present invention.

[0014] Figure 2D1 This is a structural diagram showing the instruction monitoring unit according to the fourth embodiment of the present invention.

[0015] Figure 3 This is a flowchart illustrating the processing of received instructions according to an embodiment of the present invention.

[0016] Figure 4 This is a flowchart illustrating the entry into system management mode according to an embodiment of the present invention.

[0017] Figure 5 This is a flowchart showing the processing of a simulator according to an embodiment of the present invention.

[0018] Figure 6 This is an example illustrating the simulation of receiving instructions in system management mode according to an embodiment of the present invention.

[0019] Figure 7 This is a flowchart illustrating the exit from system management mode according to an embodiment of the present invention.

[0020] Figure 8 This is a flowchart illustrating the execution of a new instruction according to an embodiment of the present invention.

[0021] Figure 9 This is a flowchart illustrating the execution of a new instruction according to another embodiment of the present invention.

[0022] Figure 10 This is a flowchart illustrating the execution of a new instruction according to another embodiment of the present invention.

[0023] The symbols in the attached diagram are briefly explained as follows:

[0024] 100: System executing new instructions; 110: Processor; 112: Instruction Monitor Unit; 114: System Management Mode Entry / Exit; 1142: System Management Mode Entry; 1144: System Management Mode Exit; 116: Dedicated Hardware; 120: Operating System; 130: Application Programming; 132: New Instruction; 142: Emulator; 201: Instruction Bypass Translation Buffer; 202, 202B, 202D: Instruction Cache; 203: Branch Predictor; 204, 204C, 204D: Renaming Unit; 205: Reserved Station; 206: Execution Unit; 207: Memory Access Unit; 210, 210B, 210C, 210D: Instruction Monitor Unit; 2101B, 210... 1D: Instruction parsing unit; 2102B, 2102D: Instruction judgment unit; 211: Special purpose register group; 220, 220B, 220D: Private registers; 221, 221C, 221D: Microcode control unit; 230, 230B, 230D: Instruction decoding unit; 240, 240C, 240D: Reordering buffer; 245, 245C, 245D: Instruction submission unit; 260: Architecture register; EF, EF1~EFN: Analog identifiers; S301~S315, S401~S411, S501~S519, S701~S729, S801~S809, S901~S913, S1001~S1009: Steps. Detailed Implementation

[0025] The following description illustrates a preferred embodiment of the invention and is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual scope of the invention must be determined by referring to the claims that follow.

[0026] It must be understood that the words “comprising” and “including” used in this specification are used to indicate the presence of specific technical features, values, method steps, work processes, elements and / or components, but do not preclude the addition of more technical features, values, method steps, work processes, elements, components, or any combination thereof.

[0027] The use of terms such as "first," "second," and "third" in the claims is to modify the elements in the claims, and is not to indicate that there is a priority order or a precedence relationship between the elements, or that one element precedes another element, or the chronological order of the execution of the method steps. It is only used to distinguish elements with the same name.

[0028] To better describe the embodiments of the present invention, the specific terms used in the present invention will be defined below.

[0029] Old instructions: Instructions that were natively supported by previous generation processors are called native instructions, also known as existing instructions or old instructions.

[0030] Unknown instructions: Instructions not natively supported by previous generation processors.

[0031] New instructions: Instructions added to the support of the new generation of processors compared to their predecessors. These new instructions are not recognized by the previous generation of processors and are therefore unknown to them.

[0032] New architecture registers: These are the new architecture registers supported by the later generation of processors compared to their predecessors. These new architecture registers did not exist in the previous generation of processors; therefore, when simulating the execution of new instructions using these new architecture registers on a previous generation processor, it is necessary to simulate the new architecture registers.

[0033] Unrecognized instructions: These are the remaining instructions after excluding newly added instructions. In other words, unrecognized instructions are those not natively supported by later processors.

[0034] Model-specific registers: A type of register in a processor that can be used to perform specific functions.

[0035] Traps: Traps are generally caused by software interrupt instructions (such as the INT instruction). When an instruction causes a trap exception, it does not mean that the instruction itself has an error. Therefore, after an instruction encounters a trap exception, the processor will continue executing the next instruction. For example, when software developers debug software code, they can set breakpoints in the code. When the code with breakpoints is executed on the processor, a trap will be generated when the breakpoint is reached, causing the code to pause execution at the breakpoint. Software developers can use the microcode handler for traps to view the values ​​of various architecture registers or variables in the code when the code reaches the breakpoint. Based on these values, they can determine whether the code executed correctly when the breakpoint was reached.

[0036] Figure 1 This is a schematic diagram showing a system 100 for executing new instructions according to an embodiment of the present invention. Figure 1As shown, the system 100 executing the new instructions includes a processor 110, an operating system 120, an application program 130, and an emulator 142. The operating system 120 runs on the processor 110 and manages it. The application program 130 runs on the operating system 120 and can use various functions provided by the processor 110 and other hardware (not shown, such as hard drives, network cards, etc.) through the operating system 120. The emulator 142 runs on the processor 110 in System Management Mode (SMM). Neither the operating system 120 nor the application program 130 is aware of the execution process of the emulator 142. That is, all operations performed by the emulator 142 are transparent to the operating system 120 or the application program 130.

[0037] When processor 110 executes a new instruction from application 130 or operating system 120, processor 110 enters system management mode and sends the new instruction to simulator 142 to simulate its execution. It is worth noting that the source code of application 130 or operating system 120 is generally written in a high-level language (such as C, C++, etc.) and / or a low-level language (such as assembly language, etc.). After the source code is compiled using a compiler, executable code that can be executed by the processor is generated. Executable code consists of instructions that can be directly executed by the processor. In this invention, application 130 or operating system 120 refers to the executable code generated after the source code of application 130 or operating system 120 is compiled by a compiler. The following will use... Figure 1 Taking the processor 110 executing instruction 118 of application program 130 as an example, the processing of the system 100 executing new instructions is briefly described.

[0038] like Figure 1 As shown, the processor 110 includes an instruction monitoring unit 112 and a system management mode entry / exit 114. The system management mode entry / exit 114 includes a system management mode entry 1142 and a system management mode exit 1144. Figure 1 Solid arrows with numerical designations indicate the direction of instruction information transmission, while dashed arrows with numerical designations indicate the direction of instruction simulation execution results transmission. The following describes the entire process of processor 110 simulating the execution of the newly added instruction 132.

[0039] First, processor 110 receives instruction 118 from application program 130 to perform a specified function (as shown by solid arrow 1). After receiving instruction 118, instruction monitoring unit 112 determines whether instruction 118 is a new instruction 132 and generates an emulation flag (EF). If instruction 118 is a new instruction 132 (the emulation flag is a first value, which is 1 in one embodiment), processor 110 issues a system management interrupt (#SMI) and simultaneously sends the instruction information of the new instruction 132 to system management mode entry / exit 114 (as shown by solid arrow 2). How to issue a system management interrupt is common knowledge to those skilled in the art and will not be described in detail here. Then, processor 110 enters system management mode through execution system management mode entry 1142 and sends the instruction information of the new instruction 132 to emulator 142 (as shown by solid arrow 3). In system management mode, emulator 142 simulates the execution of the new instruction 132. After simulating the execution of the new instruction 132, the simulator 142 sends the simulation execution result to the system management mode entry / exit 114 (as shown by dashed arrow 4). Then, the processor 110 exits the system management mode through the system management mode exit 1144 and sends the simulation execution result to the application program 130 (as shown by dashed arrow 5). At this point, the processor 110 has completed the simulation execution of the new instruction 132. In one embodiment, during the simulation execution of the new instruction 132 by the simulator 142, intermediate calculation results generated during the simulation execution can be stored in the system management memory (SMRAM).

[0040] In another embodiment, processor 110 further includes dedicated hardware 116. During the simulation execution of the new instruction 132 by simulator 142, intermediate computation results generated during the simulation execution can be stored in dedicated hardware 116. In another embodiment, when the operand of the new instruction 132 is a new architecture register, simulator 142 can utilize dedicated hardware 116 to simulate the aforementioned new architecture register (described in detail below). Compared to accessing system-managed memory, simulator 142 can access dedicated hardware 116 at a faster speed, thus accelerating the simulation execution.

[0041] This invention has multiple embodiments, which are described below through four examples. The first and second embodiments describe how to pass an analog identifier into the pipeline (i.e., pass in an analog identifier such as...). Figure 2AThe system management mode is entered via the renaming unit 204, rearrangement buffer 240, etc. (as shown in the diagram). The third and fourth embodiments describe the case where the system management mode is entered by storing the analog flag in a private register; in this case, it is not necessary to pass the analog flag into the pipeline. In the first and third embodiments, the instruction monitoring unit determines whether the received instruction is a new instruction based on the instruction information from the instruction decoding unit. In the second and fourth embodiments, the instruction monitoring unit determines whether the received instruction is a new instruction based on the machine code of the received instruction from the instruction cache. The following will first combine... Figure 2A as well as Figure 3-7 The first embodiment is described.

[0042] [First Embodiment]

[0043] Figure 2A This is a structural diagram showing the processor according to the first embodiment of the present invention. Figure 2A As shown, the part to the left of the dashed line is Figure 1 The diagram of processor 110 shown depicts simulator 142 running on processor 110 in system management mode, located to the right of the dashed line. The following section will combine... Figure 1 right Figure 2A Please provide an explanation.

[0044] like Figure 2A As shown, processor 110 includes an Instruction Translation Lookaside Buffer (ITLB) 201, an Instruction Cache 202, and a Branch Predictor 203. When processor 110 executes an instruction from application program 130 or operating system 120, the ITLB 201 of processor 110 receives this instruction. The branch predictor 203 predicts conditional branches and passes the branch prediction result to the instruction cache 202. The instruction cache 202 retrieves the received instruction from the ITLB 201 based on the branch prediction result, and then processor 110 performs further processing on the received instruction.

[0045] like Figure 2AAs shown, the processor 110 also includes an instruction decoding unit 230, an instruction monitoring unit 210, a private register 220, a renaming unit 204, a reservation station 205, an execution unit 206, a memory access unit 207, a rearrangement buffer 240, a microcode control unit 221, an architecture register 260, and a dedicated register set 211. The instruction decoding unit 230 retrieves the received instruction from the instruction cache 202 and processes it to generate a microinstruction. The renaming unit 204 receives the microinstruction from the instruction decoding unit 230 and renames it. Then, the renaming unit 204 sends the renamed microinstruction to the reservation station 205 and the rearrangement buffer 240. The reservation station 205, depending on the type of the microinstruction, sends it to the execution unit 206 or the memory access unit 207 for further processing. After receiving the microinstruction, the rearrangement buffer 240 stores it in an instruction entry. The area storing microinstructions in renaming unit 204 includes a simulated identifier field (e.g., Figure 2A The rearrangement buffer 240 (EF) is used to store the emulation identifier in the microinstructions. The rearrangement buffer 240 contains multiple instruction entries, each containing an emulation identifier field (e.g., EF). Figure 2A EF1, EF2, EFN, etc., are used to store the emulation identifiers in the microinstructions.

[0046] The instruction decoding unit 230 decodes the received instruction to obtain its decoding information. This decoding information includes a prefix, escape code, opcode, operand mode (ModR / M), and other decoding information. Then, the instruction decoding unit 230 generates a microinstruction based on this decoding information. In one embodiment, when the received instruction is a new instruction, the generated microinstruction is a no-operation microinstruction (NOP). The instruction decoding unit 230 sends the decoding information of the received instruction to the instruction monitoring unit 210 to determine whether the received instruction is a new instruction. It should be noted that since the instruction monitoring unit 210 determines whether the unknown instruction is a new instruction based on the decoding information such as the prefix, escape code, opcode, and operand mode of the received instruction, those skilled in the art can perform the above-mentioned judgment operation using combinational logic circuits.

[0047] After determining whether the received instruction is a new instruction, the instruction monitoring unit 210 generates a simulation identifier. When the received instruction is a new instruction, the simulation identifier is a first value, indicating that the received instruction is an instruction to be simulated; otherwise, the simulation identifier is a second value, indicating that the received instruction is not an instruction to be simulated. In one embodiment, the first value is 1 and the second value is 0. Then, the instruction monitoring unit 210 sends the simulation identifier to the private register 220 and the renaming unit 204. When the simulation identifier is the first value (indicating that the received instruction is a new instruction), the instruction decoding unit 230 stops fetching instructions from the instruction cache 202 and sends the decoding information to the private register 220. The private register 220 stores the simulation identifier and the decoding information. The renaming unit 204 receives the microinstruction from the instruction decoding unit 230 and receives the simulation identifier from the instruction monitoring unit 210. Then, the renaming unit 204 adds a simulation identifier field EF to the microinstruction to store the simulation identifier. When the aforementioned analog flag is the second value (i.e., the received instruction is not a new instruction), the processor 110 will process the received instruction in a normal manner. How the received instruction is processed normally—for example, if the received instruction is an old instruction, the old instruction is executed normally—is common knowledge to those skilled in the art and will not be elaborated here. It is worth noting that the aforementioned decoding information and analog flag stored in the private register 220 will not be overwritten when the processor 110 performs a context switch. The aforementioned analog flag stored in the private register 220 will only be overwritten when the processor 110 executes another instruction. For example, if the other instruction is an old instruction, the instruction monitoring unit 210 generates an analog flag with a second value and updates the analog flag field of the private register 220; if the other instruction is a new instruction, the instruction monitoring unit 210 generates an analog flag with a first value and the decoding information of the other instruction, and updates the analog flag field and the field storing the decoding information of the received instruction in the private register 220.

[0048] like Figure 2A As shown, in the rearrangement buffer 240, EF1 represents the simulated identifier EF1 in the simulated identifier field of instruction entry 1, EF2 represents the simulated identifier EF2 in the simulated identifier field of instruction entry 2, EFN represents the simulated identifier EFN in the simulated identifier field of instruction entry N, and so on. The rearrangement buffer 240 contains an instruction submission unit 245. When the aforementioned microinstruction is in a await-submit (retire) state and meets the submission conditions, the instruction submission unit 245 will submit the aforementioned microinstruction.

[0049] When the instruction submission unit 245 submits the aforementioned microinstruction, if the simulated identifier of the microinstruction is a first value (indicating that the received instruction is a new instruction), the instruction submission unit 245 will issue a system management interrupt (#SMI). In response to the aforementioned system management interrupt, the processor 110 will, as follows: Figure 1 The system management mode entry 1142 shown enters the system management mode to simulate the execution of the aforementioned receive instruction. During the simulated execution of the receive instruction, intermediate calculation results can be stored in system management memory or in a dedicated register within dedicated register group 211. In one embodiment, dedicated register group 211 is... Figure 1 Part of the dedicated hardware 116 shown.

[0050] The following is combined Figure 1 , Figure 2A as well as Figure 3 The following details how the processor 110 processes the aforementioned receive instruction in the first embodiment.

[0051] Please refer to the following at the same time Figure 1 , Figure 2A as well as Figure 3 .like Figure 3 As shown, the instruction decoding unit 230 receives an instruction (S301) and determines whether the received instruction is a new instruction (S307). If the received instruction is a new instruction, the system 100 that executes the new instruction will simulate the execution of the received instruction (S313). A detailed description follows: The instruction decoding unit 230 first executes step S301.

[0052] In step S301, the instruction decoding unit 230 receives an instruction. As described above, the instruction decoding unit 230 receives the instruction from the instruction cache 202. Then, step S307 is executed.

[0053] In step S307, the instruction monitoring unit 210 determines whether the received instruction is a new instruction. Specifically, as follows: Figure 2AAs shown, the instruction decoding unit 230 first decodes the received instruction to obtain decoding information. This decoding information includes the prefix, escape code, opcode, length, operand mode (ModR / M), source operand (register or memory), and destination operand (register or memory), etc., of the received instruction. The instruction pointer (EIP), escape code, opcode, length, and operand mode of the received instruction constitute the basic instruction information of the received instruction. The escape code, opcode, and operand mode of the received instruction constitute the basic decoding information of the received instruction. Then, the instruction decoding unit 230 generates a microinstruction based on the decoding information and sends the generated microinstruction to the renaming unit 204. Simultaneously, the instruction decoding unit 230 sends the decoding information to the instruction monitoring unit 210. The instruction monitoring unit 210 determines whether the received instruction is a new instruction based on the decoding information. For example, the opcodes of newly added instructions supported only by successor processors of processor 110 can be stored in a lookup table. Instruction monitoring unit 210 can check whether the opcode of the received instruction is stored in the lookup table. If the opcode is stored in the lookup table, it indicates that the received instruction is a newly added instruction; otherwise, it indicates that the received instruction is not a newly added instruction. In one embodiment, the lookup table is stored in instruction monitoring unit 210. Instruction monitoring unit 210 determines whether the received instruction is a newly added instruction based on the prefix, escape code, and opcode of the received instruction. In another embodiment, instruction monitoring unit 210 determines whether the received instruction is a newly added instruction based on the escape code, opcode, and operand pattern of the received instruction.

[0054] If the received instruction is not a new instruction (the result of step S307 is "No"), the processor 110 executes step S305 to process the received instruction normally. How to process the received instruction normally is common knowledge to those skilled in the art and will not be elaborated here. If the received instruction is a new instruction (the result of step S307 is "Yes"), the processor 110 executes step S309.

[0055] In step S309, the processor 110 sets a simulation identifier and prepares the information needed to simulate the execution of a receive instruction. Specifically, after the instruction monitoring unit 210 determines that the receive instruction is a new instruction, it generates a simulation identifier with a first value and sends the simulation identifier to the renaming unit 204 and the private register 220. The private register 220 stores the simulation identifier in its simulation identifier field. After receiving the simulation identifier and the microinstruction, the renaming unit 204 adds a simulation identifier field to the microinstruction and stores the simulation identifier in the simulation identifier field of the microinstruction. In one embodiment, the receive instruction is a no-operation microinstruction (NOP).

[0056] In step S309, when the simulated identifier generated by the instruction monitoring unit 210 is the first value, the instruction decoding unit 230 also stores the decoding information of the received instruction and the runtime environment information into the private register 220. The runtime environment information refers to the state information of the processor 110 when it executes the received instruction. This runtime environment information includes the running mode of the received instruction (i.e., the running mode of the processor 110 when it executes the received instruction). For example, the running mode includes read mode, protected mode, v8086 mode, compatibility mode, and long mode, etc.

[0057] Then, the renaming unit 204 sends the aforementioned microinstructions to the rearrangement buffer 240. For example... Figure 2A As shown, assuming the aforementioned microinstruction is stored in entry 1 of the rearrangement buffer 240, the value of EF1 is the first value. In one embodiment, the aforementioned microinstruction does not need to be executed by the execution unit 206, so it does not need to be sent to the reservation station 205.

[0058] When the instruction submission unit 245 submits the aforementioned microinstruction, since the value of EF1 in entry 1 storing the aforementioned microinstruction is the first value, the instruction submission unit 245 issues a system management interrupt (#SMI). Then, the microcode control unit 221 executes step S311.

[0059] In step S311, processor 110 enters system management mode. Specifically, in response to the aforementioned system management interrupt, microcode control unit 221 executes as follows: Figure 1The system management interrupt entry 1142 shown is the microcode handler (SMI) entry for entering the system management interrupt. In system management interrupt entry 1142, the processor 110 stores the analog identifier (valued as the first value), the decoded information of the aforementioned received instruction, and the runtime environment information stored in the private register 220 into the system management memory, and then enters system management mode (which will be discussed later in conjunction with...). Figure 4 (Detailed explanation)

[0060] Then, processor 110 executes step S313. In step S313, in system management mode, processor 110 simulates the execution of the aforementioned receive instruction (which will be discussed in conjunction with...). Figure 5 and Figure 6 (Detailed explanation)

[0061] Finally, processor 110 executes step S315 to exit system management mode. Specifically, microcode control unit 221 executes as follows: Figure 1 The system management interrupt exit 1144 shown (i.e., the microcode handler SMIexit for exiting the system management interrupt) is used to exit system management mode (which will be discussed later in conjunction with...). Figure 7 (Detailed explanation)

[0062] It is worth noting that, in the actual operation of entering system management mode via system management interrupt entry 1142 in step S311, those skilled in the art can add some microcode to the microcode corresponding to entering system management mode after issuing a system management interrupt (#SMI). This microcode executes the saving of the simulation identifier, the decoding information of the aforementioned received instructions, and the runtime environment information to the system management mode memory (SMRAM), ensuring that this data / information is not overwritten when the processor 110 switches to system management mode. Furthermore, because, in known technologies, the processor 110 accesses system management memory when entering system management mode, those skilled in the art can modify this part of the microcode to achieve the purpose of accessing this data / information. Since these microcodes vary depending on the processor version, those skilled in the art can write the corresponding microcode according to the actual situation. Similarly, in the actual operation of exiting the system management mode via the system management interrupt exit 1144 in step S315, those skilled in the art can add some microcode to the microcode corresponding to the exit system management mode after calling the instruction to exit system management mode (Resume from System management Mode, RSM). This microcode will store the simulated execution result from the system management memory into the architecture register, so as to pass the simulated execution result to the application program 130 or the operating system 120. Since these microcodes will vary depending on the processor version, those skilled in the art can write the corresponding microcode according to the actual situation.

[0063] In one embodiment, the processor 110 can only directly access system-managed memory and not directly access memory (i.e., system memory) in system-managed mode, and all interrupts are disabled in system-managed mode. If the aforementioned receive instruction needs to access memory (for example, when the source operand or destination operand of the aforementioned receive instruction is a memory operand), the instruction decoding unit 230 will decode the aforementioned receive instruction into a special micro-instruction so that before entering system-managed mode, the aforementioned special micro-instruction can be used to pre-check whether the memory to be accessed by the aforementioned receive instruction can be accessed. Specifically, the instruction decoding unit 230 sends the aforementioned special micro-instruction to the renaming unit 204. The renaming unit 204 sends the aforementioned special micro-instruction to the reordering buffer 240 and the reservation station 205. Then, the reservation station 205 sends it to the memory access unit 207. After receiving the aforementioned special micro-instruction, the memory access unit 207 does not perform memory access operations, but only uses the aforementioned special micro-instruction to perform permission checks on the aforementioned receive instruction to generate a check result. Specifically, the memory access unit 207 executes the aforementioned special microinstructions to perform permission checks on the received instruction and generates a check result. Then, the memory access unit 207 stores the check result in the private register 220. The check result includes a virtual address, a physical address, and an error code. If the memory cannot be accessed, the error code indicates a specific error. For example, if the error code includes a page fault code, it means that accessing the memory will result in a page fault exception. Unlike the previous embodiment, in this embodiment, in step S311, the microcode control unit 221 also stores the check result stored in the private register 220 into the system management memory. Thus, after the processor 110 enters system management mode, it can determine whether the memory can be accessed based on the error code in the check result. If the memory can be accessed, it accesses the memory using the virtual and physical addresses in the check result to obtain the source or destination operand of the received instruction. If the memory cannot be accessed, the error code in the check result is written into the system management memory. After exiting system management mode, the processor 110 enters the corresponding exception handling code based on the error code stored in the system management memory. In one embodiment, the aforementioned special microinstruction is a memory lookup microinstruction. The memory lookup microinstruction is either a memory read lookup microinstruction (ld_tickle, i.e., loadtickle) or a memory write lookup microinstruction (st_tickle, i.e., store tickle).

[0064] In another embodiment, after the memory access unit 207 performs permission checks on the received instruction using the special microinstruction described above, if the check result shows that the memory cannot be accessed, the processor 110 will directly enter the corresponding exception handling code based on the error code in the check result.

[0065] Figure 4 This is a flowchart illustrating the entry into system management mode according to an embodiment of the present invention. Figure 4 That is to Figure 1 The processing flow of the microcode processing program corresponding to system management mode entry 1142 is shown. For example... Figure 4 As shown, processor 110 disables interrupts (S401) and determines whether the simulation flag is the first value (S403). If the result of step S403 is "yes", then it enters system management mode. A detailed description is as follows: Processor 110 first executes step S401.

[0066] In step S401, processor 110 disables interrupts. As is known to those skilled in the art, interrupts are disabled in system management mode; therefore, this invention continues this architectural requirement by disabling interrupts. As for how interrupts are disabled, for example, processor 110 clears the IF flag to disable maskable interrupts, clears the TF flag to disable single-step interrupts, and clears DR7 to disable breakpoint interrupts. Then, processor 110 executes step S403.

[0067] In step S403, processor 110 determines whether the simulated identifier is the first value. Specifically, processor 110 determines whether the value stored in the simulated identifier field of private register 220 is the first value. If the determination result is "no", step S405 is executed to perform the normal processing flow for entering system management mode. Those skilled in the art will understand the normal processing flow of system management mode, and it will not be described in detail here. If the determination result is "yes", processor 110 executes step S407.

[0068] In step S407, the processor 110 sends an entry into system management mode notification (Assert#smmact) to notify the chipset processor 110 that it has entered system management mode. How to send the entry into system management mode notification is common knowledge to those skilled in the art and will not be described in detail here. Then, the processor 110 executes step S409.

[0069] In step S409, processor 110 stores the simulation identifier, the decoded information of the received instruction, and the runtime environment information into system management memory. Specifically, processor 110 reads the simulation identifier, the decoded information of the received instruction, and the runtime environment information from private register 220, and stores the read simulation identifier, the decoded information of the received instruction, and the runtime environment information into system management memory. At the same time, the contents of the architecture register (i.e., the current state of processor 110) are also stored in system management memory. As mentioned above, when the aforementioned received instruction needs to access memory, private register 220 also stores the check result of the aforementioned received instruction. Processor 110 also reads the aforementioned check result from private register 220 and stores the read check result into system management memory. The information stored in system management memory is shown in Table 1 below.

[0070] Table 1

[0071]

[0072] Then, processor 110 executes step S411 to establish a system management mode execution environment and enter system management mode. How to establish the system management mode execution environment and how to enter system management mode are common knowledge to those skilled in the art, and will not be elaborated here.

[0073] Then, processor 110 simulates the execution of the aforementioned receive instruction (such as...) in system management mode. Figure 3 Step S313 shown below). Figure 5 Describe it.

[0074] Figure 5 This is a flowchart illustrating the processing of an simulator according to an embodiment of the present invention. As previously described, processor 110 runs simulator 142 in system management mode. Figure 5 As shown, in system management mode, processor 110 establishes a simulated operating environment (S501), and then determines whether the simulated identifier is the first value (S503). If the determination result of step S503 is "yes", then it is further determined whether the above-mentioned received instruction has a decoding error (S507). If the determination result of step S507 is "no", then processor 110 generates at least one old instruction based on the basic decoding information of the above-mentioned received instruction (S509), and executes the above-mentioned at least one old instruction (S513). A detailed description is as follows: First, processor 110 executes step S501.

[0075] In step S501, processor 110 establishes a simulated runtime environment. Specifically, processor 110 reads the simulation identifier, the decoded information of the received instruction, the runtime environment information of the received instruction, and the information of the architecture registers from system management memory. When the received instruction needs to access memory, processor 110 also reads the check result from system management memory. In subsequent steps, the information read above will be used to simulate the execution of the received instruction. Then, processor 110 executes step S503.

[0076] In step S503, the processor 110 determines whether the simulated identifier is the first value. Specifically, the processor 110 determines whether the simulated identifier read in step S501 is the first value. If the determination result is "no", the processor 110 executes step S505. In step S505, the processor 110 executes the normal processing flow of the system management mode. The normal processing flow of the system management mode is common knowledge to those skilled in the art and will not be described in detail here. If the determination result of step S503 is "yes", the processor 110 executes step S507.

[0077] In step S507, the processor 110 determines whether a decoding error exists. Specifically, the runtime environment information of the received instruction read in step S501 includes the runtime environment in which the processor 110 executes the received instruction. The processor 110 determines whether the received instruction can be executed in the runtime environment. For example, the runtime environment information includes the processor 110's runtime mode. When the runtime mode is real mode, if the received instruction cannot run in real mode, the determination result of step S507 is "yes"; if the received instruction can run in real mode, the determination result of step S507 is "no". In one embodiment, the processor 110 can look up the runtime environments in which the received instruction can run based on the opcode of the received instruction using a lookup table.

[0078] In one embodiment, the lookup table is stored in the Basic Input / Output System (BIOS). As those skilled in the art will know, the BIOS is executed when the system 100, which executes the new instruction, boots up. The BIOS contains code that initializes the system management mode. When the system 100 executing the new instruction reaches the code that initializes the system management mode, it loads the lookup table into the system management memory. Then, the processor 110 can look up the opcode of the received instruction in the lookup table to determine the operating environments in which the received instruction can run.

[0079] When the processor 110 determines that there is a decoding error in the above-mentioned received instruction (the determination result of step S507 is "yes"), it executes step S511; otherwise, it executes step S509. Step S511 is described below.

[0080] In step S511, the processor 110 writes the exception to the system management memory. It should be noted that the exception is the simulated execution result of the received instruction. Specifically, the processor 110 writes the exception (i.e., the simulated execution result) to an exception vector table in the system management memory. The exception vector table is used to store partial information about the simulated execution result. The structure of the exception vector table is shown in Table 2 below. The exception vector table contains two fields: exception identifier and exception number. The exception identifier is used to store information about whether the simulated execution was successful. When the exception identifier is the first exception value, it indicates that an exception exists (i.e., the simulated execution failed); when the exception identifier is the second exception value, it indicates that no exception exists (i.e., the simulated execution succeeded). In one embodiment, the first exception value is 1, and the second exception value is 0. When the exception identifier is the first exception value, the value of the exception number field is the exception number, usually represented by an integer value. Through the exception number, the processor 110 can find and execute the microcode processing program for the aforementioned exception through the microcode control unit 221.

[0081] Table 2

[0082] Anomaly indicator Error number … …

[0083] In step S511, when the aforementioned exception is a trap, the processor 110 updates the value of the instruction pointer of the received instruction stored in the system management memory to EIP + Length, so as to point the instruction pointer of the processor 110 to the next instruction set architecture instruction to be executed. Here, EIP is the value of the instruction pointer before the update, and Length is the length of the received instruction stored in the system management memory. The instruction pointer of the received instruction in the system management memory is the value stored in the memory space corresponding to the architecture register EIP. After executing step S511, the processor 110 executes step S519, by executing the exit system management mode instruction to execute... Figure 1 The system management mode shown is exit 1144.

[0084] In step S507, when the determination result is that there is no decoding error (i.e., the determination result of step S507 is "no"), the processor 110 executes step S509.

[0085] In step S509, processor 110 generates at least one legacy instruction based on the basic decoding information of the received instruction. As mentioned above, the basic decoding information includes at least the escape code, opcode, and operand pattern of the received instruction. In one embodiment, processor 110 stores at least one legacy instruction corresponding to the received instruction in a lookup table. Then, processor 110 retrieves the at least one legacy instruction from the lookup table based on the opcode of the received instruction. In one embodiment, when the received instruction contains an escape code, processor 110 retrieves the at least one legacy instruction from the lookup table based on the escape code and opcode of the received instruction. In another embodiment, processor 110 retrieves the at least one legacy instruction from the lookup table based on the escape code, opcode, and operand pattern of the received instruction.

[0086] It is worth noting that since the at least one old instruction obtained from the lookup table does not contain other decoding information such as the source operands and / or destination operands of the received instruction, it is necessary to write other decoding information into the at least one old instruction so that it can simulate the execution of the received instruction. For example, the processor 110 writes the specific values ​​of the source operands and / or destination operands of the received instruction into the corresponding positions in the at least one old instruction. Then, the processor 110 can simulate the execution of the new instruction by executing the at least one old instruction. In one embodiment, the processor 110 writes other decoding information into the at least one old instruction based on the prefix of the received instruction.

[0087] In another embodiment, at least one legacy instruction corresponding to the aforementioned receive instruction is stored in the Basic Input / Output System (BIOS). As those skilled in the art will know, the aforementioned BIOS is executed when the system 100, which executes the new instruction, boots up. The BIOS contains code that initializes the system management mode. When the system 100 executes the code that initializes the system management mode, it loads the aforementioned at least one legacy instruction into the system management memory. Then, the processor 110 can retrieve the aforementioned at least one legacy instruction from the system management memory according to the opcode of the received instruction.

[0088] Then, processor 110 executes step S513. In step S513, processor 110 executes at least one of the aforementioned legacy instructions. Specifically, instruction decoding unit 230 decodes the at least one legacy instruction to obtain at least one microinstruction, and then processor 110 executes the at least one microinstruction. During the execution of the at least one legacy instruction, processor 110 stores intermediate operation results in system management memory. In another embodiment, processor 110 stores intermediate operation results in dedicated register set 211. Since processor 110 accesses dedicated register set 211 faster, the execution speed of the at least one legacy instruction can be accelerated.

[0089] In one embodiment, when the operand of the received instruction includes a new architecture register, the new architecture register is simulated using a dedicated register or system management memory. For example, when a descendant processor of processor 110 includes a new architecture register with a width of 1024 bits, processor 110 can simulate the new architecture register using a contiguous 1024-bit memory space in system management memory. That is, when the received instruction accesses the new architecture register, processor 110 actually accesses the contiguous 1024-bit memory space in system management memory. In another embodiment, when a descendant processor of processor 110 includes a new architecture register with a width of 1024 bits, processor 110 can simulate the new architecture register using a dedicated register with a width of 1024 bits in dedicated register set 211. That is, when the received instruction accesses the new architecture register, processor 110 actually accesses the dedicated register with a width of 1024 bits in dedicated register set 211. In another embodiment, when the dedicated register set 211 contains only dedicated registers with a width of 512-bit, two dedicated registers with a width of 512-bit are needed to simulate one newly added architecture register with a width of 1024-bit. In summary, the present invention does not limit this, and the processor 110 can use one or more dedicated registers to simulate one newly added architecture register.

[0090] When the newly added architecture register is the destination operand of the received instruction, after executing at least one of the old instructions (i.e., after simulating the execution of the received instruction), the processor 110 stores the simulated execution result of the received instruction into the dedicated register or the system management memory. Furthermore, the simulated execution result is retained in the dedicated register or the system management memory and will not be overwritten during the processor 110's entry / exit from system management mode. Thus, when the processor 110 executes another instruction, and that other instruction is also a newly added instruction, and the newly added architecture register is the source operand of that other instruction, the processor 110 directly uses the simulated execution result stored in the dedicated register or the system management memory when simulating the execution of that other instruction. It should be noted that the received instruction and the other instruction can be consecutive or non-consecutive; this invention does not impose any limitations on this.

[0091] In system management mode, processor 110 can only access system management memory and cannot access system memory in a normal memory access manner. In one embodiment of the present invention, a physical memory direct access interface is provided to enable memory access operations in system management mode. When the received instruction contains memory operands, the memory operands can be accessed through the physical memory direct access interface. The steps for accessing memory operands through the physical memory direct access interface are as follows:

[0092] The first step is for the processor 110 to translate the virtual address of the aforementioned memory operand into a physical address. Specifically, the processor 110 uses the physical memory direct access interface to access the page table and translate the virtual address of the aforementioned memory operand into a physical address. The steps for translating the virtual address into a physical address are as follows: 1. Read the page table base address stored in the architecture register CR3 from the system management memory; 2. Perform a page table lookup based on the page table base address and the virtual address, and after simulating the page table lookup process, obtain the physical address.

[0093] The second step involves the processor 110 reading the value of the memory operand from the aforementioned physical address, which is not located in system management memory. Specifically, the processor 110 reads the value of the memory operand from the aforementioned physical address via a Model Specific Register (MSR). The specific steps are as follows:

[0094] Step 1: The processor 110 writes the address of the aforementioned model special register into a first register (ECX) and writes the aforementioned physical address into a second register (EDX:EAX).

[0095] Step 2: Processor 110 executes a Write Model Special Register (WRMSR) instruction to store the value of the aforementioned memory operand into the aforementioned model special register. Specifically, after processor 110 executes the Write Model Special Register instruction, the aforementioned physical address is written into the aforementioned model special register. Then, processor 110 uses the aforementioned physical address stored in the aforementioned model special register to load the value of the aforementioned memory operand from system memory into the aforementioned model special register by executing a Load from Physical Address microinstruction (ld_phys).

[0096] Step 3, the processor 110 executes the Read Model Special Register (RDMSR) instruction to read the value of the memory operand from the aforementioned model special register and stores the read value of the memory operand into the aforementioned second register.

[0097] After executing step S513, processor 110 executes step S515. In step S515, processor 110 determines whether a runtime exception exists. If a runtime exception occurs during the execution of step S513, the result is "yes"; otherwise, the result is "no". When the result of S515 is "yes", processor 110 executes step S511. Step S511 has already been described above and will not be repeated here. When the result of S515 is "no", processor 110 executes step S517.

[0098] In step S517, processor 110 writes the simulated execution result to system management memory. Specifically, first, processor 110 writes the second exception value (indicating no exception) to the exception identifier field of the exception vector table in system management memory, as shown in Table 2 above. Then, processor 110 writes the simulated execution result of the above-mentioned receive instruction to the area corresponding to the architecture register in system management memory. For example, if the simulated execution result of the above-mentioned receive instruction is to change the value of the architecture register ECX to 10H (hexadecimal number, the same below), then processor 110 writes the value 10H to the storage space corresponding to the architecture register ECX in system management memory. Finally, processor 110 updates the value of the instruction pointer of the above-mentioned receive instruction stored in system management memory to: EIP + Length, so as to point the instruction pointer of processor 110 to the next instruction set architecture instruction to be executed, where EIP is the value of the instruction pointer before the update, and Length is the length of the above-mentioned receive instruction. The instruction pointer of the above-mentioned receive instruction in system management memory is the storage space corresponding to the architecture register EIP. When exiting system management mode, the value in the space corresponding to the architecture register in system management memory will be written into the corresponding architecture register to send the simulated execution result of the new instruction to application 130 or operating system 120, which will be described in detail later.

[0099] Then, processor 110 executes step S519. In step S519, processor 110 executes the Resume from System Management mode instruction. After executing the Resume from System Management mode instruction, processor 110 will execute as follows: Figure 1 The microcode processing program for system management mode exit 1144 shown below will be combined with... Figure 7 It will be explained in detail.

[0100] Figure 6 This is an example illustrating the simulation of receiving instructions in system management mode according to an embodiment of the present invention. Figure 6 It demonstrates how to implement such a thing in the form of pseudocode. Figure 5 The simulated execution of the instruction receiving process shown is a specific implementation of the simulator.

[0101] like Figure 6 As shown, lines 1-20 contain the code for the simulator's main function, `simulator_start`. Lines 21-30 contain the code for the simulation function `Unsupport_X_handle`, which implements the new instruction functionality and includes at least one old instruction corresponding to the received instruction mentioned earlier. The main function `simulator_start` will be described first.

[0102] In the main function `simulator_start`, line 3 of the code is executed first. Line 3 completes. Figure 5 Step S501 involves the processor 110 establishing a simulated runtime environment. In line 3, the processor 110 uses the function `setup_simulator_env` to establish the simulated runtime environment. After executing line 3, the processor 110 saves the simulation flag, decoded instruction information, runtime environment information, architecture register information, and check results read from system management memory into the variable `env`. For example, in line 4, the value of the simulation flag is accessed via `env.emulation_flag`. Line 4 completes... Figure 5 In step S503, the processor 110 determines whether the analog identifier is the first value. If the result of the determination in line 4 is that the analog identifier is not the first value, then line 5 is executed. Line 5 completes. Figure 5 Step S505 functions as follows: processor 110 executes the normal processing flow of system management mode. In line 5, processor 110 enters the normal processing flow of system management mode by executing the function `exit_to_normal_SMM`. If the result of the judgment in line 4 is that the simulation flag is the first value, then lines 7-8 are executed. Lines 7-8 are then completed. Figure 5 The function of step S507 is for processor 110 to determine whether a decoding exception exists. In line 7, processor 110 checks and obtains the decoding exception value decode_excep of the received instruction by executing the function check_decode_excep. In line 8, processor 110 determines whether a decoding exception exists based on the value of decode_excep. If a decoding exception exists, line 9 is executed. Line 9 completes. Figure 5 In step S511, the processor 110 writes the exception to the system-managed memory. In line 9, the processor 110 uses the `set_exception` function to write the exception to the system-managed memory in the format described in Table 2. After executing line 9, the processor executes line 10, then jumps to line 18. In line 10, the processor 110 uses the `goto` instruction to jump to the location of label `out` (i.e., line 18). Then execution continues from line 18. Since line 18 only has label `out` and no code to execute, the processor 110 executes line 19. Line 19 is then completed. Figure 5 The function of step S519 is that processor 110 executes the instruction to exit system management mode. In line 19, processor 110 executes the instruction to exit system management mode through the function execute_rsm. Subsequently, processor 110 will execute as follows: Figure 1 The microcode for system management mode exit 1144 is shown.

[0103] If the result of the conditional statement in line 8 is that no decoding exception exists, then the code in line 12 will be executed. Line 12 completes. Figure 5 The function of step S509 is that the processor 110 generates at least one old instruction based on the basic decoding information of the received instruction. For example... Figure 6 As shown, in line 12, the at least one old instruction is retrieved from the `op_mapping` table using the opcode for receiving the instruction. A pointer `routine` represents this at least one old instruction, and its value is the address of the `Unsupport_X_handle` function. Then, line 13 is executed. Line 13 completes. Figure 5 The function of step S513 is that processor 110 executes at least one legacy instruction. When executing `routine()`, processor 110 actually executes the simulated function `Unsupport_X_handle` (described in detail later). After executing the `routine`, the simulation execution result is stored in `runtime_excep`. Then, the code on line 14 is executed. Line 14 completes. Figure 5 The function of step S515 is for processor 110 to determine whether a runtime exception exists. In line 14, processor 110 determines whether a runtime exception exists based on the value of runtime_excep, the result of the simulated execution. If a runtime exception exists, line 15 is executed. In line 14, processor 110 uses the function set_exception to store the runtime exception in the format described in Table 2 above into system management memory. Then, processor 110 executes line 16, jumping to line 18 via the goto instruction. As mentioned earlier, processor 110 will then execute line 19. The function of line 19 has been described previously and will not be repeated here.

[0104] The following describes the simulation function Unsupport_X_handle.

[0105] In the simulated function `Unsupport_X_handle`, lines 23-24 are executed first. These lines read the operand's value, storing it in the array `op`. In line 24, the processor uses the function `read_op` to read the operand. Specifically, `read_op` retrieves the operand's value from the previously mentioned `env` variable. Line 25 then completes... Figure 5The function of step S513 is that processor 110 executes at least one of the aforementioned old instructions, that is, processor 110 simulates the execution of the aforementioned receive instruction. In line 25, op represents the operand of the aforementioned receive instruction, and operate with op means writing the value of the operand of the aforementioned receive instruction into the aforementioned at least one old instruction and executing the aforementioned at least one old instruction. During the execution of line 25, if a runtime exception occurs, the code on line 26 completes... Figure 5 The function of step S511 is that processor 110 writes the exception to system management memory; if no runtime exception occurs, line 26 completes the process. Figure 5 The function of step S517 is that processor 110 writes the simulation execution result into system management memory. In line 26, processor 110 uses the function `write_result_to_SMRAM` to store the simulation execution result in the format described in Table 2 above into system management memory. Line 27 checks whether a runtime exception occurred during the execution of line 25. If a runtime exception occurred, line 28 is executed to send the exception information to the main function; otherwise, line 29 is executed to send the correct execution information to the main function. In lines 28 and 29, processor 110 uses the `return` instruction to send either the exception information or the correct execution information to the main function `simulator_start`.

[0106] Figure 7 This is a flowchart illustrating the exit from system management mode according to an embodiment of the present invention. Figure 7 That is to Figure 1 The processing flow of the microcode processing program corresponding to system management mode exit 1144 is shown. For example... Figure 7 As shown, when exiting system management mode, processor 110 determines whether the simulation identifier is the first value (S701). If the determination result is "yes", processor 110 determines whether there is an exception in the simulation execution result (S705). Processor 110 performs the operation of exiting system management mode according to whether there is an exception in the simulation execution result and the type of exception. A detailed description is as follows: Processor 110 first executes step S701.

[0107] In step S701, the processor 110 determines whether the simulated identifier is a first value. Specifically, the processor 110 reads the simulated identifier from the system management memory and then determines whether the read simulated identifier is the first value. If the simulated identifier is not the first value, the processor 110 executes step S703. In step S703, the processor 110 executes the normal process for exiting the system management mode. The normal process for exiting the system management mode is common knowledge to those skilled in the art and will not be described in detail here. If the simulated identifier is the first value, the processor 110 executes step S705.

[0108] In step S705, the processor 110 determines whether there is an anomaly in the simulation execution result. Specifically, the processor 110 reads the anomaly vector table shown in Table 2 above from the system management memory. If the value of the anomaly identifier field in the anomaly vector table is the first anomaly value, it indicates that there is an anomaly in the simulation execution result, and the judgment result is "yes"; if the value of the anomaly identifier field in the anomaly vector table is the second anomaly value, it indicates that there is no anomaly in the simulation execution result, and the judgment result is "no". If the judgment result is "no", the processor 110 executes step S707.

[0109] In step S707, processor 110 stores the simulated execution results stored in system management memory into the architecture register. As mentioned above, in Figure 5 In step S517, the processor 110 has written the simulated execution result of the aforementioned receive instruction into the area corresponding to the architecture register in the system management memory. In this step, the processor 110 stores the value in the area corresponding to the architecture register in the system management memory into the architecture register. This is equivalent to the processor 110 having completed executing the aforementioned receive instruction.

[0110] If the destination operand of the aforementioned received instruction is a new architecture register, since the processor 110's architecture register does not contain a new architecture register, the processor 110 will not store the simulated execution result from the region in system management memory simulating the new architecture register or the dedicated register simulating the new architecture register into the architecture register. As mentioned earlier, when the processor 110 simulates the execution of another new instruction, and the operand of the other new instruction is also the aforementioned new architecture register, the processor 110 can directly use the value stored in the region in system management memory simulating the aforementioned new architecture register or the value stored in the dedicated register simulating the aforementioned new architecture register to simulate the execution of the other new instruction.

[0111] Then, processor 110 executes step S709. In step S709, processor 110 enables interrupts. For example, processor 110 sets the IF flag to enable maskable interrupts, sets the TF flag to enable single-step interrupts, and sets DR7 to enable breakpoint interrupts. Then, processor 110 executes step S711.

[0112] In step S711, the processor 110 sends an exit system management mode notification (Deassert#smmact) to notify the chipset processor 110 that it has exited system management mode. Then, the processor 110 executes step S713 to exit system management mode.

[0113] When the processor 110 determines that there is an abnormality in the simulation execution result in step S705, it executes step S715.

[0114] In step S715, the processor 110 determines whether the exception type is a trap. Specifically, the processor 110 determines whether the exception in the simulated execution result is a trap based on the exception number in the exception vector table read from the system management memory in step S705. For example, when the exception identifier is the first exception value and the exception number is 3 (as shown in Table 2-1 below), it indicates an overflow exception. The overflow exception is a trap, so the determination result is "yes". When the exception identifier is the first exception value and the exception number is 0 (as shown in Table 2-2 below), it indicates a division error exception. The division error exception is a fault, not a trap, so the determination result is "no".

[0115] Table 2-1

[0116] Anomaly indicator Error number 1 3

[0117] Table 2-2

[0118] Anomaly indicator Error number 1 0

[0119] When the judgment result of step S715 is "no", the processor 110 executes steps S717, S719, and S721. Steps S717 and S719 are the same as steps S709 and S711, respectively, and will not be described again here. Step S721 is described below.

[0120] In step S721, the processor 110 executes the microcode handling program for the exception. Specifically, the processor 110 determines whether an exception has occurred based on the exception identifier in the exception vector table stored in the system management memory. If an exception has occurred, the processor 110 executes the microcode handling program for the exception based on the exception number stored in the exception vector table. That is, it executes the microcode handling program for the exception corresponding to the exception number. For example, when the exception identifier in the exception vector table stored in the system management memory is the first exception value, it indicates that there is an exception in the simulation execution result. If the exception number in the exception vector table is 0 at this time, it indicates that the exception is a division error, and the processor 110 will execute the microcode handling program for the division error.

[0121] In step S715, when the judgment result is "yes," meaning the exception type of the simulated execution result is a trap, the processor 110 executes steps S723, S725, S727, and S729. Steps S723, S725, and S727 are the same as steps S707, S709, and S711, respectively, and will not be repeated here. Step S729 is described below.

[0122] In step S729, processor 110 executes the microcode handler for the exception. For example, when an exception occurs in the simulation execution result, and the exception is an overflow exception, processor 110 executes the microcode handler for the overflow exception.

[0123] [Second Embodiment]

[0124] In the second embodiment, the processor 110 passes the emulation identifier to the pipeline, and the instruction monitoring unit determines whether the received instruction is a new instruction based on the machine code of the received instruction from the instruction cache. The following is in conjunction with... Figure 2B , Figure 2B1 and Figure 3-7 The second embodiment is described.

[0125] Figure 2B Chinese numbering and Figure 2A The same module has the same function as Figure 2A The corresponding modules have the same function, so they will not be described again here. The second embodiment is described below. Figure 2B Compared with the first embodiment Figure 2A The differences.

[0126] like Figure 2B As shown, the instruction monitoring unit 210B directly receives instructions from the instruction cache 202B. Then, the instruction monitoring unit 210B decodes the received instructions to generate decoding information. Next, the instruction monitoring unit 210B determines whether the received instruction is a new instruction based on the decoding information and generates a simulated identifier. Then, the instruction monitoring unit 210B sends the simulated identifier to the renaming unit 204 and the private register 220B. When the simulated identifier is the first value, the instruction monitoring unit 210B also stores the decoded information and runtime environment information into the private register 220B. The following is in conjunction with... Figure 2B1 The instruction monitoring unit 210B is described in detail.

[0127] like Figure 2B1 As shown, the instruction monitoring unit 210B includes an instruction parsing unit 2101B and an instruction judgment unit 2102B. The instruction parsing unit 2101B decodes the received instruction from the instruction cache 202B to generate decoding information. Then, the instruction parsing unit 2101B sends the decoded information to the instruction judgment unit 2102B. The instruction judgment unit 2102B determines whether the received instruction is a new instruction based on the decoded information and generates a simulated identifier. Then, the instruction judgment unit 2102B sends the simulated identifier to the private register 220B and the renaming unit 204. The private register 220B stores the simulated identifier. When the simulated identifier is a first value, the private register 220B also stores the decoded information of the received instruction from the instruction parsing unit 2101B.

[0128] In the second embodiment, in Figure 3 In step S307, unlike the first embodiment, the processor 110 directly decodes the received instruction through the instruction monitoring unit 210B and determines whether the received instruction is a new instruction based on the decoding information. In the second embodiment, Figure 3 Other steps and Figure 4-7 The steps in this embodiment are the same as those in the first embodiment, and will not be repeated here.

[0129] In summary, unlike the first embodiment, in this embodiment, the instruction monitoring unit 210B directly reads the machine code of the received instruction from the instruction cache 202B. Then, the instruction monitoring unit 210B parses the read machine code and generates decoding information. Next, the instruction monitoring unit 210B determines whether the received instruction is a new instruction based on the decoding information. When the received instruction is a new instruction, the instruction monitoring unit 210B generates a simulated identifier with a first value. Then, the instruction monitoring unit 210B sends the generated simulated identifier to the renaming unit 204 and sends the decoding information to the private register 220B. Compared to the first embodiment, this embodiment directly parses the machine code from the instruction cache 202B, eliminating the need to modify the instruction decoding unit 230B, thus making it relatively easy to implement.

[0130] [Third Embodiment]

[0131] In the third embodiment, the processor 110 does not pass the analog identifier into the pipeline, and the instruction monitoring unit determines whether the received instruction is a new instruction based on the instruction information of the received instruction from the instruction decoding unit. The following is in conjunction with... Figure 2C as well as Figure 3-7 The third embodiment is described.

[0132] Figure 2C Chinese numbering and Figure 2A The same module has the same function as Figure 2A The corresponding modules have the same function, so they will not be described in detail here. The difference between the third embodiment and the first embodiment is that in the third embodiment, the instruction monitoring unit 210C does not send the emulation identifier to the renaming unit 204C. The third embodiment will now be described in detail. Figure 2C Compared with the first embodiment Figure 2A The differences.

[0133] like Figure 2CAs shown, the instruction monitoring unit 210C determines whether the received instruction is a new instruction and generates a simulation flag. Then, the instruction monitoring unit 210C stores the simulation flag in the private register 220. When the simulation flag is the first value, the private register 220 also stores the decoding information of the received instruction from the instruction decoding unit 230 and the runtime environment information.

[0134] After decoding the received instruction, the instruction decoding unit 230 generates decoding information. Based on this decoding information, the instruction decoding unit 230 generates microinstructions. As is known to those skilled in the art, when the received instruction is not an old instruction, the microinstruction contains an unknown instruction identifier (UD) with a first value. Then, the renaming unit 204C receives the microinstruction from the instruction decoding unit 230, renames it, and sends it to the rearrangement buffer 240C. When the instruction submission unit 245C submits the microinstruction, if the unknown instruction identifier in the microinstruction is the first value, an unknown instruction exception is generated. In response to the unknown instruction exception, the microcode control unit 221C executes the microcode processing procedure for the unknown instruction exception. In the microcode processing procedure for the unknown instruction exception, the processor 110 determines whether the analog identifier in the private register 220 is the first value. If the analog identifier in the private register 220 is the first value, the processor 110 issues a system management interrupt. The subsequent processing flow is the same as in the first embodiment and will not be described again here.

[0135] Unlike the first embodiment, in the third embodiment, in Figure 3 In steps S307 and S309, the instruction monitoring unit 210C does not send the generated analog identifier to the renaming unit 204C. In the third embodiment, Figure 3 Other steps and Figure 4-7 The steps in this embodiment are the same as those in the first embodiment, and will not be repeated here.

[0136] In summary, unlike the first and second embodiments, in this embodiment, after the instruction monitoring unit 210C generates the emulated identifier, it only sends the emulated identifier to the private register 220 and does not send it to the renaming unit 204C or the rearrangement buffer 240C. Since the instruction entries in the rearrangement buffer 240C do not contain the emulated identifier, the instruction submission unit 245C can only issue an unknown instruction exception based on the unknown instruction identifier. In the microcode handler for processing the unknown instruction exception, the processor 110 issues a system management interrupt based on the emulated identifier stored in the private register 220. Compared to the first and second embodiments, this embodiment does not require modification of the renaming unit and the rearrangement buffer, and is therefore relatively easy to implement.

[0137] [Fourth Embodiment]

[0138] In the fourth embodiment, the processor 110 does not pass the analog identifier into the pipeline. The instruction monitoring unit determines whether the received instruction is a new instruction based on the machine code of the received instruction from the instruction cache. The following is in conjunction with... Figure 2D , Figure 2D1 as well as Figure 3-7 The fourth embodiment is described.

[0139] Figure 2D Chinese numbering and Figure 2A The same module has the same function as Figure 2A The corresponding modules have the same function, so they will not be described in detail here. The difference between the fourth embodiment and the third embodiment is that in the fourth embodiment, the instruction monitoring unit 210D directly obtains the received instruction from the instruction cache 202D and determines whether the received instruction is a new instruction. Figure 2D Modules 204D, 240D, 245D, and 221D are respectively with Figure 2C Modules 204C, 240C, 245C, and 221C are the same, and will not be described again here. The fourth embodiment will be described in detail below. Figure 2D Compared with the first embodiment Figure 2C The differences.

[0140] like Figure 2D As shown, the instruction monitoring unit 210D directly receives instructions from the instruction cache 202D. Then, the instruction monitoring unit 210D decodes the received instructions to generate decoding information. Next, the instruction monitoring unit 210D determines whether the received instruction is a new instruction based on the decoding information and generates a simulated identifier. Then, the instruction monitoring unit 210D sends the simulated identifier to the private register 220D. When the simulated identifier is the first value, the instruction monitoring unit 210D also stores the decoding information and runtime environment information into the private register 220D. The following is a combination of... Figure 2D1 The instruction monitoring unit 210D is described in detail.

[0141] like Figure 2D1As shown, the instruction monitoring unit 210D includes an instruction parsing unit 2101D and an instruction judgment unit 2102D. The instruction parsing unit 2101D decodes the received instruction from the instruction cache 202D to generate decoded information. Then, the instruction parsing unit 2101D sends the decoded information to the instruction judgment unit 2102D. The instruction judgment unit 2102D determines whether the received instruction is a new instruction based on the decoded information and generates a simulated identifier. Then, the instruction judgment unit 2102D sends the simulated identifier to a private register 220D. The private register 220D stores the simulated identifier. When the simulated identifier is a first value, the private register 220D also stores the decoded information of the received instruction from the instruction parsing unit 2101D.

[0142] In the fourth embodiment, Figure 3 In step S307, unlike in the third embodiment, the processor 110 directly decodes the received instruction through the instruction monitoring unit 210D and determines whether the received instruction is a new instruction based on the decoding information. In the fourth embodiment, Figure 3 Other steps and Figure 4-7 The steps in this embodiment are the same as those in the third embodiment, and will not be repeated here.

[0143] In summary, similar to the third embodiment, and compared to the first and second embodiments, the instruction monitoring unit in this embodiment does not need to send the analog identifier to the renaming unit and the rearrangement buffer, so there is no need to modify the renaming unit and the rearrangement buffer, making it relatively easy to implement. Furthermore, unlike the third embodiment, in this embodiment, the instruction monitoring unit 210D directly reads the machine code of the received instruction from the instruction cache 202D. Then, the instruction monitoring unit 210D parses the received machine code and generates decoding information. Then, the instruction monitoring unit 210D determines whether the received instruction is a new instruction based on the decoding information. When the received instruction is a new instruction, the instruction monitoring unit 210D generates an analog identifier with a first value. Then, the instruction monitoring unit 210D sends the decoding information to the private register 220D. Compared to the third embodiment, this embodiment directly parses the machine code from the instruction cache 202D, eliminating the need to modify the instruction decoding unit 230D, thus making it relatively easy to implement.

[0144] It is worth noting that the aforementioned four embodiments all achieve the function of entering and exiting the simulator 142 by modifying the existing code for entering and exiting the system management mode. In another embodiment, dedicated code for entering and exiting the system management mode can be added to the system 100 that executes the new instruction, and a new system management interrupt number can be defined. Then, by calling the newly added system management interrupt number, the newly added dedicated code for entering the system management mode is executed. In the newly added dedicated code for entering the system management mode, the processor 110 writes a dedicated entry identifier with a first value to the system management memory, and then enters the system management mode. In the system management mode, the processor 110 executes the simulator 142 to simulate the execution of the new instruction. After simulating the execution of the new instruction, the simulator 142 determines whether the dedicated entry identifier in the system management memory is the first value. If the dedicated entry identifier is the first value, the simulator 142 executes the newly added dedicated code for exiting the system management mode. In one embodiment, the simulator 142 executes the newly added dedicated code for exiting the system management mode by calling or jumping.

[0145] All the functions described in the first, second, third, and fourth embodiments can be implemented based on the newly added dedicated code for entering and exiting the system management mode. To achieve better performance, when implementing the functions of the four embodiments based on the newly added dedicated code for entering and exiting the system management mode, the following can be deleted: Figure 4 and Figure 7 The step of determining whether the simulated identifier is the first value is omitted. This is because the code for entering and exiting system management mode does not need to consider the normal system management mode processing code. For example, it can be deleted. Figure 4 In steps S403 and S405, delete Figure 7 Steps S701 and S703 in the process. Additionally... Figure 4 Step S409 needs to be modified to "store the analog identifier, the dedicated entry identifier, the decoding information of the received instruction, and the operating environment information into the system management memory". Figure 5 Step S519 needs to be changed to "When the dedicated entry identifier is the first value, execute the newly added dedicated code to exit the system management mode; otherwise, execute the exit system management mode instruction". Figure 6 Line 19 of the code needs to be changed to: "if(newEntryFlag==1)execute_newExit();else execute_rsm();", where newEntryFlag is a dedicated entry point identifier, and execute_newExit() represents the execution of the newly added dedicated code for exiting the system management mode.

[0146] As can be seen from the above description, the revised version Figure 4 The processing flow for code specifically designed to enter system management mode; modified Figure 7 A dedicated code flow for exiting system management mode; modified Figure 5 The processing flow of emulator 142 when using dedicated code to enter and exit system management mode; modified Figure 6 This example demonstrates the simulation of executing new commands when using dedicated code to enter and exit system management mode. The modified versions are described below. Figure 4 Step S409 and the modified Figure 5 Step S519.

[0147] In the revised Figure 4 In step S409, processor 110 stores the analog identifier, the dedicated entry identifier, the decoded information of the received instruction, and the runtime environment information into the system management memory. Specifically, processor 110 generates an analog identifier and a dedicated entry identifier with a first value, and writes the generated analog identifier and dedicated entry identifier into the system management memory. Additionally, processor 110 reads the decoded information of the received instruction and the runtime environment information from private register 220, and writes the read decoded information of the received instruction and runtime environment information into the system management memory.

[0148] In the revised Figure 5 In step S519, when the dedicated entry identifier is the first value, the processor 110 executes the newly added dedicated code for exiting system management mode; otherwise, the processor 110 executes the instruction to exit system management mode. Specifically, the processor 110 reads the dedicated entry identifier from system management memory and determines whether the read dedicated entry identifier is the first value. When the dedicated entry identifier is the first value, the processor 110 executes the newly added dedicated code for exiting system management mode; otherwise, the processor 110 executes the instruction to exit system management mode. It is worth noting that the modified... Figure 6 The function performed by line 19 is the function of this step.

[0149] In summary, compared with using the original code for entering and exiting system management mode, using dedicated code for entering and exiting system management mode allows those skilled in the art to optimize the code, thus achieving higher execution efficiency.

[0150] Figure 8 This is a flowchart illustrating the execution of a newly added instruction according to an embodiment of the present invention. For example... Figure 8As shown, processor 110 receives an instruction (S801) and determines whether the received instruction is a new instruction (S803). When the received instruction is a new instruction, processor 110 enters system management mode (S805), and in system management mode, it simulates the execution of the received instruction by executing at least one old instruction (S807).

[0151] exist Figure 8 In step S801 and Figure 3 Step S301 is the same; step S803 is the same. Figure 3 Step S307 is the same; step S805 is the same. Figure 3 Step S311 is the same; step S807 is the same. Figure 3 Step S313 is the same; step S809 is the same. Figure 3 The steps are the same as in step S305. Therefore, the above steps will not be described again here.

[0152] Figure 9 This is a flowchart illustrating the execution of a newly added instruction according to another embodiment of the present invention. For example... Figure 9 As shown, processor 110 receives an instruction (S901) and determines whether the received instruction is a new instruction (S903). When the received instruction is a new instruction, processor 110 generates a simulation flag (S905). Then, processor 110 issues a system management interrupt based on the simulation flag (S907). In response to the system management interrupt, processor 110 enters a system management mode (S909), simulates the execution of the received instruction in this system management mode, generates a simulation execution result (S911), and stores the simulation execution result in a system management memory (S912).

[0153] exist Figure 9 In the middle, step S901 and Figure 3 Step S301 is the same; step S903 is the same. Figure 3 Step S307 is the same; step S909 is the same. Figure 3 Step S311 is the same; step S912 is the same. Figure 5 Step S517 is the same; step S913 is the same. Figure 3 Step S305 is the same. Therefore, steps S901, S903, S909, S912, and S913 will not be described again here. Steps S905, S907, and S911 will be described below.

[0154] In step S905, the processor 110 generates a simulated identifier. Specifically, the simulated identifier is generated when the instruction monitoring unit 210 determines that the received instruction is a new instruction. For details on generating the simulated identifier, please refer to the previous section. Figure 2A , Figure 2B, Figure 2C and Figure 2D The relevant descriptions of the instruction monitoring units 210, 210B, 210C, and 210D in the document, and refer to the previous descriptions... Figure 3 The relevant description of step S309 will not be repeated here.

[0155] In step S907, the processor 110 issues a system management interrupt based on the aforementioned emulation identifier. For details on how to issue the system management interrupt based on the emulation identifier, please refer to the previous descriptions of steps S403 and S407; they will not be repeated here.

[0156] In step S911, the processor 110, in system management mode, simulates the execution of the receive instruction and generates a simulated execution result. Specifically, the processor 110 generates at least one old instruction based on the basic decoding information of the receive instruction, and then simulates the execution of the receive instruction by executing the at least one old instruction, generating a simulated execution result. For a more detailed description, please refer to the preceding section... Figure 5 The description of steps S509 and S513.

[0157] Figure 10 This is a flowchart illustrating the execution of a newly added instruction according to another embodiment of the present invention. For example... Figure 10 As shown, processor 110 receives an instruction (S1001) and determines whether the instruction is a new instruction based on its opcode (S1003). If the instruction is a new instruction, processor 110 stores the basic decoding information of the instruction into a private register (S1005). Then, processor 110 enters system management mode (S1006) and simulates the execution of the instruction based on the basic decoding information stored in the private register (S1007).

[0158] exist Figure 10 In the middle, step S1001 and Figure 3 Step S301 is the same; step S1003 is the same as... Figure 3 Step S307 is the same; step S1006 is the same as... Figure 3 Step S311 is the same; step S1007 is the same as... Figure 3 Step S313 is the same; step S1009 is the same as... Figure 3 Step S305 is the same. Therefore, the above steps will not be described again here. Step S1005 is described below.

[0159] In step S1005, the processor 110 stores the basic decoding information of the received instruction into a private register. For specific implementation details, please refer to the previous section. Figure 2A , Figure 2B , Figure 2C and Figure 2D The relevant descriptions of the instruction monitoring units 210, 210B, 210C, and 210D in the document, and refer to the previous descriptions... Figure 3 The relevant description of step S309 will not be repeated here.

[0160] The method and system for executing new instructions provided by this invention allow for the implementation of newly added instructions in later-generation processors on previous-generation processors without modifying the processor's microarchitecture. This significantly reduces the workload for design, testing, and other tasks, thus saving substantial costs.

[0161] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. A method for executing a newly added instruction, characterized in that, Include: Receive instructions; The opcode of the received instruction determines whether it is a new instruction. A new instruction is one that cannot be recognized by the processor and is only supported by its successor processors. When the received instruction is a new instruction: The basic decoded information of the received instruction is stored in a private register, wherein the basic decoded information includes the opcode; and Enter system management mode, and simulate the execution of the receive instruction based on the basic decoding information stored in the private register in system management mode, wherein interrupts are disabled in system management mode.

2. The method for executing a new instruction as described in claim 1, further comprising, when the received instruction is a new instruction: The received command is decoded to obtain its basic decoding information; and The basic decoding information is read from the private register and stored in the system management memory.

3. The method for executing a new instruction as described in claim 1, further comprising, when the received instruction is a new instruction: Set the simulation flag in the private register to the first value; and Enter the system management mode based on the simulation identifier in the private register.

4. The method for executing a new instruction as described in claim 1, wherein when the received instruction is a new instruction, the method for executing the new instruction further comprises: If the receive instruction requires memory access, then the receive instruction is decoded into special micro-instructions, where, This special microinstruction contains a simulated identifier; When the simulated identifier of this special micro-instruction is the first value, the special micro-instruction is used to perform an authorization check on the received instruction and generate a check result. as well as The result of the inspection is stored in the private register.

5. The method for executing a new instruction as described in claim 1, wherein, When the receive instruction is a new instruction and the operand of the receive instruction is a new architecture register, in the system management mode, the new architecture register is simulated using a dedicated register or system management memory.

6. The method for executing a new instruction as described in claim 5, further comprising, when the new architecture register is the destination operand of the received instruction: After the simulated execution of the receive instruction is completed, the simulated execution result of the receive instruction is stored in the dedicated register or the system management memory.

7. The method for executing a new instruction as described in claim 6, further comprising, when the new architecture register is the destination operand of the received instruction: When exiting the system management mode, the simulation execution result stored in the dedicated register or the system management memory is not stored in the architecture register.

8. The method for executing a new instruction as described in claim 6, further comprising: Receive another instruction; and When the other instruction is a new instruction and the new architecture register is the source operand of the other instruction, the execution of the other instruction can be simulated directly using the special register or the simulated execution result stored in the system management memory.

9. The method for executing a new instruction as described in claim 1, further comprising: The received instruction is decoded into micro-instructions, where, This microinstruction contains a simulated identifier; Based on the simulated identifier of the microinstruction, a system management interrupt is initiated; and The system management mode has been entered due to a system management interruption.

10. The method for executing a new instruction as described in claim 9, further comprising, when the received instruction is a new instruction: When the microinstruction is submitted, a system management interrupt is initiated based on the simulation identifier of the microinstruction.

11. A system for executing newly added instructions, characterized in that, Include: The instruction monitoring unit receives an instruction and determines whether the received instruction is a new instruction based on the opcode of the received instruction. The new instruction is an instruction that cannot be recognized by the processor and is only supported by the processor's successor processors. as well as When the received instruction is a new instruction, the instruction decoding unit stores the basic decoding information of the received instruction into a private register. The system executing the new instruction enters the system management mode and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode. The basic decoding information includes the opcode. Interrupts are disabled in the system management mode.

12. The system for executing new instructions as described in claim 11, wherein when the received instruction is a new instruction, the instruction decoding unit decodes the received instruction to obtain the basic decoding information of the received instruction, and the system for executing new instructions reads the basic decoding information from the private register and stores the read basic decoding information into the system management memory.

13. The system for executing a new instruction as described in claim 11, further comprising, when the received instruction is a new instruction: The system executing the new instruction sets the simulation flag in the private register to the first value and enters the system management mode based on the simulation flag in the private register.

14. The system for executing the new instruction as described in claim 11, further comprising: In the memory access unit, when the received instruction is an add instruction, if the received instruction needs to access memory, the system executing the add instruction decodes the received instruction into special micro-instructions, wherein... The special microinstruction contains a simulated identifier; when the simulated identifier of the special microinstruction is a first value, the memory access unit uses the special microinstruction to perform an access permission check on the received instruction, generates a check result, and stores the check result in the private register.

15. The system for executing the new instruction as claimed in claim 11, further comprising: In the case of a special-purpose register, when the receive instruction is a new instruction and the operand of the receive instruction is a new architecture register, the new architecture register is simulated using the special-purpose register or system management memory in the system management mode.

16. The system for executing new instructions as described in claim 15, wherein, When the newly added architecture register is the destination operand of the receive instruction, after the system executing the newly added instruction completes the simulation of the receive instruction, the simulation execution result of the receive instruction is stored in the dedicated register or the system-managed memory.

17. The system for executing new instructions as claimed in claim 16, wherein, When the newly added architecture register is the destination operand of the received instruction, the system executing the new instruction will not store the simulated execution result stored in the dedicated register or the system management memory into the architecture register when exiting the system management mode.

18. The system for executing new instructions as described in claim 16, wherein, The instruction monitoring unit receives another instruction; when the other instruction is a new instruction and the new architecture register is the source operand of the other instruction, the system executing the new instruction directly uses the dedicated register or the simulated execution result stored in the system management memory to simulate the execution of the other instruction.

19. The system for executing new instructions as claimed in claim 11, wherein, The instruction decoding unit decodes the received instruction into a microinstruction, wherein the microinstruction contains an analog identifier; the system executing the new instruction initiates a system management interrupt based on the analog identifier of the microinstruction, and enters the system management mode based on the system management interrupt.

20. The system for executing new instructions as described in claim 19 further includes an instruction submission unit, wherein when the received instruction is a new instruction, the instruction submission unit initiates a system management interrupt based on the simulation identifier of the microinstruction when submitting the microinstruction.

Images