Coprocessor chip, electronic device and startup method

Abstract

The embodiment of the present application discloses a co-processing chip, an electronic device and a startup method, wherein the co-processing chip of the embodiment of the present application includes a peripheral interface, a security module and a central processing unit; the peripheral interface is used to connect to an application processing chip, and can speed up in response to a speed-up operation of the application processing chip; wherein, during the speed-up period of the peripheral interface, the security module decrypts a boot loader received from the application processing chip through the peripheral interface, and the central processing unit runs the decrypted boot loader, which makes full use of the time of the interface speed-up and greatly improves the startup speed of the co-processing chip.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a co-processing chip, an electronic device and a startup method. Background Art

[0002] At present, in order to achieve product differentiation, mobile phone manufacturers of electronic devices such as mobile phones and tablet computers generally choose to add some co-processing chips in addition to application processing chips, such as multimedia processing chips for image processing. The startup process of the co-processing chip generally requires loading multiple firmwares. Since the ROM (Read-Only Memory) storage space of the co-processing chip is limited, it can only store bootcodes. The firmware of the bootloader and the operating system (Operation System, referred to as OS) is stored in the application processing chip. When the co-processing chip is started, the application processing chip loads the firmware of the bootloader and the operating system into the co-processing chip through the peripheral interface for operation. The current startup scheme has the problem of low startup efficiency. Summary of the invention

[0003] The embodiments of the present application provide a co-processing chip, an electronic device, and a startup method, which can improve the startup speed of the co-processing chip.

[0004] In a first aspect, an embodiment of the present application provides a co-processing chip, comprising a peripheral interface, a security module and a central processing unit; the peripheral interface is used to connect to an application processing chip, and can speed up in response to a speed-up operation of the application processing chip;

[0005] During the acceleration of the peripheral interface, the security module decrypts the boot loader program received from the application processing chip through the peripheral interface, and the central processing unit runs the decrypted boot loader program.

[0006] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device includes the co-processing chip provided in the embodiment of the present application, and the electronic device also includes:

[0007] The application processing chip is used to initiate a speed-up operation on the peripheral interface after the boot loader is transmitted to the co-processing chip through the peripheral interface.

[0008] In a third aspect, an embodiment of the present application further provides a method for starting a co-processing chip, which is applied to a co-processing chip, wherein the co-processing chip is connected to an application processing chip through a peripheral interface, and the method includes:

[0009] During the period when the peripheral interface speeds up in response to the speed-up operation of the application processing chip, the co-processing chip decrypts and runs the boot loader received from the application processing chip through the peripheral interface.

[0010] The technical solution provided by the embodiment of the present application is that during the speed-up period of the peripheral interface of the co-processing chip, the security module decrypts the boot loader received from the application processing chip through the peripheral interface, and the central processing unit runs the decrypted boot loader, which makes full use of the time of interface speed-up and greatly improves the startup speed of the co-processing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A first structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0013] Figure 2 A first schematic diagram of the startup process of the co-processing chip provided in an embodiment of the present application.

[0014] Figure 3 A second schematic diagram of the startup process of the co-processing chip provided in an embodiment of the present application.

[0015] Figure 4 A second structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0017] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0018] At present, the startup method of the co-processing chip is generally to speed up the peripheral interface first, then transfer the firmware of the security module to the co-processing chip and wait for the security module to be initialized, and then transfer the bootloader and OS. After the bootloader and OS are transferred, they are decrypted and run using the security module. The defect of this scheme is that the speed-up processing takes too long, which may take tens of milliseconds. During this period of speed-up processing, the co-processing chip can only be in a waiting state, resulting in the overall startup time of the co-processing chip being too long, affecting the subsequent processing effect of the co-processing chip. For example, the co-processing chip is a multimedia processing chip, and its main function is to enhance the shooting effect. The multimedia processing chip is not always in the on state, but is started only when some image processing is required. Therefore, if the startup time of the co-processing chip is too long, the image cannot be processed in time, resulting in a delay in the output of the image, or even a short black screen, which greatly affects the user experience.

[0019] In order to solve the above problems, the present application provides a co-processing chip, see Figure 1 , Figure 1 The schematic diagram of the structure of the co-processing chip provided by the present application is that the co-processing chip 100 includes a peripheral interface 101, a central processing unit 102 and a security module 103. The peripheral interface 101 is used to connect to the application processing chip 200, and can speed up in response to the speed-up operation of the application processing chip 200; wherein, during the speed-up of the peripheral interface 101, the security module 103 decrypts the boot loader received from the application processing chip 200 through the peripheral interface 101, and the central processing unit 102 runs the decrypted boot loader.

[0020] In the embodiment of the present application, the application processing chip 200 is the main control SOC (System on Chip) of the electronic device. The co-processing chip 100 can be integrated with a central processing unit 102 and a security module 103, wherein the central processing unit 102 can perform data processing, and the security module 103 can verify and decrypt the firmware and boot loader sent by the application processing chip 200.

[0021] The central processing unit 102 is the control center of the co-processing chip 100. It uses various interfaces and lines to connect the various parts of the entire co-processing chip 100. By running or calling computer programs stored in the memory and calling data stored in the memory, it executes various functions of the co-processing chip 100 and processes data, thereby monitoring the electronic device as a whole.

[0022] The coprocessor chip 100 also includes a memory (not shown in the figure), which can be used to store computer programs and data. The computer program stored in the memory contains instructions that can be executed in the central processing unit 102. The computer program can be composed of various functional modules. The central processing unit 102 executes various functional applications and data processing by calling the computer program stored in the memory.

[0023] In addition, the co-processing chip 100 can also set other IP cores (Intellectual Property core, also known as intellectual property core or intellectual property module) according to functional needs. In the chip field, some commonly used but relatively complex functional modules in digital circuits are designed as modules with modifiable parameters, such as NPU (Neural-network Processing Unit), ISP (Image Signal Processor), DDR (Double Data Rate Synchronous Dynamic Random Access Memory) and other IP cores. The peripheral interface 101 and the central processing unit 102 inside the co-processing chip 100 are both connected to the system bus 104.

[0024] The application processing chip 200 is connected to the peripheral interface 101 of the co-processing chip 100, and the firmware that needs to be loaded during the startup of the co-processing chip 100 is transferred to the memory of the co-processing chip 100 through the peripheral interface 101. Among them, the peripheral interface 101 of the co-processing chip 100 can be an SDIO (Secure Digital Input and Output) interface, and the application processing chip 200 is connected to the SDIO interface through the SDIO bus. Among them, the SDIO interface adopts a master-slave structure, the application processing chip 200 is the host end (HOST), and the co-processing chip 100 is the device end (DEVICE). The device end can only passively respond to the operation of the host end, and the communication between the device end and the host end is started by the host end issuing a command. The device end parses the command of the host end to communicate with the host end.

[0025] In addition, the memory of the co-processing chip 100 may be DDR or SRAM (Static Random-Access Memory), and the first firmware, the boot loader, and the second firmware sent by the application processing chip 100 may be stored in the DDR or SRAM.

[0026] After the co-processing chip 100 is powered on, the application processing chip 200 sends the firmware of the security module 103 to the co-processing chip at the default transmission speed. Here, in order to distinguish several different firmwares, the firmware of the security module 103 is recorded as the first firmware, the firmware of the operating system is recorded as the second firmware, and the firmware of other IP cores is recorded as the third firmware.

[0027] The security module (Security IP core) 103 is used to verify the signature and decrypt the firmware sent by the application processing chip 200. In order to ensure the security and correctness of the firmware transmission, the application processing chip 200 will first send the first firmware of the Security IP core to the co-processing chip 100, and then send other firmware. Then, the co-processing chip 100 can run after verifying the signature and decrypting other firmware using the Security IP core. In an embedded operating system, the bootloader runs before the operating system kernel runs, and plays a role in guiding the operation of the operating system. It can initialize hardware devices and establish a memory space mapping map, so as to bring the system's hardware and software environment to a suitable state. After it completes the initialization of the relevant hardware, it will install the operating system image or the solidified embedded application into the memory and then jump to the space where the operating system is located to start the operating system.

[0028] The default transmission speed of the SDIO interface is generally low, usually around 10MB / s. If the speed is increased according to the SDIO protocol, the transmission speed will be much higher than the default transmission speed, for example, it can reach around 100MB / s.

[0029] See also Figure 2 , Figure 2 A first schematic diagram of the startup process of the co-processing chip provided in an embodiment of the present application.

[0030] In some embodiments, after the co-processing chip is powered on, the peripheral interface performs initialization processing in response to the configuration operation of the application processing chip, and after the initialization is completed, the first firmware transmitted by the application processing chip is downloaded through the peripheral interface.

[0031] like Figure 2As shown, after the co-processing chip 100 is powered on, the application processing chip 200 initializes the SDIO interface. Specifically, the first configuration information is sent to the co-processing chip 100 according to the instruction format defined by the SDIO protocol. The first configuration information is used to set the data transmission speed of the peripheral interface 101 to the default transmission speed. The co-processing chip 100 receives the first configuration information sent by the application processing chip 200; and sets the data transmission speed of the peripheral interface 101 to the default transmission speed according to the first configuration information. Then, the co-processing chip 100 first runs the bootcode, where the bootcode is the code fixed inside the chip during chip production.

[0032] In some embodiments, after the security module 103 completes the initialization process, the central processor 102 downloads the boot loader transmitted by the application processing chip 200 through the peripheral interface 101 .

[0033] The co-processing chip 100 receives the first firmware of the security module 103 sent by the application processing chip 200 at the default transmission speed, and initializes the security module 103. After completing the initialization, the co-processing chip 100 receives the bootloader sent by the application processing chip 200 at the default transmission speed. After the boot loader program is transmitted, the application processing chip 200 starts to speed up the peripheral interface 101. The speed-up process generally takes about 50 milliseconds to complete. During this period of time, the co-processing chip 100 can use the security module 103 to verify the signature and decrypt the boot loader program, and run the boot loader program after completing the signature verification and decryption.

[0034] Among them, the application processing chip 200 performs speed-up processing according to the SDIO protocol. The application processing chip 200 determines the transmission speed supported by the co-processing chip 100 through a handshake operation and notifies the application processing chip 200 of the supported transmission speed, and then determines a higher transmission speed supported by both parties, and sets the transmission speed of the SDIO interface to this speed, which is recorded as the second transmission speed.

[0035] After the speed-up process is completed, the transmission speed of the peripheral interface 101 is increased to a faster transmission speed, and the application processing chip 200 can quickly transmit the second firmware of the operating system to the co-processing chip 100, and the second firmware can be run after being verified and decrypted by the security module 103.

[0036] like Figure 2 As shown, decrypting the boot loader and running the boot loader are basically processed in parallel with speeding up the peripheral interface 101. The time occupied by the two parallel processes is T6+T7 and T5 respectively. This parallel processing method saves startup time and improves the startup speed of the multimedia processing chip compared to the conventional startup method.

[0037] See also Figure 3 , Figure 3 This is a second schematic diagram of the startup process of the co-processing chip 100 provided in an embodiment of the present application.

[0038] In some embodiments, after the coprocessing chip 100 is powered on, the peripheral interface 101 performs initialization processing in response to the configuration operation of the application processing chip 200 , and after the initialization is completed, the first firmware transmitted by the application processing chip 200 is downloaded through the peripheral interface 101 .

[0039] After the co-processing chip 100 is powered on, the application processing chip 200 initializes the SDIO interface. At the same time, after the co-processing chip 100 is powered on, the bootcode is first run, wherein the bootcode is a code fixed inside the chip during chip production. The bootcode is used to boot the chip, and its running process can be started synchronously with the initialization process of the SDIO interface.

[0040] In some embodiments, the security module 103 downloads the first firmware transmitted by the application processing chip 200 through the peripheral interface 101; when the security module 103 receives the first interrupt signal sent by the application processing chip 200, the security module 103 determines that the download of the first firmware is completed and performs initialization processing; while the security module 103 is performing initialization processing, the central processing unit 102 downloads the boot loader transmitted by the application processing chip 200 through the peripheral interface 101.

[0041] After the SDIO interface is initialized, the coprocessor chip 100 receives the first firmware of the security module 103 sent by the application processing chip 200 at the default transmission speed, and during the initialization process, the application processing chip 200 can send the boot loader to the coprocessor chip 100 through the SDIO interface. In other words, the initialization of the security module 103 by the coprocessor chip 100 and the sending of the boot loader by the application processing chip 200 can be performed simultaneously. Among them, the bootloader occupies a small space, and even if it is transmitted at a smaller default transmission speed, it can be transmitted quickly. This process generally takes a few milliseconds. The application processing chip 200 notifies the coprocessor chip 100 whether a firmware has been transmitted through an interrupt signal. For example, when the coprocessor chip 100 receives the first interrupt signal sent by the application processing chip 200, it is determined that the first firmware transmission is completed. After completing the transmission of the boot loader, the peripheral interface 101 speeds up in response to the speed-up operation of the application processing chip 200.

[0042] In some embodiments, during the acceleration of the peripheral interface 101 , the security module 103 performs an initialization process, and after the initialization process is completed, decrypts the boot loader.

[0043] After the boot loader program is transmitted, the application processing chip 200 starts to speed up the peripheral interface 101. The speed-up process generally takes about 50 milliseconds to complete. During this period, if the first firmware of the security module 103 has been transmitted, the security module 103 can be initialized. The time taken by the initialization process of the security module 103 is generally longer than the time taken by the boot loader program transmission. When the security module 103 is initialized, the boot loader program is also transmitted. The co-processing chip 100 can use the security module 103 to verify the signature and decrypt the boot loader program, and run the boot loader program after the signature verification and decryption are completed. Among them, when the co-processing chip 100 receives the second interrupt signal sent by the application processing chip 200, it is determined that the boot loader program transmission is completed.

[0044] The application processing chip 200 performs speed-up processing according to the SDIO protocol. The application processing chip 200 determines the transmission speed supported by the co-processing chip 100 through a handshake operation and notifies the application processing chip 200 of the supported transmission speed, then determines a higher transmission speed supported by both parties and sets the transmission speed of the SDIO interface to this speed.

[0045] After the peripheral interface 101 completes the speed increase, the central processor 102 downloads the second firmware of the operating system transmitted by the application processing chip 200 through the peripheral interface 101, and runs the operating system after the second firmware is downloaded. After the speed increase process is completed, the transmission speed of the peripheral interface 101 is increased to a faster transmission speed, and the application processing chip 200 can quickly transmit the second firmware of the operating system to the co-processing chip 100, and the second firmware can be run after the security module 103 verifies the signature and decrypts it.

[0046] For example, see Figure 3 , Figure 3A second schematic diagram of the startup process of the coprocessor chip 100 provided in the embodiment of the present application. Among them, the SDIO interface initialization, the reception of the first firmware, the initialization of the security module 103, the decryption of the boot loader and the operation of the boot loader are basically processed in parallel with the operation of the bootcode, the reception of the boot loader and the speed-up of the peripheral interface 101. The time occupied by the two parallel processes is T0+T2+T3+T6+T7 and T1+T4+T5 respectively. After testing on multiple electronic devices, T0 is generally about 24 microseconds, which is very short and negligible compared to other processes. T2 is generally about 10 milliseconds, T3 is generally about 24 milliseconds, T6 is generally about 1 millisecond, and T7 is generally about 18 milliseconds; T1 is generally about 5 milliseconds, T4 is generally about 6 milliseconds, and T5 is generally about 50 milliseconds. It can be seen from this that T0+T2+T3+T6+T7 and T1+T4+T5 are basically equal. Compared with the conventional startup method, this solution saves half of the startup time and makes full use of the time when the peripheral interface 101 is accelerated, which greatly improves the startup speed of the co-processing chip 100, so that image processing requirements can be responded to in time, avoiding image delay or black screen phenomenon.

[0047] As can be seen from the above, the co-processing chip 100 provided in the embodiment of the present application includes a peripheral interface 101, a security module 103 and a central processing unit 102; the peripheral interface 101 is used to connect to the application processing chip 200, and can speed up in response to the speed-up operation of the application processing chip 200; during the speed-up period of the peripheral interface 101 of the co-processing chip 100, the security module 103 decrypts the boot loader received from the application processing chip 200 through the peripheral interface 101, and the central processing unit 102 runs the decrypted boot loader, which makes full use of the interface speed-up time and greatly improves the startup speed of the co-processing chip 100.

[0048] Optionally, in some embodiments, the central processor 102 is further configured to receive a third firmware of a preset IP core sent by the application processing chip 200 .

[0049] In this embodiment, the firmware of some IP cores of the coprocessor chip 100 can also be stored in the application processing chip 200. After the operating system is loaded, the application processing chip 200 can also transmit the third firmware of these IP cores to the coprocessor chip 100 at a faster transmission speed and store them in its corresponding memory. For example, in some embodiments, the coprocessor chip 100 can be provided with DDR and SRAM at the same time, wherein SRAM is used to store some firmware that occupies less space, and DDR is used to store some firmware that occupies more space. For example, the received first firmware and the boot loader are stored in SRAM, and the received second firmware and third firmware are stored in DDR.

[0050] The present application also provides an electronic device, which includes the coprocessing chip proposed in the embodiment of the present application, and an application processing chip connected to the coprocessing chip, wherein the application processing chip is used to initiate a speed-up operation on the peripheral interface after the boot loader is transmitted to the coprocessing chip through the peripheral interface. The operations performed by the application processing chip have been described in the above embodiment and will not be repeated here.

[0051] An embodiment of the present application further provides a method for starting a co-processing chip. The method can be applied to an electronic device, which may be a co-processing chip or an electronic device integrating the co-processing chip.

[0052] The execution subject of the startup method of the co-processing chip can be the startup device of the co-processing chip provided in the embodiment of the present application, or an electronic device integrated with the startup device of the co-processing chip, wherein the startup device of the co-processing chip can be implemented in hardware or software. Among them, the electronic device can be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic devices, a smaller device (such as a wristwatch device, a hanging device, a headset or a receiver device, a device embedded in glasses or other devices worn on the user's head, or other wearable or micro devices), a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which an electronic device with a display is installed in an information kiosk or a car), a device that implements the functions of two or more of these devices, or other electronic devices.

[0053] The startup method of the co-processing chip provided in the embodiment of the present application includes:

[0054] During the period when the peripheral interface speeds up in response to the speed-up operation of the application processing chip, the co-processing chip decrypts and runs the boot loader received from the application processing chip through the peripheral interface.

[0055] In some embodiments, the method further comprises:

[0056] After the transmission of the boot loader is completed, the speed is increased in response to the speed-up operation of the application processing chip.

[0057] In some embodiments, the method further comprises:

[0058] During the acceleration of the peripheral interface, the security module is initialized, and after the initialization is completed, the boot loader is decrypted.

[0059] In some embodiments, the method further comprises:

[0060] After completing the initialization of the security module, the boot loader transmitted by the application processing chip is downloaded through the peripheral interface.

[0061] In some embodiments, the method further comprises:

[0062] Downloading the first firmware of the security module transmitted by the application processing chip through the peripheral interface;

[0063] Upon receiving a first interrupt signal sent by the application processing chip, determining that the first firmware download is complete, and initializing processing of the security module; and

[0064] While initializing the security module, the boot loader transmitted by the application processing chip is downloaded through the peripheral interface.

[0065] In some embodiments, the method further comprises:

[0066] After the peripheral interface completes the speed increase, downloading the second firmware of the operating system transmitted by the application processing chip through the peripheral interface; and

[0067] After the second firmware is downloaded, the operating system is run.

[0068] In some embodiments, see Figure 4 , Figure 4 A second structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 300 further includes a radio frequency circuit 303, a display screen 304, a control circuit 305, an input unit 306, an audio circuit 307, a sensor 308, and a power supply 309. The application processing chip 200 and the coprocessing chip 100 are electrically connected to the radio frequency circuit 303, the display screen 303, the control circuit 303, the input unit 306, the audio circuit 307, the sensor 308, and the power supply 309, respectively.

[0069] The application processing chip 200 is a main control SOC of the electronic device.

[0070] The radio frequency circuit 303 is used to send and receive radio frequency signals to communicate with network devices or other electronic devices through wireless communication.

[0071] The display screen 304 may be used to display information input by a user or information provided to a user and various graphical user interfaces of the electronic device. These graphical user interfaces may be composed of images, texts, icons, videos and any combination thereof.

[0072] The control circuit 305 is electrically connected to the display screen 304 and is used to control the display screen 304 to display information.

[0073] The input unit 306 can be used to receive input numbers, character information or user feature information (such as fingerprints), and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control. The input unit 306 can include a fingerprint recognition module.

[0074] The audio circuit 307 can provide an audio interface between the user and the electronic device through a speaker and a microphone. The audio circuit 307 includes a microphone. The microphone is electrically connected to the central processor 102. The microphone is used to receive voice information input by the user.

[0075] The sensor 308 is used to collect external environment information. The sensor 308 may include one or more sensors such as an environment brightness sensor, an acceleration sensor, and a gyroscope.

[0076] The power supply 309 is used to supply power to various components of the electronic device 300. In some embodiments, the power supply 309 can be logically connected to the central processor 102 through a power management system, so that the power management system can manage charging, discharging, power consumption and other functions.

[0077] Although not shown in the figure, the electronic device 300 may also include a camera, a Bluetooth module, etc., which will not be described in detail here.

[0078] In this embodiment, the coprocessor chip 100 further includes a memory 105. The central processor 102 in the electronic device 300 loads instructions corresponding to the processes of one or more computer programs into the memory 104 according to the following steps, and the central processor 102 runs the computer programs stored in the memory 104, thereby realizing various functions:

[0079] During the period when the peripheral interface speeds up in response to the speed-up operation of the application processing chip, the co-processing chip decrypts and runs the boot loader received from the application processing chip through the peripheral interface.

[0080] From the above, it can be seen that an embodiment of the present application provides an electronic device, in which, during the period when the peripheral interface of the co-processing chip is accelerated, the security module decrypts the boot loader received from the application processing chip through the peripheral interface, and the central processing unit runs the decrypted boot loader, thereby making full use of the time of interface acceleration and greatly improving the startup speed of the co-processing chip.

[0081] An embodiment of the present application further provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium. When the computer program is executed on a computer, the computer executes the method for starting the coprocessing chip described in any of the above embodiments.

[0082] It should be noted that, those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer-readable storage medium can include but is not limited to: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0083] In addition, the terms "first", "second", and "third" in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but some embodiments also include steps or modules that are not listed, or some embodiments also include other steps or modules inherent to these processes, methods, products, or devices.

[0084] The above is a detailed introduction to the co-processing chip, electronic device and startup method provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application; at the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A co-processing chip, characterized in that: It includes a peripheral interface, a security module and a central processing unit; the peripheral interface is used to connect to an application processing chip, and can speed up in response to a speed-up operation of the application processing chip; During the speed-up of the peripheral interface, the security module decrypts the boot loader received from the application processing chip through the peripheral interface, and the central processing unit runs the decrypted boot loader. Decrypting the boot loader and running the boot loader are processed in parallel with the speed-up of the peripheral interface.

2. The co-processing chip according to claim 1, characterized in that: After completing the transmission of the boot loader, the peripheral interface speeds up in response to the speed-up operation of the application processing chip.

3. The co-processing chip according to claim 1, characterized in that: During the acceleration of the peripheral interface, the security module performs an initialization process, and after the initialization process is completed, decrypts the boot loader.

4. The co-processing chip according to claim 1 or 2, characterized in that: After the security module completes the initialization process, the central processing unit downloads the boot loader transmitted by the application processing chip through the peripheral interface.

5. The co-processing chip according to any one of claims 1 to 3, characterized in that: The security module downloads the first firmware of the security module transmitted by the application processing chip through the peripheral interface; when the security module receives the first interrupt signal sent by the application processing chip, it determines that the download of the first firmware is completed and performs initialization processing; While the security module is performing initialization processing, the central processing unit downloads the boot loader transmitted by the application processing chip through the peripheral interface.

6. The co-processing chip according to any one of claims 1 to 3, characterized in that: After the peripheral interface is accelerated, the central processing unit downloads the second firmware of the operating system transmitted by the application processing chip through the peripheral interface, and runs the operating system after the download of the second firmware is completed.

7. An electronic device, characterized in that: The electronic device comprises the co-processing chip according to any one of claims 1 to 6, and the electronic device further comprises: The application processing chip is used to initiate a speed-up operation on the peripheral interface after the boot loader is transmitted to the co-processing chip through the peripheral interface.

8. A method for starting a co-processing chip, characterized in that: Applied to a co-processing chip, the co-processing chip is connected to an application processing chip via a peripheral interface, and the method includes: During the period when the peripheral interface is accelerated in response to the acceleration operation of the application processing chip, the co-processing chip decrypts and runs the boot loader received from the application processing chip through the peripheral interface, and the decryption of the boot loader and the running of the boot loader are processed in parallel with the acceleration processing of the peripheral interface.

9. The method for starting a co-processing chip according to claim 8, characterized in that: Also includes: After the transmission of the boot loader is completed, the speed is increased in response to the speed-up operation of the application processing chip.

10. The method for starting a co-processing chip according to claim 8, characterized in that: Also includes: During the acceleration of the peripheral interface, the security module is initialized, and after the initialization is completed, the boot loader is decrypted.

11. The method for starting a co-processing chip according to claim 8 or 9, characterized in that: Also includes: After completing the initialization of the security module, the boot loader transmitted by the application processing chip is downloaded through the peripheral interface.

12. The method for starting a co-processing chip according to any one of claims 8 to 10, characterized in that: Also includes: Downloading the first firmware of the security module transmitted by the application processing chip through the peripheral interface; Upon receiving a first interrupt signal sent by the application processing chip, determining that the first firmware download is complete, and initializing processing of the security module; as well as While initializing the security module, the boot loader transmitted by the application processing chip is downloaded through the peripheral interface.

13. The method for starting a co-processing chip according to any one of claims 8 to 10, characterized in that: Also includes: After the peripheral interface completes the speed-up, downloading the second firmware of the operating system transmitted by the application processing chip through the peripheral interface; as well as After the second firmware is downloaded, the operating system is run.

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