Event triggering main control terminal, control chip and control method

Abstract

An event-triggered host, a control chip, and a control method are disclosed, wherein the event-triggered host includes an event receiving interface, a storage device, a state machine, and a host control interface. The event receiving interface is configured to receive an event request. The storage device includes a command queue for storing at least one setting command. When the event request is triggered, the state machine executes the setting command to access a first peripheral device or a second peripheral device. The host control interface is coupled between the state machine and the peripheral device. The state machine accesses the first or second peripheral device via the host control interface.

Description

Technical Field

[0001] The present invention relates to an event-triggered host terminal, and more particularly to an event-triggered host terminal coupled between a processor and a peripheral device. Background Art

[0002] With technological advancements, electronic devices are becoming increasingly diverse and versatile. These devices contain numerous control chips. Each control chip typically contains a processor. This processor, the heart of the chip, is responsible for controlling all internal components.

[0003] For example, a processor may trigger a first specific circuit to instruct the first specific circuit to perform a preset operation. While the first specific circuit is performing the preset operation, the processor may read and execute a code. After completing the preset operation, the first specific circuit issues an event notification. Therefore, the processor pauses code execution and triggers a second specific circuit based on the event notification issued by the first specific circuit. While the second specific circuit is performing the corresponding preset operation, the processor resumes code execution. After the second specific circuit completes the preset operation, the second specific circuit issues an event notification. Therefore, the processor pauses code execution again and acts based on the interrupt signal issued by the second specific circuit. Since the processor's operation is interrupted multiple times, the processor's performance is reduced. Summary of the Invention

[0004] One embodiment of the present invention provides an event-triggered host terminal, comprising an event receiving interface, a storage device, a state machine, and a host control interface. The event receiving interface is configured to receive an event request. The storage device has a command queue for storing a configuration command. When the event request is triggered, the state machine executes the configuration command to access a first peripheral device or a second peripheral device. The host control interface couples the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first or second peripheral device via the host control interface.

[0005] The present invention further provides a control chip, which includes a first peripheral device, a second peripheral device, a peripheral system bus, and an event-triggered master terminal. The peripheral system bus couples the first and second peripheral devices. The event-triggered master terminal communicates with the first and second peripheral devices via the peripheral system bus, and includes an event receiving interface, a storage device, a state machine, and a master interface. The event receiving interface is used to receive an event request. The storage device has an instruction queue for storing a setting instruction. When the event request is triggered, the state machine executes the setting instruction to access the first or second peripheral device. The master interface is coupled between the state machine and the peripheral system bus. The state machine accesses the first or second peripheral device via the master interface and the peripheral system bus.

[0006] Another embodiment of the present invention provides a control method for controlling a first peripheral device and a second peripheral device. The control method includes storing a configuration instruction and determining whether an event request is triggered. When the event request is triggered, executing the configuration instruction to access the first or second peripheral device. The configuration instruction is provided by a processor. The configuration instruction is executed by an event-triggered host. The event-triggered host responds to the triggered event request. The processor does not respond to the triggered event request.

[0007] The control method of the present invention can be implemented via an event-triggered control terminal or control chip of the present invention, which is hardware or firmware capable of executing specific functions. Alternatively, the method can be implemented as code stored on a recording medium and combined with specific hardware. When the code is loaded and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes the event-triggered control terminal or control chip for implementing the present invention.

[0008] In this embodiment of the present invention, an event-triggered master monitors whether an event request has been triggered and responds when it is. Therefore, the processor does not need to respond to event requests. The processor can now perform other operations without having to respond to each event request. This significantly improves processor efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the control chip of the present invention.

[0010] Figure 2 This is a possible schematic diagram of an event-triggered master terminal of the present invention.

[0011] Figure 3 FIG. 1 is a possible control diagram of the control chip of the present invention.

[0012] Figure 4 FIG. 4 is a possible flow chart of the control method of the present invention.

[0013] Figure Numbers

[0014] 100, 300: control chip

[0015] 102, 302: Processor

[0016] 104, 304: Main system bus

[0017] 106, 200, 306: Event triggering the master control end

[0018] 108: Peripheral Circuits

[0019] 110, 308: Peripheral system bus

[0020] 112: Transmission interface

[0021] E1~EN:Event request

[0022] PD_1~PD_3: Peripheral devices

[0023] 202: Storage devices

[0024] 204: State Machine

[0025] 206: Event receiving interface

[0026] 208: Main control interface

[0027] 210: slave interface

[0028] QU_1~QU_N: instruction queue

[0029] CM1_1~CM1_X, CM2_1~CM2_Y, CMN_1~CM2_Z: Setting command

[0030] CME: Termination Instructions

[0031] 310: Timer

[0032] 312: Analog-to-digital converter

[0033] 314: Direct Memory Access Controller

[0034] 316: Sequence Peripheral Interface

[0035] AIN: analog signal

[0036] DOUT: output signal DETAILED DESCRIPTION

[0037] To make the objectives, features, and advantages of the present invention more readily apparent, the following examples are presented and described in detail with reference to the accompanying drawings. This specification provides various examples to illustrate the technical features of various embodiments of the present invention. The configurations of the various components in the examples are for illustrative purposes only and are not intended to limit the present invention. Furthermore, any repetition of reference numerals in the figures of the examples is for simplification and does not imply a correlation between the different examples.

[0038] Figure 1FIG1 is a schematic diagram of a control chip according to the present invention. As shown, the control chip 100 includes a processor 102, a main system bus 104, an event trigger master 106, and a peripheral circuit 108. The processor 102 is coupled to the main system bus 104. In one embodiment, the processor 102 is a central processing unit (CPU).

[0039] The event trigger master 106 is coupled to the peripheral circuit 108 and receives event requests E1-EN. When an event request is triggered, the event trigger master 106 configures the peripheral circuit 108 to instruct it to perform a specific action. After completing the specific action, the peripheral circuit 108 may trigger one of the event requests E1-EN. In this case, the event trigger master 106 performs a specific action based on the triggered event request, such as interrupting the processor 102, or reconfigures the peripheral circuit 108 to instruct it to perform another specific action. In this embodiment, the event trigger master 106 acts as a master device to control the peripheral circuit 108. In this example, the peripheral circuit 108 acts as a slave device.

[0040] In some embodiments, the event-triggered master 106 is directly coupled to the main system bus 104. In this example, the event-triggered master 106 sends an interrupt signal to the processor 102 via the main system bus 104. Alternatively, the processor 102 may send data to the event-triggered master 106 or receive data from the event-triggered master 106. In this case, the processor 102 acts as a master device, and the event-triggered master 106 acts as a slave device. In this embodiment, the main system bus 104 provides a connection that allows the processor 102 to access the event-triggered master 106.

[0041] In other embodiments, the control chip 100 further includes a transmission interface 112. The transmission interface 112 is coupled between the main system bus 104 and the peripheral circuit 108. In this example, the processor 102 sends data to the peripheral circuit 108 or receives data from the peripheral circuit 108 through the transmission interface 112. In addition, the processor 102 can also send data to the event trigger host 106 or receive data from the event trigger host 106 through the transmission interface 112 and the peripheral circuit 108.

[0042] In one embodiment, peripheral circuit 108 generates event requests E1-EN and includes a peripheral system bus 110 and peripheral devices PD_1-PD_3. Peripheral system bus 110 is coupled between event trigger host 106 and peripheral devices PD_1-PD_3. In this embodiment, peripheral system bus 110 provides a connection that allows event trigger host 106 to access peripheral devices PD_1-PD_3, such as setting operations.

[0043] For example, the event trigger host 106 outputs control commands to the peripheral devices PD_1 - PD_3 or receives response data from the peripheral devices PD_1 - PD_3 via the peripheral system bus 110. In other embodiments, the processor 102 communicates with the event trigger host 106 via the peripheral system bus 110, the transmission interface 112, and the main system bus 104.

[0044] The peripheral devices PD_1 to PD_3 are coupled to the peripheral system bus 110 to receive data from the peripheral system bus 110 or output data to the peripheral system bus 110. Figure 1 Only peripheral devices PD_1 to PD_3 are shown, but this is not intended to limit the present invention. In other embodiments, the peripheral circuit 108 has more or fewer peripheral devices.

[0045] In this embodiment, event requests E1-EN are generated by peripheral devices PD_1-PD_3. The present invention does not limit the number of event requests generated by each peripheral device. In one embodiment, each peripheral device generates a single event request. In this example, the number of event requests E1-EN is the same as the number of peripheral devices in peripheral circuit 108.

[0046] In other embodiments, at least one of the peripheral devices PD_1 to PD_3 generates multiple event requests. In this example, when the same peripheral device completes different specific actions, the peripheral device triggers different event requests. Taking the peripheral device PD_1 as an example, when the peripheral device PD_1 completes a first action (such as a timing operation), the peripheral device PD_1 triggers an event request E1. When the peripheral device PD_1 completes a second action (such as a counting operation), the peripheral device PD_1 triggers an event request E2. In some embodiments, the first and second actions may both be timing operations, but the execution time of the first action is different from the execution time of the second action. In this example, the first action is considered different from the second action. In other embodiments, the number of event requests generated by at least one of the peripheral devices PD_1 to PD_3 is different from the number of event requests generated by another peripheral device PD_1 to PD_3.

[0047] The present invention does not limit the types of peripheral devices PD_1 - PD_3 . At least one of peripheral devices PD_1 - PD_3 may be of the same type as another of peripheral devices PD_1 - PD_3 . In one embodiment, any of peripheral devices PD_1 - PD_3 may be a serial peripheral interface (SPI), a pulse-width modulation (PWM) circuit, an analog-to-digital converter (ADC), a direct memory access (DMA) controller, a timer, etc.

[0048] In this embodiment, the event-triggering host 106 detects whether peripheral devices PD_1-PD_3 have completed a specific action based on event requests E1-EN. Upon completion of the specific action, the host 106 triggers any of the peripheral devices PD_1-PD_3 based on its own stored configuration data (not shown). Therefore, the processor 102 is not interrupted multiple times. The processor 102 only executes the corresponding action after the event-triggering host 106 issues an interrupt signal. This frees the processor 102 to perform other operations, thereby increasing the efficiency of the processor 102.

[0049] In other embodiments, the processor 102 is located in a first power domain (not shown), while the event trigger host 106 and the peripheral circuits 108 are located in a second power domain (not shown). The first power domain and the second power domain are independent of each other. Therefore, when the power in the first power domain decreases, even if the processor 102 enters power saving mode and stops operating, as long as the power in the second power domain is sufficient, the event trigger host 106 and the peripheral circuits 108 can continue to operate normally.

[0050] In other embodiments, the processor 102 is located in a first clock domain (not shown), while the event trigger master 106 and peripheral devices PD_1-PD_3 are located in a second clock domain (not shown). The first clock domain and the second clock domain are independent of each other. Therefore, when the frequency of the clock signal in the first clock domain decreases, even if the processor 102 enters power saving mode and stops operating, as long as the frequency of the clock signal in the second clock domain remains unchanged, the event trigger master 106 and peripheral circuits 108 can continue to operate normally. In this example, the processor 102, the event trigger master 106, and the peripheral circuits 108 may be located in the same power domain.

[0051] Figure 2The following is a possible schematic diagram of an event-triggered master terminal of the present invention. As shown, the event-triggered master terminal 200 includes a storage device 202, a state machine 204, an event receiving interface 206, and a master control interface 208. The storage device 202 has instruction queues (queues) QU_1 through QU_N. The present invention does not limit the number of queues. In one possible embodiment, the number of queues is the same as the number of event requests. In addition, the instruction queues QU_1 through QU_N may be stored in different blocks of the same memory. In other embodiments, the storage device 202 has different memories, each storing a corresponding queue.

[0052] In this embodiment, each queue stores at least one configuration command. As shown, command queue QU_1 stores configuration commands CM1_1-CM1_X. Command queue QU_2 stores configuration commands CM2_1-CM2_Y. Command queue QU_N stores configuration commands CMN_1-CM2_Z. The present invention does not limit the number of configuration commands stored in command queues QU_1-QU_N. The number of configuration commands stored in one of command queues QU_1-QU_N may be the same as or different from the number of configuration commands stored in another of command queues QU_1-QU_N.

[0053] In some embodiments, each of command queues QU_1 through QU_N further includes an end of command (CME). The end of command (CME) is located after the last set command in command queues QU_1 through QU_N. Taking command queue QU_1 as an example, assume that set commands CM1_1 through CM1_X are arranged sequentially, with set command CM1_1 being the first set command and set command CM1_X being the last set command. In this example, the end of command (CME) is located after set command CM1_X. In one embodiment, the end of command (CME) indicates the end of the queue, and its value may be 0xFFFF_FFFF or 0x0000_0000.

[0054] The present invention does not limit the format of the configuration commands of command queues QU_1 through QU_N. Taking command queue QU_1 as an example, each configuration command CM1_1 through CM1_X may include an address and configuration data. In another embodiment, each configuration command of command queue QU_1 further includes a bit mask. In some embodiments, each configuration command of command queue QU_1 may include a device identification code.

[0055] The state machine 204 is coupled to the memory device 202, the event receiving interface 206, and the host control interface 208. The state machine 204 receives event requests E1-~EN through the event receiving interface 206. When an event request is triggered, the state machine 204 reads a corresponding queue (such as the instruction queue QU_1) of the memory device 202 and executes the queue's setting instructions (such as CM1_1~CM_X) to provide at least one setting value to a corresponding peripheral device. In one embodiment, when the state machine 204 reads the termination instruction CME of the instruction queue QU_1, it indicates that all setting instructions in the queue have been executed. Therefore, the state machine 204 triggers the corresponding peripheral device. At this time, the corresponding peripheral device acts according to the setting value provided by the state machine 204. After the peripheral device completes the specific action, the peripheral device triggers an event request, causing the state machine 204 to read a corresponding queue and execute the setting instructions in the queue according to the triggered event request.

[0056] Event receiving interface 206 is coupled between state machine 204 and a peripheral circuit (e.g., 108) to receive event requests E1-EN from the peripheral circuit and provide event requests E1-EN to state machine 204. In one embodiment, event receiving interface 206 has a plurality of pins (not shown) for receiving event requests E1-EN. In this example, the number of pins on event receiving interface 206 is the same as the number of event requests E1-EN.

[0057] The main control interface 208 is coupled between the state machine 204 and a peripheral circuit. Figure 1 For example, host interface 208 is coupled to peripheral system bus 110 of peripheral circuit 108. In this example, state machine 204 outputs a setting value to a corresponding peripheral device via host interface 208 and peripheral system bus 110. Therefore, host interface 208 provides a connection that allows state machine 204 to perform setting operations with multiple peripheral devices. For ease of explanation, it is assumed that state machine 204 communicates with peripheral devices PD_1 through PD_3 via peripheral system bus 110.

[0058] In one possible embodiment, the setting instructions in different queues are for different peripheral devices. For example, after the peripheral device PD_1 completes a first action, the peripheral device PD_1 triggers an event request E1. At this time, the state machine 204 reads a corresponding instruction queue, such as QU_1, based on the triggered event request E1. In this example, the state machine 204 reads and executes the setting instructions CM1_1~CM1_X to write multiple data to the peripheral device PD_2 until the termination instruction CME is read. When the state machine 204 reads the termination instruction CME, the instruction response to the event request E1 is completed. In this embodiment, the termination instruction CME represents the end of the queue.

[0059] When the peripheral device PD_2 completes a second action, the peripheral device PD_2 triggers an event request E2. Therefore, the state machine 204 reads a corresponding instruction queue, such as QU_2. In this example, the state machine 204 reads and executes the setting instructions CM2_1~CM2_Y to write multiple data to the peripheral device PD_3 until the termination instruction CME of the instruction queue QU_2 is read. The termination instruction CME of the instruction queue QU_2 may be the same as the termination instruction CME of the instruction queue QU_1. In one possible embodiment, when the peripheral device PD_3 completes the action, the peripheral device PD_3 triggers an event request EN. Therefore, the state machine 204 reads a corresponding instruction queue, such as QU_N. In this example, after executing the setting instructions CMN_1~CMN_Z, the state machine 204 may send an interrupt signal to a processor (102) through the host control interface 208.

[0060] In other embodiments, the setting instructions of different queues may be directed to the same peripheral device. In this example, the same peripheral device performs different actions according to the setting instructions of different queues. For example, when the event request E1 is triggered, the state machine 204 reads the instruction queue QU_1 and executes the setting instructions CM1_1~CM1_X to write multiple data to the peripheral device PD_1. Then, the peripheral device PD_1 performs a first action. After completing the first action, the peripheral device PD_1 may trigger the event request E2. At this time, the state machine 204 may read the instruction queue QU_2 and execute the setting instructions CM2_1~CM2_Y to write multiple data to the peripheral device PD_1. Then, the peripheral device PD_1 starts to perform a second action.

[0061] In other embodiments, different configuration commands within the same queue may target different peripheral devices. Taking command queue QU_1 as an example, when event request E1 is triggered, the state machine reads command queue QU_1. In this example, state machine 204 writes a first data message to peripheral device PD_1 based on the device identification code of configuration command CM1_1, writes a second data message to peripheral device PD_2 based on the device identification code of configuration command CM1_2, and writes a third data message to peripheral device PD_3 based on the device identification code of configuration command CM1_3.

[0062] In some embodiments, state machine 204 receives data (e.g., setting commands CM1_1-CM1_X, CM2_1-CM2_Y, CMN_1-CMN_Z, and a termination command CME) from processor 102 via host interface 208. In this example, state machine 204 writes setting commands CM1_1-CM1_X, CM2_1-CM2_Y, and CMN_1-CMN_Z into command queues QU_1-QU_N, respectively. In other embodiments, event-triggered master 200 further includes a slave interface 210. Slave interface 210 is coupled between state machine 204 and processor 102. In this example, slave interface 210 is configured to receive designated commands CM1_1-CM1_X, CM2_1-CM2_Y, CMN_1-CMN_Z, and a termination command CME from main system bus 104. The state machine 204 writes the designated commands CM1_1-CM1_X, CM2_1-CM2_Y, CMN_1-CMN_Z and the termination command CME into the memory device 202. The present invention does not limit the type of the slave interface 210. In one embodiment, the type of the slave interface 210 is the same as that of the master interface 208.

[0063] Figure 3 This is a schematic diagram of a possible control scheme for a control chip according to the present invention. As shown, the control chip 300 includes a processor 302, a main system bus 304, an event trigger host 306, a peripheral system bus 308, a timer 310, an analog-to-digital converter (ADC) 312, a direct memory access controller (DMA) 314, and a serial peripheral interface 316. The timer 310, ADC 312, DMA 314, and serial peripheral interface 316 are all peripheral devices.

[0064] In one embodiment, the processor 302, the event trigger host 306, and the direct memory access controller 314 can all access a static random access memory (SRAM), an analog-to-digital converter 312, and a serial peripheral interface 316. In this embodiment, the event trigger host 306 receives event requests E1-E4 generated by the timer 310, the analog-to-digital converter 312, the direct memory access controller 314, and the serial peripheral interface 316.

[0065] When the timer 310 reaches a certain time point, the timer 310 triggers the event signal E1. Therefore, the event trigger host 306 executes a first queue of setting commands (not shown) to configure the analog-to-digital converter 312. In this example, the analog-to-digital converter 312 samples an analog signal AIN. After completing the sampling, the analog-to-digital converter 312 triggers the event signal E2. At this point, the event trigger host 306 executes a second queue of setting commands to configure the direct memory access controller 314. After completing the setting, the direct memory access controller 314 reads the sampling results from the analog-to-digital converter 312 and writes the sampling results to the register of the serial peripheral interface 316. After completing the operation, the direct memory access controller 314 triggers the event signal E3.

[0066] At this point, the event triggers the host 306 to execute a third queue setup command to configure the serial peripheral interface 316. In this example, the serial peripheral interface 316 outputs the sampled result from the analog-to-digital converter 312 as output data, which is encoded in the output signal DOUT. After the serial peripheral interface 316 completes the output operation, it may trigger the event signal E4. In this example, the event triggers the host 306 to execute a fourth queue setup command to issue an interrupt signal to the processor 302. In other embodiments, after the serial peripheral interface 316 completes the output operation, it directly issues an interrupt signal to the processor 302.

[0067] After receiving the interrupt signal, processor 302 knows that a series of actions have been completed. Specifically, when timer 310 reaches a certain time point, analog-to-digital converter 312 samples analog signal AIN and outputs the sampled result via serial peripheral interface 316. In this embodiment, since processor 302 does not need to monitor each peripheral device to see if a specific action has been completed, processor 302 can perform other actions, thereby improving processor 302 efficiency.

[0068] Figure 4 FIG2 is a flow chart of a possible control method of the present invention. The control method of the present invention is used to control multiple peripheral devices. For ease of explanation, the following uses a first peripheral device and a second peripheral device as an example.

[0069] First, store at least one setting instruction (step S411). In the present embodiment, the setting instruction is provided by a processor. In this example, the processor may write the setting instruction to an event-triggered master terminal through a main system bus. In other embodiments, the processor may write the setting instruction to an event-triggered master terminal through a main system bus and a peripheral system bus. In some embodiments, the processor further provides at least one termination instruction to the event-triggered master terminal. The present invention does not limit the format of the setting instruction. In one possible embodiment, the setting instruction may have an address information and a setting information. In another possible embodiment, the setting instruction further has a backplane information. In some embodiments, the setting instruction may have a device identification code.

[0070] Determine whether an event request is triggered (step S412). When the event request is not triggered, return to step S412. When the event request is triggered, execute a setting instruction to configure the first or second peripheral device (step S413). In one possible embodiment, the event triggering master detects whether the event request is triggered. In this example, the event triggering master has at least one queue for storing setting instructions. When an event request is triggered, the event triggering master reads and executes the corresponding queue to configure a corresponding peripheral device.

[0071] In this embodiment, the event-triggered master monitors whether an event request has been triggered and responds when it is. Therefore, the processor does not need to respond to event requests. The processor can now perform other operations without having to respond to each event request. This significantly improves processor efficiency.

[0072] The control method of the present invention, or a specific form or part thereof, can exist in the form of code. The code can be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product that is not limited to an external form, wherein when the code is loaded and executed by a machine, such as a computer, the machine becomes a master terminal or control chip for participating in the event triggering of the present invention. The code can also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission mode, wherein when the code is received, loaded and executed by a machine, such as a computer, the machine becomes a master terminal or control chip for participating in the event triggering of the present invention. When actually operated on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.

[0073] Unless otherwise defined, all terms used herein (including technical and scientific terms) are those generally understood by those skilled in the art. Furthermore, unless otherwise expressly stated, dictionary definitions of terms should be interpreted as consistent with their meanings in articles in the relevant technical field and should not be interpreted as idealized or overly formal. While terms such as "first" and "second" may be used to describe various devices, these devices should not be limited by these terms. These terms are used solely to distinguish one device from another.

[0074] While the present invention has been described above with reference to preferred embodiments, this is not intended to limit the present invention. Any skilled artisan may make modifications and variations without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An event-triggered master control terminal, characterized in that: A first peripheral device is directly coupled via a peripheral system bus and includes: a slave interface directly connected to a master system bus; An event receiving interface, for receiving a first event request; A storage device having a first instruction queue for storing a first setting instruction; a state machine, which executes the first setting instruction to access the first peripheral device or a second peripheral device when the first event request is triggered; and a host interface directly connected between the state machine and the peripheral system bus, wherein the state machine accesses the first peripheral device or the second peripheral device through the host interface and the peripheral system bus; in: The first peripheral device and the second peripheral device are directly coupled to the peripheral system bus, The first setting instruction is provided by a processor, the processor is not directly coupled to the peripheral system bus, and the processor is directly connected to the main system bus. The main system bus and the peripheral system bus are independent of each other.

2. The event-triggered master control terminal according to claim 1, wherein: The state machine receives the first setting instruction from the processor through the main control interface, and writes the first setting instruction into the storage device.

3. The event-triggered master control terminal according to claim 1, wherein: The state machine receives the first setting instruction from the processor through the slave interface and writes the first setting instruction into the storage device.

4. The event-triggered master control terminal according to claim 1, wherein: The memory device further comprises: A second command queue is used to store a second setting command.

5. The event-triggered master control terminal according to claim 4, wherein: When the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device. When a second event request is triggered, the state machine executes the second setting instruction to access the second peripheral device.

6. The event-triggered master control terminal according to claim 4, wherein: When the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device and instruct the first peripheral device to perform a first action. When a second event request is triggered, the state machine executes the second setting instruction to access the first peripheral device and instruct the first peripheral device to perform a second action.

7. The event-triggered master control terminal according to claim 6, wherein: The first instruction queue has multiple first setting instructions and a first termination instruction. When the first event request is triggered, the state machine reads and executes the multiple first setting instructions of the first instruction queue until the first termination instruction is read. After reading the first termination instruction, the state machine stops reading the first instruction queue.

8. A control chip, characterized in that: include: a processor; a main system bus directly connected to the processor; a first peripheral device; a second peripheral device; a peripheral system bus directly coupling the first peripheral device and the second peripheral device; as well as An event-triggered master terminal is directly connected between the main system bus and the peripheral system bus, and communicates with the first peripheral device and the second peripheral device via the peripheral system bus, and includes: a slave interface directly connected to the master system bus; An event receiving interface, for receiving a first event request; A storage device having a first instruction queue for storing a first setting instruction; a state machine, which executes the first setting instruction to access the first peripheral device or the second peripheral device when the first event request is triggered; and a host interface directly connected between the state machine and the peripheral system bus, wherein the state machine accesses the first peripheral device or the second peripheral device through the host interface and the peripheral system bus; The first setting instruction is provided by the processor. The processor is not directly coupled to the peripheral system bus. The main system bus and the peripheral system bus are independent of each other.

9. The control chip according to claim 8, wherein: The first instruction queue further stores a second setting instruction. When the first event request is triggered, the state machine executes the first setting instruction to set the first peripheral device. When a second event request is triggered, the state machine executes the second setting instruction to set the second peripheral device.

10. A control method, characterized in that: For controlling a first peripheral device and a second peripheral device, the control method includes: receiving a setting instruction from a main system bus; storing a setting instruction, wherein the setting instruction is provided by a processor; Determine whether an event request is triggered; When the event request is triggered, executing the setting instruction to access the first peripheral device or the second peripheral device through a peripheral system bus; The setting instruction is executed by an event-triggered master terminal, the event-triggered master terminal responds according to the triggered event request, and the processor does not respond according to the triggered event request. The first peripheral device and the second peripheral device are directly coupled to the peripheral system bus, the processor is not directly coupled to the peripheral system bus, and the main system bus and the peripheral system bus are independent of each other.

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