Event control device and method of operation thereof

Abstract

The application discloses an event control device and an operating method thereof. The device comprises a first selection module, a second selection module, a first processing module, a channel connection module and an output module. The first selection module receives a plurality of event signals and outputs a first event signal. The second selection module receives an event signal and outputs a second event signal. The first processing module receives the first event signal and the second event signal, and performs a first logic processing on the first event signal or a first inverted event signal and the second event signal or a second inverted event signal to generate a first processing signal. The channel connection module has a plurality of output channels, receives the first processing signal, and specifies a first output channel of the output channels to output the first processing signal. The output module receives the first processing signal and generates a first output signal or a first synchronous output signal according to the first processing signal, effectively increasing the flexibility and use situation of event connection and the convenience in use.

Description

Technical Field

[0001] This invention relates to a control device, and more particularly to an event control device and its operating method. Background Technology

[0002] Generally, event connections between peripheral devices can be executed through an event controller. However, an event controller only provides a linear relationship between peripheral devices; that is, the event controller provides event trigger signals from one peripheral device to another, causing the other peripheral device to perform a corresponding operation. This makes the event controller's processing mode rather monotonous. Therefore, increasing the flexibility and convenience of event controllers is an important current issue. Summary of the Invention

[0003] This invention provides an event control device and its operating method, thereby increasing the flexibility and application scenarios of event connections between peripheral devices and enhancing ease of use.

[0004] This invention provides an event control device, including a first selection module, a second selection module, a first processing module, a channel connection module, and an output module. The first selection module receives multiple event signals and outputs a first event signal. The second selection module receives the event signals and outputs a second event signal. The first processing module is coupled to the first and second selection modules, receives the first and second event signals, and performs first logic processing on the first event signal or a first inverted event signal and the second event signal or a second inverted event signal to generate a first processed signal. The channel connection module is coupled to the first processing module and has multiple output channels. The channel connection module receives the first processed signal and outputs the first processed signal through a first output channel of a designated output channel. The output module is coupled to the channel connection module, receives the first processed signal, and generates a first output signal or a first synchronous output signal based on the first processed signal.

[0005] This invention provides an operation method for an event control device, comprising the following steps: Receiving multiple event signals and outputting a first event signal via a first selection module. Receiving event signals and outputting a second event signal via a second selection module. Performing first logic processing on the first event signal or a first inverted event signal and the second event signal or a second inverted event signal via a first processing module to generate a first processed signal. Receiving the first processed signal via a channel connection module and designating a first output channel of the multiple output channels of the channel connection module to output the first processed signal. Receiving the first processed signal via an output module and generating a first output signal or a first synchronous output signal based on the first processed signal.

[0006] The event control device and its operating method disclosed in this invention perform first logical processing on at least a first event signal or a first inverted event signal and a second event signal or a second inverted event signal through a first processing module to generate a first processed signal. A channel connection module outputs the first processed signal through a first output channel of a specified output channel, and an output module generates a first output signal or a first synchronous output signal based on the first processed signal. This effectively increases the flexibility and application scenarios of event connections, thereby enhancing ease of use. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an event control device according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram showing the correspondence between the first event signal, the second event signal, the first processing signal, and the first synchronization output signal according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of an event control device according to another embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of an event control device according to another embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram showing the correspondence between the first event signal, the second event signal, the first processing signal, the third event signal, the second processing signal, the third processing signal, and the first synchronous output signal according to an embodiment of the present invention.

[0012] Figure 6 This is a schematic diagram of an event control device according to another embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram of an event control system according to an embodiment of the present invention.

[0014] Figure 8 This is a flowchart of an operation method of an event control device according to an embodiment of the present invention.

[0015] Figure 9 for Figure 8 The detailed flowchart of step S806.

[0016] Figure 10 for Figure 8 The detailed flowchart of step S810.

[0017] Figure 11 This is a flowchart of an operation method of an event control device according to another embodiment of the present invention.

[0018] Figure 12 for Figure 11 The detailed flowchart of step S1104.

[0019] Figure 13 for Figure 11 The detailed flowchart of step S1108.

[0020] Figure 14 for Figure 13 The detailed flowchart of step S1302.

[0021] Attached icon number

[0022] 100, 300, 400, 500, 600, 710_1~710_N: Event control device

[0023] 110_1,310_1,610_1: First selection module

[0024] 110_2,310_2,610_2: Second selection module

[0025] 120,320: First processing module

[0026] 121_1,321_1: First inverter

[0027] 121_2,321_2: Second inverter

[0028] 122_1,322_1: First selection unit

[0029] 122_2,322_2: Second selection unit

[0030] 123_1, 323_1: First logic processing unit

[0031] 130, 330, 630: Channel connection modules

[0032] 140, 340, 410, 640: Output modules

[0033] 141_1~141_3, 341_1~341_3, 430_1~430_3: Synchronization Units

[0034] 142_1~142_3, 342_1~342_3, 440_1~440_3: Output selection unit

[0035] 310_3, 610_3: Third Selection Module

[0036] 321_3: Third inverter

[0037] 322_3: Third Selection Unit

[0038] 323_2: Second Logic Processing Unit

[0039] 420: Second processing module

[0040] 421_1~421_3: Second processing unit

[0041] 422_1~422_3: First AND gate

[0042] 423_1~423_3: Second AND gate

[0043] 424_1~424_3: Third AND gate

[0044] 425_1~425_3: Third Logic Processing Unit

[0045] 426_1~426_3: Mutual exclusion OR gate

[0046] 700: Event Control System

[0047] CH0, CH1, CH2: Output channels

[0048] S0, S1, S2: Event signals

[0049] SEL1_1~SEL1_3, SEL2_1~SEL2_3, SEL3_1~SEL3_3: Selection signals

[0050] S0': First inverted event signal

[0051] S1': Second phase-reversing event signal

[0052] PS1: First signal processing

[0053] PS2: Second signal processing

[0054] PS3: Third Signal Processor

[0055] PS3': Third Inverting Signal Processor

[0056] SS1: First synchronous output signal

[0057] CLK1~CLK3: Clock signals

[0058] ES1_1~ES1_3: First Start Signal

[0059] ES2_1~ES2_3: Second start signal

[0060] ES3_1~ES3_3: Third Start Signal

[0061] ES4_1~ES4_3: Fourth Start Signal

[0062] S802~S810, S902~S910, S1002~S1004, S1102~S1108, S1202~S1206, S1302~S1306, S1402~S1408: Steps Detailed Implementation

[0063] The channel connection module 130 specifies that the first output channel CH0 outputs the first processing signal PS1, but the present invention is not limited thereto. In some embodiments, the channel connection module 130 may specify either the first output channel CH1 or the second output channel to output the first processing signal PS1, which can achieve the same or similar effects.

[0064] Figure 1 This is a schematic diagram showing the correspondence between the first event signal, the second event signal, the first processing signal, and the first synchronization output signal according to an embodiment of the present invention. Figure 2 It can correspond to Figure 1 Event control device 100. In Figure 2 In this diagram, S0 represents the first event signal, S1 represents the second event signal, PS1 represents the first processing signal, and SS1 represents the first synchronization output signal. Please refer to [reference needed]. Figure 1 and Figure 2 The first selection module 110_1 outputs a first event signal S0, and the second selection module 110_2 outputs a second event signal S1. Selection unit 122_1 outputs the first event signal S0, and selection unit 122_2 outputs the second event signal S1. The first logic processing unit 123_1 performs a first logic processing (e.g., OR logic processing) on ​​the first event signal S0 and the second event signal S1 to generate a first processing signal PS1.

[0065] The channel connection module 130 specifies the first output channel CH0 to output the first processing signal PS1. The synchronization unit 141_1 uses CLK1 to perform synchronization processing on the first processing signal PS1 (e.g., negative edge triggering) to generate the first synchronization output signal SS1. However, this embodiment is not limited to this. In other embodiments, the synchronization unit 141_1 may also use the clock signal CLK1 and, for example, positive edge triggering to perform synchronization processing on the first processing signal PS1 to generate the first synchronization output signal SS1. The selection unit 142_1 can select to output either the first processing signal PS1 or the first synchronization output signal SS1. The first processing signal PS1 can, for example, be provided to the next-level event control device 100 for subsequent event connection operations. The first synchronization output signal SS1 can, for example, be provided to the target peripheral device to instruct the target device to perform corresponding operations.

[0066] Figure 3 This is a schematic diagram of an event control device according to another embodiment of the present invention. Please refer to... Figure 3The event control device 300 may include a first selection module 310_1, a second selection module 310_2, a third selection module 310_3, a first processing module 320, a channel connection module 330, and an output module 340.

[0067] The first selection module 310_1 can receive multiple event signals S0, S1, S2 and a selection signal SEL1_1, and output a first event signal S0 from the event signals S0, S1, S2 according to the selection signal SEL1_1. In this embodiment, the first selection module 110_1 can be a multiplexer. In addition, the above-mentioned event signals S0, S1, S2 are generated by peripheral devices, such as analog-to-digital converters, timers, etc., but the embodiments of the present invention are not limited to this.

[0068] The second selection module 310_2 can receive event signals S0, S1, S2 and selection signal SEL1_2, and output a second event signal S1 from event signals S0, S1, S2 based on selection signal SEL1_2. In this embodiment, the second selection module 310_2 can be a multiplexer. The third selection module 310_3 can receive event signals S0, S1, S2 and selection signal SEL1_3, and output a third event signal S2 from event signals S0, S1, S2 based on selection signal SEL1_3. In this embodiment, the third selection module 310_3 can be a multiplexer.

[0069] The first processing module 320 is coupled to the first selection module 310_1, the second selection module 310_2, and the third selection module 310_3. The first processing module 320 can receive a first event signal S0, a second event signal S1, and a third event signal S2. The first processing module 320 can perform first logic processing on the first event signal S0 or the first inverted event signal S0' and the second event signal S1 or the second inverted event signal S1' to generate a first processing signal PS1. The method by which the first processing module 320 generates the first processing signal PS1 can be found in [reference needed]. Figure 1 The description of an embodiment of the first processing module 120 is omitted here.

[0070] The first processing module 320 can perform second logic processing on the third event signal S2 or the third inverted event signal S2' to generate a second processed signal PS2. In this embodiment, the second logic processing is, for example, no processing. That is, the first processing module 320 can use the third event signal S2 or the third inverted event signal S2' as the second processed signal PS2 and output the second processed signal PS2. In this embodiment, the third inverted event signal S2' is the inverted signal of the third event signal S2.

[0071] The channel connection module 330 can receive the first processing signal PS1 and the second processing signal PS2, and specify the first output channel (e.g., CH0) of the output channels CH0, CH1, and CH2 to output the first processing signal PS1, and specify the second output channel (e.g., CH1) of the output channels CH0, CH1, and CH2 to output the second processing signal PS2.

[0072] The output module 340 can receive a first processing signal PS1 and a second processing signal PS2, and generate a first output signal or a first synchronous output signal based on the first processing signal PS1, and generate a second output signal or a second synchronous output signal based on the second processing signal PS2.

[0073] Furthermore, the first processing module 320 may include a first inverter 321_1, a second inverter 321_2, a third inverter 321_3, a first selection unit 322_1, a second selection unit 322_2, a third selection unit 322_3, a first logic processing unit 323_1, and a second logic processing unit 323_2. In this embodiment, the first inverter 321_1, the second inverter 321_2, the first selection unit 322_1, the second selection unit 322_2, and the first logic processing unit 323_1 and... Figure 1 The first inverter 121_1, the second inverter 121_2, the first selection unit 122_1, the second selection unit 122_2, and the first logic processing unit 123_1 are the same or similar, and can be referred to Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0074] The third inverter 321_3 has an input terminal and an output terminal. The input terminal of the third inverter 321_3 receives the third event signal S2, and the output terminal of the third inverter 321_3 generates the third inverted event signal S2'. That is, the third inverter 321_3 receives the third event signal S2 and inverts the third event signal S2 to generate the third inverted event signal S2'.

[0075] The third selection unit 322_1 can receive the third event signal S2, the third inverted event signal S2' and the selection signal SEL2_3, and select to output the third event signal S2 or the third inverted event signal S2' according to the selection signal SEL2_3.

[0076] The second logic processing unit 323_1 can receive the third event signal S2 or the third inverted event signal S2', and perform second logic processing on the third event signal S2 or the third inverted event signal S2' to generate the second processing signal PS2.

[0077] The output module 340 may include synchronization units 341_1, 341_2, 341_3, output selection units 341_1, 342_2, and 342_3. Synchronization unit 341_1 is coupled to the first output channel CH0 of the channel connection module 330, receives the signal output from the first output channel CH0 (e.g., the first processing signal PS1) and the clock signal CLK1, and uses the clock signal CLK1 to perform synchronization processing on the signal output from the first output channel CH0 (e.g., the first processing signal PS1) to generate a synchronization output signal (e.g., the first synchronization output signal SS1).

[0078] Synchronization unit 341_2 is coupled to the second output channel CH2 of channel connection module 330, receives the signal (e.g., the second processing signal PS2) and clock signal CLK2 output from second output channel CH1, and uses clock signal CLK2 to perform synchronization processing on the signal (e.g., the second processing signal PS2) output from second output channel CH1 to generate a synchronization output signal (e.g., the second synchronization output signal SS2). Synchronization unit 341_3 is coupled to the third output channel CH2 of channel connection module 330, receives the signal output from third output channel CH2 and clock signal CLK3, and uses clock signal CLK3 to perform synchronization processing on the signal output from third output channel CH2 to generate a synchronization output signal.

[0079] The output selection unit 342_1 is coupled to the first output channel CH0 of the channel connection module 330 and the synchronization unit 341_1. It receives the signal output by the first output channel CH0 (e.g., the first processing signal PS1) and the synchronization output signal generated by the synchronization unit 341_1 (e.g., the first synchronization output signal SS1). It outputs the signal output by the first output channel CH0 (e.g., the first processing signal PS1) as the first output signal or outputs the synchronization output signal generated by the synchronization unit 341_1 (e.g., the first synchronization output signal SS1).

[0080] Output selection unit 342_2 is coupled to the second output channel CH1 of channel connection module 330 and synchronization unit 341_2. It receives the signal output from the second output channel CH1 (e.g., the second processing signal PS2) and the synchronization output signal generated by synchronization unit 341_2 (e.g., the second synchronization output signal SS2), and outputs the signal output from the second output channel CH1 (e.g., the second processing signal PS2) as the first output signal or outputs the synchronization output signal generated by synchronization unit 341_2 (e.g., the second synchronization output signal SS2). Output selection unit 342_3 is coupled to the third output channel CH2 of channel connection module 130 and synchronization unit 341_3. It receives the signal output from the third output channel CH2 and the synchronization output signal generated by synchronization unit 341_3, and outputs the signal output from the third output channel CH2 as the first output signal or outputs the synchronization output signal generated by synchronization unit 341_3.

[0081] Figure 4 This is a schematic diagram of an event control device according to another embodiment of the present invention. Please refer to... Figure 4 The event control device 400 may include a first selection module 310_1, a second selection module 310_2, a third selection module 310_3, a first processing module 320, a channel connection module 330, and an output module 410.

[0082] In this embodiment, the first selection module 310_1, the second selection module 310_2, the third selection module 310_3, the first processing module 320, and the channel connection module 330 are connected with... Figure 3 The first selection module 310_1, the second selection module 310_2, the third selection module 310_3, the first processing module 320, and the channel connection module 330 are the same or similar, so they will not be described in detail here.

[0083] Additionally, the first processing module 320 may include a first inverter 321_1, a second inverter 321_2, a third inverter 321_3, a first selection unit 322_1, a second selection unit 322_2, a third selection unit 322_3, a first logic processing unit 323_1, and a second logic processing unit 323_2. In this embodiment, the first inverter 321_1, the second inverter 321_2, the third inverter 321_3, the first selection unit 322_1, the second selection unit 322_2, the third selection unit 322_3, the first logic processing unit 323_1, and the second logic processing unit 323_2 are... Figure 1The first inverter 321_1, the second inverter 321_2, the third inverter 321_3, the first selection unit 322_1, the second selection unit 322_2, the third selection unit 322_3, the first logic processing unit 323_1, and the second logic processing unit 323_2 are the same or similar, and can be referenced. Figure 3 The embodiments are described in detail here, so they will not be repeated here.

[0084] The output module 410 is coupled to the channel connection module 330, and can receive the first processing signal PS1 provided by the first output channel CH0 and the second processing signal PS2 provided by the second output channel CH1, and generate a first output signal or a first synchronous output signal SS1 based on the first processing signal PS1 and the second processing signal PS2.

[0085] Furthermore, the output module 410 may include a second processing module 420, a synchronization unit 430_1, a synchronization unit 430_2, a synchronization unit 430_3, an output selection unit 440_3, an output selection unit 440_2, and an output selection unit 440_3.

[0086] The second processing module 420 is coupled to the channel connection module 330. The second processing module 420 can receive at least the first processing signal PS1 and the second processing signal PS2 output by the channel connection module 330, and perform third logic processing on the first processing signal PS1 and the second processing signal PS2 to generate a third processing signal PS3 or a third inverted processing signal PS3'. In this embodiment, the third logic processing may include AND processing, OR processing, inverse AND processing, mutually exclusive OR processing, etc.

[0087] Synchronization unit 430_1 is coupled to the second processing module 420, receives the third processing signal PS3 or the third inverted processing signal PS3' and the clock signal CLK1, and uses the clock signal CLK1 to synchronize the third processing signal PS3 or the third inverted processing signal PS3' to generate the first synchronous output signal SS1. Synchronization unit 430_2 is coupled to the second processing module 420, receives the third processing signal or the third inverted processing signal generated by the second processing module 420 and the clock signal CLK2, and uses the clock signal CLK2 to synchronize the third processing signal or the third inverted processing signal to generate the second synchronous output signal. Synchronization unit 430_3 is coupled to the second processing module 420, receives the third processing signal or the third inverted processing signal generated by the second processing module 420 and the clock signal CLK3, and uses the clock signal CLK3 to synchronize the third processing signal or the third inverted processing signal to generate the third synchronous output signal.

[0088] Output selection unit 440_1 is coupled to the second processing module 420 and the synchronization unit 430_1. It receives the third processing signal PS3 or the third inverted processing signal PS3' and the first synchronization output signal SS1, and outputs the third processing signal PS3 or the third inverted processing signal PS3' as the first output signal or outputs the first synchronization output signal SS1. Output selection unit 440_2 is coupled to the second processing module 420 and the synchronization unit 430_2. It receives the third processing signal or the third inverted processing signal and the second synchronization output signal, and outputs the third processing signal or the third inverted processing signal as the second output signal or outputs the second synchronization output signal. Output selection unit 430_3 is coupled to the second processing module 420 and the synchronization unit 430_3. It receives the third processing signal or the third inverted processing signal and the third synchronization output signal, and outputs the third processing signal or the third inverted processing signal as the third output signal or outputs the third synchronization output signal.

[0089] In this embodiment, the second processing module 420 may include a plurality of second processing units 421_1, 421_2, and 421_3. The second processing unit 421_1 may include a first AND gate 422_1, a second AND gate 423_1, a third AND gate 424_1, a third logic processing unit 425_1, and a mutex OR gate 426_1.

[0090] The first AND gate 422_1 has a first terminal, a second terminal, and an output terminal. The first terminal of the first AND gate 422_1 receives a first start signal ES1_1, the second terminal of the first AND gate 422_1 is coupled to the first output channel CH0 and receives the signal output by the first output channel CH0 (e.g., the first processing signal PS1), and the first terminal of the first AND gate 422_1 outputs a first AND signal. The second AND gate 423_1 has a first terminal, a second terminal, and an output terminal. The first terminal of the second AND gate 422_1 receives a second start signal ES2_1, the second terminal of the second AND gate 423_1 is coupled to the second output channel CH1 and receives the signal output by the second output channel CH1 (e.g., the second processing signal PS2), and the first terminal of the second AND gate 423_1 outputs a second AND signal. The third AND gate 424_1 has a first terminal, a second terminal, and an output terminal. The first terminal of the third AND gate 424_1 receives the fourth start signal ES4_1. The second terminal of the third AND gate 424_1 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2. The first terminal of the third AND gate 424_1 outputs the third AND signal.

[0091] The third logic processing unit 425_1 is coupled to the outputs of the first AND gate 422_1, the second AND gate 423_1, and the third AND gate 424_1. It receives the first AND signal, the second AND signal, and the third AND signal, and performs third logic processing on these signals to generate the third processing signal PS3. The mutex OR gate 426_1 has a first terminal, a second terminal, and an output terminal. The first terminal of the mutex OR gate 426_1 receives the third processing signal PS3, the second terminal receives the third start signal ES3_1, and the output terminal of the mutex OR gate 426_1 generates either the third processing signal PS3 or the third inverted processing signal PS3'.

[0092] The second processing unit 421_2 may include a first AND gate 422_2, a second AND gate 423_2, a third AND gate 424_2, a third logic processing unit 425_2, and a mutex OR gate 426_2.

[0093] First AND gate 422_2 has a first terminal, a second terminal, and an output terminal. The first terminal of first AND gate 422_2 receives a first start signal ES1_2, the second terminal of first AND gate 422_2 is coupled to the first output channel CH0 and receives the signal output by the first output channel CH0, and the first terminal of first AND gate 422_2 outputs a first AND signal. Second AND gate 423_2 has a first terminal, a second terminal, and an output terminal. The first terminal of second AND gate 423_2 receives a second start signal ES2_2, the second terminal of second AND gate 423_2 is coupled to the second output channel CH1 and receives the signal output by the second output channel CH1, and the first terminal of second AND gate 423_2 outputs a second AND signal. Third AND gate 424_2 has a first terminal, a second terminal, and an output terminal. The first terminal of third AND gate 424_2 receives a fourth start signal ES4_2, the second terminal of third AND gate 424_2 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2, and the first terminal of third AND gate 424_2 outputs a third AND signal.

[0094] The third logic processing unit 425_2 is coupled to the outputs of the first AND gate 422_2, the second AND gate 423_2, and the third AND gate 424_2. It receives the first AND signal, the second AND signal, and the third AND signal, and performs third logic processing on these signals to generate a third processed signal. The mutex OR gate 426_2 has a first terminal, a second terminal, and an output terminal. The first terminal of the mutex OR gate 426_2 receives the third processed signal PS3, the second terminal receives the third start signal ES3_2, and the output terminal of the mutex OR gate 426_2 generates either the third processed signal or a third inverted processed signal.

[0095] The second processing unit 421_3 may include a first AND gate 422_3, a second AND gate 423_3, a third AND gate 424_3, a third logic processing unit 425_3, and a mutex OR gate 426_3.

[0096] First AND gate 422_3 has a first terminal, a second terminal, and an output terminal. The first terminal of first AND gate 422_3 receives a first start signal ES1_3, the second terminal of first AND gate 422_3 is coupled to the first output channel CH0 and receives the signal output by the first output channel CH0, and the first terminal of first AND gate 422_3 outputs a first AND signal. Second AND gate 423_3 has a first terminal, a second terminal, and an output terminal. The first terminal of second AND gate 423_3 receives a second start signal ES2_3, the second terminal of second AND gate 423_3 is coupled to the second output channel CH1 and receives the signal output by the second output channel CH1, and the first terminal of second AND gate 423_3 outputs a second AND signal. Third AND gate 424_3 has a first terminal, a second terminal, and an output terminal. The first terminal of third AND gate 424_3 receives a fourth start signal ES4_3, the second terminal of third AND gate 424_3 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2, and the first terminal of third AND gate 424_3 outputs a third AND signal.

[0097] The third logic processing unit 425_3 is coupled to the output of the first AND gate 422_3, the output of the second AND gate 423_3 and the output of the third AND gate 424_3. It receives the first AND signal, the second AND signal and the third AND signal, and performs third logic processing on the first AND signal, the second AND signal and the third AND signal to generate a third processed signal.

[0098] The OR gate 426_3 has a first terminal, a second terminal, and an output terminal. The first terminal of the OR gate 426_3 receives a third processing signal, the second terminal of the OR gate 426_3 receives a third start signal ES3_3, and the output terminal of the OR gate 426_3 generates either the third processing signal or a third inverted processing signal.

[0099] In this embodiment, the number of first AND gates 422_1 to 422_3, second AND gates 423_1 to 423_3, and third AND gates 424_1 to 424_3 corresponds to the number of output channels CH0, CH1, and CH2 of the channel connection module 330.

[0100] Furthermore, in the aforementioned embodiments, the first processing signal PS1 and the second processing signal PS2 are provided to the third logic processing unit 425_1, and the third logic processing unit 425_1 performs third logic processing (e.g., AND processing, OR processing, NOT AND processing, mutual exclusion OR processing, etc.) on the first processing signal PS1 and the second processing signal PS2, but the embodiments of the present invention are not limited thereto. In some embodiments, the first processing signal PS1 and the second processing signal PS2 may be provided to the third logic processing units 425_1 and 425_2 respectively, and the third logic processing units 425_1 and 425_2 may perform third logic processing on the first processing signal PS1 and the second processing signal PS2. In this embodiment, the third logic processing of the third logic processing units 425_1 and 425_2 may be, for example, no processing. That is, the third logic processing unit 425_1 may use the first processing signal PS1 as the third processing signal PS3 output by the third logic processing unit 425_1, and the third logic processing unit 425_2 may use the second processing signal PS2 as the third processing signal PS3 output by the third logic processing unit 425_2.

[0101] Figure 5 This is a schematic diagram showing the correspondence between the first event signal, the second event signal, the first processing signal, the third event signal, the second processing signal, the third processing signal, and the first synchronous output signal according to an embodiment of the present invention. Figure 5 It can correspond to Figure 4 Event control device 400. In Figure 5 In this diagram, S0 represents the first event signal, S1 represents the second event signal, PS1 represents the first processing signal, S2 represents the third event signal, PS2 represents the second processing signal, PS3 represents the third processing signal, and SS1 represents the first synchronization output signal. Please refer to [reference needed]. Figure 4 and Figure 5 The first selection module 310_1 outputs the first event signal S0, the second selection module 310_2 outputs the second event signal S1, and the third selection module 310_3 outputs the third event signal S2. The selection unit 322_1 outputs the first event signal S0, the selection unit 322_2 outputs the second event signal S1, and the selection unit 322_3 outputs the third event signal S2.

[0102] The first logic unit 323_1 performs a first logic processing (e.g., "OR" logic processing) on ​​the first event signal S0 and the second event signal S1 to generate a first processing signal PS1. The second logic unit 323_2 performs a second logic processing (e.g., "no processing") on the second event signal S2 to use the second event signal S2 as the second processing signal PS2.

[0103] The channel connection module 330 designates the first output channel CH0 to output the first processing signal PS1 and the second output channel CH1 to output the second processing signal PS2. The first start signal ES1_1 and the second start signal ES2_1 are enabled, and the first start signals ES1_2 to ES1_3, the second start signals ES2_2 to ES2_3, the fourth start signal ES4_1 to ES4_3, and the third start signal ES3_1 to ES3_3 are disabled.

[0104] The first AND signal output by the first AND gate 422_1 is the first processing signal PS1, and the second AND signal output by the second AND gate 423_1 is the second processing signal PS2. The third logic unit 425_1 performs third logic processing (e.g., OR logic processing) on ​​the first processing signal PS1 and the second processing signal PS2 to generate a third processing signal PS3. The synchronization unit 430_1 uses the clock signal CLK1 to perform synchronization processing (e.g., negative edge triggering) on ​​the third processing signal PS3 to generate a first synchronization output signal SS1. However, this embodiment is not limited to this. In other embodiments, the synchronization unit 430_1 can also use the clock signal CLK1 and, for example, positive edge triggering to perform synchronization processing on the third processing signal PS3 to generate the first synchronization output signal SS1. The selection unit 440_1 can selectively output either the third processing signal PS1 or the first synchronization output signal SS1. The third processing signal PS3 can, for example, be provided to the next-level event control device 400 for subsequent event linking operations. The first synchronization output signal SS1 can, for example, be provided to the target peripheral device to instruct the target device to perform corresponding operations.

[0105] Figure 6 This is a schematic diagram of an event control device according to another embodiment of the present invention. Please refer to... Figure 6 The event control device 600 includes a first selection module 610_1, a second selection module 610_2, a channel connection module 630, and an output module 640. In this embodiment, the first selection module 610_1 and the second selection module 610_2 are connected to the output module 640. Figure 1 The first selection module 110_1 and the second selection module 110_2 are the same or similar, and can be referred to Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0106] The channel connection module 630 is coupled to at least the first selection module 610_1 and the second selection module 610_2. The channel connection module 630 can receive at least the first event signal S0 and the second event signal S1, and designate the first output channel (e.g., CH0) of the output channels CH0, CH1, and CH2 to output the first event signal S0, and designate the second output channel (e.g., CH1) of the output channels CH0, CH1, and CH2 to output the second event signal S1.

[0107] The output module 640 is coupled to the channel connection module 630, receives the first event signal S0 and the second event signal S1, performs a fourth logic operation on the first event signal S0 and the second event signal S1 to generate a fourth processing signal or a fourth reverse processing signal, and generates a fourth output signal or a fourth synchronous output signal based on the fourth processing signal or the fourth reverse processing signal.

[0108] Furthermore, the output module 640 may include a second processing module 420, synchronization units 430_1, 430_2, 430_3, and output selection units 440_3, 440_2, and 440_3. In this embodiment, the second processing module 420, synchronization units 430_1, 430_2, 430_3, output selection units 440_3, 440_2, and 440_3, along with... Figure 5 The second processing module 420, synchronization unit 430_1, synchronization unit 430_2, synchronization unit 430_3, output selection unit 440_3, output selection unit 440_2, and output selection unit 440_3 are the same or similar, and can be referred to. Figure 5 The embodiments are described in detail here, so they will not be repeated here.

[0109] in addition, Figure 6 The second processing module 420 may also include second processing units 421_1, 421_2, and 421_3. Figure 6 The second processing units 421_1, 421_2, 421_3 and their internal components and Figure 5 The second processing units 421_1, 421_2, and 421_3 and their internal components are the same or similar, and can be referred to... Figure 5 The embodiments are described in detail here, so they will not be repeated here.

[0110] Furthermore, the event control device 600 can also receive the event signal S2 and includes a third selection module 610_3. The first selection module 610_1, the second selection module 610_2, and the third selection module 610_3 can interact with... Figure 3 or Figure 4The first selection module 310_1, the second selection module 310_2, and the third selection module 310_3 are the same or similar, and can be referred to... Figure 3 or Figure 4 The description of the embodiments is omitted here. In this way, the event control device 600 can also increase the flexibility of event connections and usage scenarios, thereby increasing ease of use.

[0111] Figure 7 This is a schematic diagram of an event control system according to an embodiment of the present invention. Please refer to... Figure 7 The event control system 700 includes multiple event control devices 710_1 to 710_N, where N is a positive integer greater than 1. The event control devices 710_1 to 710_N are connected in series sequentially, and each of the event control devices 710_1 to 710_N can be implemented by event control devices 100, 300, 400, 500, and 600, respectively. In this way, the event control system 700 can achieve increased flexibility in event connections and usage scenarios, thereby increasing ease of use.

[0112] Based on the above description, this embodiment of the invention provides an operation method for an event control device. Figure 8 This is a flowchart of an operation method of an event control device according to an embodiment of the present invention. In step S802, a first selection module receives multiple event signals and outputs a first event signal. In step S804, a second selection module receives event signals and outputs a second event signal.

[0113] In step S806, the first processing module performs first logical processing on the first event signal or the first inverted event signal and the second event signal or the second inverted event signal to generate a first processed signal. In step S808, the channel connection module receives the first processed signal and designates the first output channel of the multiple output channels of the channel connection module to output the first processed signal. In step S810, the output module receives the first processed signal and generates a first output signal or a first synchronous output signal based on the first processed signal. In this embodiment, the first logical processing includes, for example, AND processing, OR processing, NOT AND processing, and mutual exclusion OR processing.

[0114] Figure 9 for Figure 8The detailed flowchart of step S806 is as follows: In step S902, the first event signal is inverted by the first inverter of the first processing module to generate a first inverted event signal. In step S904, the second event signal is inverted by the second inverter of the first processing module to generate a second inverted event signal. In step S906, the first selection unit of the first processing module selects to output either the first event signal or the first inverted event signal. In step S908, the second selection unit of the first processing module selects to output either the second event signal or the second inverted event signal. In step S910, the first logic processing unit of the first processing module performs first logic processing on the first event signal or the first inverted event signal and the second event signal or the second inverted event signal to generate a first processed signal.

[0115] Figure 10 for Figure 8 The detailed flowchart of step S810 is as follows: In step S1002, the first processing signal is synchronized by the synchronization unit of the output module to generate a first synchronization output signal. In step S1004, the first processing signal is output as a first output signal or output as a first synchronization output signal by the output selection unit of the output module.

[0116] Figure 11 This is a flowchart of an operation method for an event control device according to another embodiment of the present invention. In this embodiment, steps S802 to S808 are... Figure 8 Steps S802 to S808 are the same or similar, and can be referred to Figure 8 The embodiments are described in detail here, so they will not be repeated here.

[0117] In step S1102, the third selection module receives the event signal and outputs the third event signal. In step S1104, the first processing module performs second logic processing on the third event signal or the third inverted event signal to generate a second processed signal. In step S1106, the channel connection module receives the second processed signal and specifies the second output channel of the channel connection module to output the second processed signal. In step S1108, the output module receives the first processed signal and the second processed signal, and generates a first output signal or a first synchronous output signal based on the first processed signal and the second processed signal.

[0118] Figure 12 for Figure 11A detailed flowchart of step S1104 is provided. In step S1202, the third event signal is inverted by the third inverter of the first processing module to generate a third inverted event signal. In step S1204, the third selection unit of the first processing module selects to output either the third event signal or the third inverted event signal. In step S1206, the second logic processing unit of the first processing module performs second logic processing on the third event signal or the third inverted event signal to generate a second processed signal. In this embodiment, the second logic processing is, for example, no processing.

[0119] Figure 13 for Figure 11 The detailed flowchart of step S1108 is as follows: In step S1302, the first processed signal and the second processed signal undergo third logic processing through the second processing module of the output module to generate a third processed signal or a third inverted processed signal. In step S1304, the third processed signal or the third inverted processed signal undergoes synchronization processing through the synchronization unit of the output module to generate a first synchronized output signal. In step S1306, the third processed signal or the third inverted processed signal is output as the first output signal or the first synchronized output signal is output through the output selection unit of the output module.

[0120] Figure 14 for Figure 13 A detailed flowchart of step S1302 is provided. In step S1402, the first start signal and the first processing signal are received through the first AND gate of the second processing module, and a first AND signal is output. In step S1404, the second start signal and the second processing signal are received through the second AND gate of the second processing module, and a second AND signal is output. In step S1406, the first AND signal and the second AND signal are received through the third logic processing unit of the second processing module, and the first AND signal and the second AND signal are subjected to third logic processing to generate a third processing signal. In step S1408, the third processing signal and the third start signal are received through the mutex OR gate of the second processing module, and a third processing signal or a third inverted processing signal is generated. In this embodiment, the third logic processing includes, for example, AND processing, OR processing, inverse AND processing, and mutex OR processing.

[0121] It is worth noting that, Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14The order of the steps described is for illustrative purposes only and is not intended to limit the order of steps in the embodiments of the present invention. The order of the steps described above can be changed by the user as needed. Furthermore, additional steps can be added or fewer steps can be used without departing from the spirit and scope of the present invention.

[0122] In summary, the event control device and its operating method disclosed in this invention perform first logical processing on at least a first event signal or a first inverted event signal and a second event signal or a second inverted event signal through a first processing module to generate a first processed signal. A channel connection module specifies a first output channel to output the first processed signal, and an output module generates a first output signal or a first synchronous output signal based on the first processed signal. This effectively increases the flexibility and application scenarios of event connections, thereby enhancing ease of use.

[0123] Furthermore, the first processing module in this embodiment can further perform second logic processing on the third event signal or the third inverted event signal to generate a second processing signal. The channel connection module specifies the output channel of the second output channel to output the first processing signal, and the output module generates a second output signal or a second synchronous output signal based on the second processing signal. In addition, the output module in this embodiment can further perform third logic processing on the first processing signal and the second processing signal to generate a first output signal or a first synchronous output signal. This further increases the flexibility of event connection and the range of application scenarios.

[0124] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent claims.

Claims

1. An event control device, characterized in that, include: A first selection module receives multiple event signals and outputs a first event signal; A second selection module receives the multiple event signals and outputs a second event signal; A first processing module, coupled to the first selection module and the second selection module, receives the first event signal and the second event signal. The first processing module performs a first logic processing on the first event signal or a first inverted event signal and the second event signal or a second inverted event signal to generate a first processing signal. A channel connection module is coupled to the first processing module and has multiple output channels. The channel connection module receives the first processing signal and designates a first output channel of the multiple output channels to output the first processing signal. as well as An output module, coupled to the channel connection module, receives the first processing signal and generates a first output signal or a first synchronous output signal based on the first processing signal. The first processing module includes: A first inverter receives the first event signal and inverts the first event signal to generate the first inverted event signal; A second inverter receives the second event signal and inverts the second event signal to generate the second inverted event signal; A first selection unit receives the first event signal and the first inverted event signal, and selects to output either the first event signal or the first inverted event signal; and A second selection unit receives the second event signal and the second inverted event signal, and selects to output the second event signal or the second inverted event signal.

2. The event control device as described in claim 1, characterized in that, The first processing module further includes: A first logic processing unit receives the first event signal or the first inverted event signal and the second event signal or the second inverted event signal, and performs the first logic processing on the first event signal or the first inverted event signal and the second event signal or the second inverted event signal to generate the first processed signal.

3. The event control device as described in claim 1 or 2, characterized in that, Including: A third selection module, coupled to the first processing module, receives the multiple event signals and outputs a third event signal; The first processing module further receives the third event signal, and performs a second logic processing on the third event signal or a third inverted event signal to generate a second processing signal. The channel connection module further receives the second processing signal and designates a second output channel of the output channels to output the second processing signal; The output module further receives the second processing signal and generates a first output signal or a first synchronous output signal based on the first processing signal and the second processing signal.

4. The event control device as described in claim 3, characterized in that, The first processing module further includes: A third inverter receives the third event signal and inverts the third event signal to generate the third inverted event signal; A third selection unit receives the third event signal and the third inverted event signal, and selects to output either the third event signal or the third inverted event signal; and A second logic processing unit receives the third event signal or the third inverted event signal, and performs the second logic processing on the third event signal or the third inverted event signal to generate the second processed signal.

5. The event control device as described in claim 3, characterized in that, The output module includes: A second processing module, coupled to the channel connection module, receives the first processing signal and the second processing signal, and performs a third logic processing on the first processing signal and the second processing signal to generate a third processing signal or a third inverted processing signal. A synchronization unit, coupled to the second processing module, receives the third processing signal or the third inverted processing signal, and performs synchronization processing on the third processing signal or the third inverted processing signal to generate the first synchronization output signal; and An output selection unit is coupled to the second processing module and the synchronization unit, receives the third processing signal or the third inverted processing signal and the first synchronization output signal, and outputs the third processing signal or the third inverted processing signal as the first output signal or outputs the first synchronization output signal.

6. The event control device as described in claim 5, characterized in that, The second processing module includes: A first AND gate has a first terminal, a second terminal and an output terminal. The first terminal of the first AND gate receives a first start signal, the second terminal of the first AND gate receives a first processing signal, and the first terminal of the first AND gate outputs a first AND signal. A second AND gate has a first terminal, a second terminal and an output terminal. The first terminal of the second AND gate receives a second start signal, the second terminal of the second AND gate receives a second processing signal, and the first terminal of the second AND gate outputs a second AND signal. A third logic processing unit, coupled to the output of the first AND gate and the output of the second AND gate, receives the first AND signal and the second AND signal, and performs the third logic processing on the first AND signal and the second AND signal to generate the third processed signal; and A mutex gate has a first terminal, a second terminal and an output terminal. The first terminal of the mutex gate receives the third processing signal, the second terminal of the mutex gate receives a third start signal, and the output terminal of the mutex gate generates the third processing signal or the third inverted processing signal.

7. The event control device as described in claim 6, characterized in that, The third logical processing includes AND processing, OR processing, NOT AND processing, and MEP processing.

8. The event control device as claimed in claim 1, characterized in that, The output module includes: A synchronization unit, coupled to the channel connection module, receives the first processing signal and performs synchronization processing on the first processing signal to generate the first synchronization output signal; and An output selection unit is coupled to the channel connection module and the synchronization unit, receives the first processing signal and the first synchronization output signal, and outputs the first processing signal as the first output signal or outputs the first synchronization output signal.

9. A method for operating an event control device, characterized in that, include: A first selection module receives multiple event signals and outputs a first event signal. The system receives the multiple event signals through a second selection module and outputs a second event signal. A first processing module performs a first logic processing on the first event signal or a first inverted event signal and the second event signal or a second inverted event signal to generate a first processed signal. The first processing signal is received through a channel connection module, and the first processing signal is output through a first output channel of a plurality of output channels of the channel connection module. The first processing module receives the first processing signal through an output module and generates a first output signal or a first synchronous output signal based on the first processing signal. The first processing module includes a first inverter, a second inverter, a first selection unit, and a second selection unit. The first event signal is received by the first inverter and the first event signal is inverted to generate a first inverted event signal; The second event signal is received by the second inverter and the second event signal is inverted to generate a second inverted event signal; The first selection unit receives the first event signal and the first inverted event signal, and selects to output either the first event signal or the first inverted event signal. as well as The second selection unit receives the second event signal and the second inverted event signal, and selects to output either the second event signal or the second inverted event signal.

10. The operation method of the event control device as described in claim 9, characterized in that, The output module receives the first processing signal and generates the first output signal or the first synchronization output signal based on the first processing signal, including: The first processing signal is synchronized through a synchronization unit of the output module to generate the first synchronized output signal; and The first processed signal can be output as the first output signal or the first synchronous output signal can be output through an output selection unit of the output module.

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