Dedicated bounds information register file to prevent out-of-bounds memory references

Abstract

A method, system and apparatus for preventing out-of-bounds references, comprising: storing the address of a buffer in a general register, and storing boundary information (BI) for the buffer in a boundary information register; when the content of the general register is used as an address in a load or store operation, using the content of the boundary information register to determine whether the load or store is out-of-bounds.

Description

Technical Field

[0001] The present invention relates to embodiments of a method, apparatus, and system for a boundary information register file, and more particularly, but not by way of limitation, to a method, apparatus, and system for preventing out-of-bounds memory references using a dedicated boundary information register file. Background Art

[0002] Memory security vulnerabilities (eg, buffer overflows, null pointers, heap corruption, use after free, or double free, etc.) occur when software accidentally or intentionally accesses system memory in a manner that exceeds its allocated size and memory address.

[0003] Programs such as C and C++ that are widely used in some operating systems and other programs can lead to multiple memory security errors that attackers can exploit with dangerous and invasive consequences such as remote code execution or escalation of privilege flaws. For example, by reading out-of-bounds memory, an attacker may be able to bypass memory protection and obtain secret values.

[0004] Therefore, there is a need for technology that can reduce or eliminate memory security vulnerabilities in an effective manner. Summary of the invention

[0005] In view of the above and other problems, drawbacks and deficiencies in the background art, exemplary aspects of the disclosed invention provide a method, apparatus and system for a dedicated boundary information register file for preventing out-of-bounds memory references.

[0006] According to an embodiment of the present invention, a method for preventing out-of-bounds references includes: storing the address of a buffer in a general register, and storing boundary information (BI) for the buffer in a boundary information register, and when the content of the general register is used as an address in a load or store operation, using the content of the boundary information register to determine whether the load or store is out of bounds.

[0007] According to an embodiment of the present invention, a system for preventing out-of-bounds references includes: storing the address of a buffer in a general register, and storing boundary information (BI) for the buffer in a boundary information register, and when the content of the general register is used as an address in a load or store operation, using the content of the boundary information register to determine whether the load or store is out of bounds.

[0008] According to another embodiment of the present invention, a computer program product includes a computer-readable storage medium having program instructions embodied therein, and the program instructions can be read and executed by a computer to enable the computer to perform a method for preventing out-of-bounds references, the method including: storing an address of a buffer in a general register, and storing boundary information (BI) for the buffer in a boundary information register, and when the content of the general register is used as an address in a load or store operation, using the content of the boundary information register to determine whether the load or store is out of bounds.

[0009] Thus, there has been outlined rather broadly certain embodiments of the invention so that the detailed description of the invention may be better understood, and so that the invention's contribution to the art may be better appreciated. Of course, additional embodiments of the invention will be described below, and they will form the subject matter of the appended claims.

[0010] It should be understood that the present invention is not limited in its application to the construction details and component arrangements set forth in the following description or shown in the accompanying drawings. The present invention can have embodiments other than those described, and can be practiced and implemented in various ways. Moreover, it should be understood that the words and terms used herein and the abstract are for descriptive purposes and should not be considered as limiting.

[0011] Therefore, those skilled in the art will appreciate that the concepts upon which the present disclosure is based can be readily used as a basis for designing other structures, methods and systems for carrying out the several purposes of the present invention. It is therefore important that the claims be regarded as including such equivalent constructions as long as they do not depart from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Exemplary aspects of the present invention will be better understood through the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0013] Figure 1 An example system of an embodiment of the present invention is shown.

[0014] Figure 2 A boundary information table is shown.

[0015] Figure 3 A method for a boundary information table is shown.

[0016] Figure 4 It shows how to select between two BI tables, an index table and a value / key table, in an embodiment of the present invention.

[0017] Figure 5 An exemplary creation of a BI instruction of an embodiment of the present invention is shown.

[0018] Figure 6An exemplary load instruction of an embodiment of the present invention is shown.

[0019] Fig. 7A It is shown how an application can be modified to include protection against out-of-bounds memory references according to an embodiment of the present invention.

[0020] Figure 7B Shows how to modify an application using INTEL MPX to include protection against out-of-bounds memory references.

[0021] Figure 8 Exemplary storage instructions of embodiments of the present invention are shown.

[0022] Fig. 9 Shows an alternative implementation of the mapping.

[0023] Fig. 10A A method of an embodiment of the present invention is shown.

[0024] Fig. 10B A method of an embodiment of the present invention is shown.

[0025] Fig.11 An exemplary hardware / information processing system is shown in which the exemplary embodiments of the present invention may be incorporated.

[0026] Fig.12 A signal bearing storage medium for storing machine readable instructions of a program implementing a method according to an exemplary embodiment of the present invention is shown.

[0027] Fig.13 A cloud computing node according to an example embodiment of the invention is depicted.

[0028] Fig.14 A cloud computing environment is depicted according to an example embodiment of the invention.

[0029] Fig.15 Abstract model layers according to an example embodiment of the present invention are depicted. DETAILED DESCRIPTION

[0030] The present invention will now be described with reference to the accompanying drawings, wherein the same reference numerals always represent the same parts. It is emphasized that, according to convention, the various features of the drawings are not necessarily drawn to scale. On the contrary, for the sake of clarity, the sizes of the various features can be arbitrarily expanded or reduced. The exemplary embodiments provided below are for illustrative purposes and not for limiting the claims. In addition, please note that any steps can be performed in a different order, or in combination, or simultaneously. In addition, any structure and embodiment shown can be modified or combined.

[0031] Memory references beyond their boundaries may cause serious security issues. It is important to check whether each memory reference (load or store) is within its memory boundary. An existing solution is INTEL's memory protection (MPX) system. MPX introduces a new ISA (instruction set architecture) and hardware support for accurate boundary checking. In the memory, boundary information (BI) for each buffer is stored / retrieved by pointer value as a key. In the core, the pointer and its BI are in registers, and the mapping is maintained by additional instructions added by the compiler. The original calculation and boundary protection operations share the same hardware resources. There are other methods that try to remove or reduce memory security vulnerabilities. However, all these other solutions have a major problem, that is, multiple instructions need to be added, and they are also expensive to implement. As a result, the number of instructions can be increased by four times or more, and even when boundary checking is turned off, the execution time can be increased by two times or more.

[0032] The present invention solves the above-mentioned problem of memory security vulnerabilities without the problem of increasing the number of instructions as in previous solutions. Generally, the present invention introduces a dedicated register file to save boundary information for active pointers, which are in general registers. The present technology also maintains a mapping from general registers to boundary registers so that operations related to boundary checking can be performed with the original instructions. The number of instructions to be added for boundary checking will be greatly reduced. In addition, special hardware is added to perform boundary checking related operations for instructions. In addition, with the use of boundary information registers, when boundary checking operations are added to most instructions, the waiting time of these instructions will not increase.

[0033] The present invention provides accurate protection, where it protects each buffer and is accurate to the byte. The system can be applied to C / C++ applications where there is arbitrary pointer arithmetic and other programs that may have memory issues, and the number of buffers to be protected in one application can range from thousands to millions.

[0034] Figure 1 An example system of an embodiment of the present invention is shown. System 100 includes a CPU (central processing unit) core 10 and a memory 20. CPU core 10 includes instruction fetch and decode 12, ALU (arithmetic logic unit) 14, general register file 16, boundary register file 18, boundary processing unit 20. The general register file communicates with a data cache 22, while the boundary register file 18 is connected to a boundary information (BI) cache 24. BI information can be cached in a dedicated cache (BI cache 24) within the hardware organization 100. BI cache 24 limits any slowdown in access to BI tables 26 in memory 20.

[0035] The memory 20 includes a boundary information table 26, which includes an index table 28 and a value / key table 30. Thus, the boundary information (BI) table 26 is located in the memory 20.

[0036] CPU core 10 communicates information with index table 28 and value / key table 30. CPU core 10 provides data to index table 28 via the index in the pointer (path 23) and to value / key table 30 via the value of the pointer (path 25).

[0037] Boundary information (BI) includes a starting address and length for each buffer. Index table 28 includes access by index. Value / key table 30 includes access with pointer value as key. Instruction execution in CPU core 10 includes BI register 18 saving boundary information. System 100 maintains a mapping between general registers in general register file 16 and boundary information registers in boundary register file 18. Boundary information for pointers in register file 18 can be located from the original instruction. Boundary processing unit performs operations for boundary protection. Boundary register file 18 is further described in detail as follows. Registers (e.g., 128 bits) in boundary register file 18 store boundary information including the starting address and length of the buffer. System 100 ensures that the BI of the pointer in register 18 can be found by mapping, such as FB:

[0038] FB(R n )=B m : means for general register R n The BI of the pointer in register B is at the boundary m middle.

[0039] This mapping allows the boundary information to be accessible via a pointer register. The system 100 does not use separate instructions to operate on the boundary information, as seen in MPX. Additional register addresses can be added to previous instructions.

[0040] A proposed implementation of mapping FB: shadow of general registers

[0041] FB(R n )=B n .

[0042] The number of boundary registers 18 is the same as the number of general registers 16, or may be reduced if the compiler uses only a subset of general registers 16 as pointers. System 100 performs pointer arithmetic (e.g., adding R i , R j , R k ) propagates BI, and the compiler marks which operand is a pointer (R k is a pointer). BI from B k Copied to Bi .

[0043] The boundary information (BI) table 26 is described in further detail below. The BI table 26 contains at least two sub-tables, including an index table 28 and a value / key table 30.

[0044] Figure 2 Boundary information table 26 is shown, and in index table 28, each entry contains the starting address 40 and length 42 of the buffer. Each entry in value / key table 30 includes pointer value (key) 50, starting address 52 and length 54 of the buffer. Value / key table 30 can grow as needed and is searched by pointer value. Pointer value (key) 50 can be obtained from pointer value 64 of pointer 60. Index 62 of pointer 60 can be used to obtain entries of the index table.

[0045] The index table 28 may be organized as a linear table including a plurality of BI entries 29, wherein each BI entry includes a base address field 40 and an object size or length field 42. Each BI entry 29 of the index table 28 may be associated with a heap object. Accessing a particular BI entry 29 in the index table 28 corresponding to a given object may involve a single table lookup. The single table lookup may involve the use of an index 62 that may be embedded in a pointer 60 during object allocation.

[0046] The member functions or microinstructions are as follows:

[0047] Void initialize(long long int bit_mask): Builds an index bitmap from bit_mask and allocates space for the index table and value / key table

[0048] unsigned long long int get_index_bits(void*addr) : Returns the unsigned value represented by the index bits in the pointer address

[0049] Void*set_index_bits(void*addr,unsigned int v): Returns the address with the index bits set to the value v

[0050] Constant INDEX_NA: all ones, 11...1 / / index not available for this pointer

[0051] The functions get_index_bits and set_index_bits should be directly supported by the hardware.

[0052] Figure 3 A method for a boundary information table is shown.

[0053] The system 100 may create an index bitmap 202 from the bitmask and allocate space for the index table 28 and the value / key table 30 at step 204. Steps 202 and 204 may be performed using the above-mentioned instruction "Void initialize(long long int bit_mask)".

[0054] The system 100 then returns the unsigned value represented by the index bits 62 in the pointer address 206. The system 100 then returns the address with the index bits 62 set to the value v at step 208. Constant INDEX_NA: All ones, 11 ... 1, where the index is not available for this pointer at step 210. The function at step 206 ("get_index_bits") and the function at step 208 ("set_index_bits") should be directly supported in hardware.

[0055] Figure 4 It shows how to select between two BI tables, the index table 28 and the value / key table 30, in an embodiment of the present invention.

[0056] The decision to select or choose between the two BI tables 26 of the index table 28 and the value / keyword table 30 (step 232) may be made at runtime based on resource availability (index bits) 62. The binary code is identical.

[0057] The system 100 provides control to the compiler / user by allowing which boundary information table 26 (index table 28 or value / key table 30) to be used when possible, and reserves entries in the index table 28 for future buffer allocations.

[0058] In step 234, the system 100 determines whether the caller (compiler / user) makes the decision. If the determination at step 234 is "yes", then at step 240, the system 100 determines whether the index table 28 is selected by the compiler / user (caller). If the determination at step 240 is "no", the system 100 uses the value / key table 30 for the buffer. If the determination at step 240 is "yes", the system 100 uses the index table 28 for the buffer 238.

[0059] If the determination at step 234 is "no", the system 100 determines whether to select the index table 28 by runtime heuristics (236). If the determination at step 236 is "no", the system 100 uses the value / key table 30 for the buffer 242. If the determination at step 236 is "yes", the system 100 uses the index table 28 for the buffer 238.

[0060] As shown above, a simple or complex approach can be used to make the selection. A simple strategy would be to use index table 28 first. System 100 can use index table 28 for buffers whose pointers themselves involve many loads / stores. System 100 can force the use of index table 28 for pointers that will undergo type conversion in the step.

[0061] Figure 5 An example of creation 370 of a BI instruction of an embodiment of the present invention is shown.

[0062] Figure 6 An exemplary load instruction 402 of an embodiment of the present invention is shown. Note that the boundary protection operations 400 (without the bold 404) are designed to allow them to be enabled or disabled at run time.

[0063] Fig. 7A How to modify an application to include protection against out-of-bounds memory references according to an embodiment of the present invention is shown. There are far fewer instructions than other schemes, such as MPX, and the same code is used regardless of which BI table 26 is used. The changes also include "createBI p,p,@a+79,0" (406) to create a boundary information table 26. In addition, "load*" at 408 indicates the loading of a pointer.

[0064] Figure 7B It shows how an application can be modified using INTEL MPX to include protection against out of bounds memory references. As seen in the underline and bold lines of instruction 409, the number of instructions increases greatly if MPX is used instead of the present invention.

[0065] Figure 8 An example store instruction 412 of an embodiment of the present invention is shown. Note that the boundary protection operations (without the bold instruction 414) are designed to allow these operations to be enabled or disabled at run time.

[0066] Fig. 9 An alternative implementation of the mapping is shown.

[0067] System 100 may attach an additional N bits to each general register of general register file 16. The additional N bits may be used to register 2 N The boundary registers are indexed, where N is an integer (step 302).

[0068] FB(R i )=B j , j is attached to R i The value of the additional N bits.

[0069] The mapping is maintained as follows: At pointer initialization, a free B(BI) register is selected and the index of that B(BI) register is recorded in the N bits of the general register for pointer 304. For all other registers, the N bits should indicate the B(BI) register 306 to which those other registers are associated.

[0070] The propagation is performed using pointer arithmetic by selecting the non-zero value of the extra bit from the operand 308. One of the key issues becomes how to free or overflow the BI registers of the BI register file 18.

[0071] The system 100 releases the BI registers of the BI register file 18 with instructions inserted by the compiler as follows. For instructions to release registers, the system 100 uses the mapped register file and requires a release instruction to release the BI register from the BI register file 18. If a one-to-one mapping is used, no release instruction is required and the hardware can maintain the BI register file 18, the system 100 uses pointer analysis to identify the pointer set for each BI register: (B1:{R2,R4}) (step 310).

[0072] When it is determined (through data flow analysis) that the pointer register 60 becomes invalid 312 , the system 100 removes it from the register set 314 .

[0073] If it is determined that the register set is about to be empty 316, the system releases the corresponding BI register 18 (step 318). Another way is to identify which BI registers are still active by scanning all live pointers (at the beginning or end of the function) and release other BI registers at step 318.

[0074] When it is determined that there are not enough 320, the system 100 overflows the BI register 18. Assume that KS is the register set that should be kept (a minimum of two BI registers for the next instruction)

[0075] If for all Ry in KS, FB(Rx) != FB(Ry), then overflow Rx

[0076] Remember all Rz where FB(Rz)=FB(Rx) for recovery

[0077] The system then uses the method for register spilling in conjunction with the pointer analysis results to select which register to spill 322 .

[0078] Fig. 10A A method of an embodiment of the present invention is shown.

[0079] The system 100 stores boundary information (BI) in registers in the boundary register file 18 (step 502). The boundary information is mapped with the general register file 16. The boundary information includes a starting address and a length for each buffer.

[0080] Then, the system 100 generates the index table 28 in the memory 20 according to the boundary information from the boundary register file 18 (step 504). The index table 28 is accessed by index. Each entry of the index table 28 includes the starting address 40 and the length 42 of the buffer.

[0081] The system 100 also generates a value / key table 30 in the memory 20 according to the boundary information (step 506). The value / key table 30 is accessed using the pointer value 64 as the key 50. Each entry of the value / key table 30 includes a key 50 having a pointer value 62, a starting address 52 of the buffer, and a length 54. The boundary information for the pointer can be located from the original instruction.

[0082] The system 100 uses the index table 28 and the value / key table 30 to prevent out-of-bounds references (step 508). The processor or CPU core 10 includes a boundary processing unit 20 that performs operations for preventing out-of-bounds references.

[0083] Therefore, the present invention introduces a dedicated register file to save boundary information for valid pointers, which are in general registers. The present invention maintains a mapping from general registers of the general register file 16 to boundary registers of the boundary register file 18 so that boundary check related operations can be performed with the original instructions. The present invention greatly reduces the number of instructions to be added for boundary checking. Special hardware for performing boundary check related operations for instructions is also introduced. In addition, using the boundary information registers of the boundary information register file 18, when adding boundary check operations to most instructions, the waiting time of most instructions will not increase.

[0084] Therefore, the present invention can provide accurate protection, where the system 100 protects each buffer with down to byte precision. The present invention is applicable to conventional programs such as C / C++ applications that include arbitrary pointer arithmetic, and the number of buffers to be protected in one application can range from thousands to millions.

[0085] Fig. 10B A method of an embodiment of the present invention is shown.

[0086] Stated another way, the method for preventing out-of-bounds references includes the following. When a buffer is allocated, the system 100 stores the address of the buffer in a general register from the general register file 16 and stores boundary information (BI) for the buffer in a boundary information register from the boundary register file 18 (step 510). When the contents of the general register from the general register file 16 are used as an address in a load or store operation, the system 100 uses the contents of the boundary information register of the boundary register file 18 to determine whether the load or store is out of bounds (step 512).

[0087] exist Figure 1 to Figure 1 The different features shown in the different figures of FIG. 0 may be combined, changed or interchanged between the different examples. Figure 1 to Figure 1 The system 100 shown in FIG. 0 may also be Figures 11 to 15 The hardware and software shown are implemented.

[0088] Fig.11 Another hardware configuration of a system is shown in which there is an information processing / computer system 1100 according to the present invention, and preferably has at least one processor or central processing unit (CPU) 1110, which can implement the technology of the present invention in the form of a software program for software intelligence as a service.

[0089] The CPU 1110 is interconnected via a system bus 1112 to a random access memory (RAM) 1114, a read-only memory (ROM) 1116, an input / output (I / O) adapter 1118 (for connecting peripheral devices such as a disk unit 1121 and a tape drive 1140 to the bus 1112), a user interface adapter 1122 (for connecting a keyboard 1124, a mouse 1126, a speaker 1128, a microphone 1132 and / or other user interface devices to the bus 1112), a communications adapter 1134 for connecting the information processing system to a data processing network, the Internet, an intranet, a personal area network (PAN), etc., and a display adapter 1136 for connecting the bus 1112 to a display device 1138 and / or a printer 1139 (e.g., a digital printer, etc.).

[0090] In addition to the hardware / software environment described above, various aspects of the present invention include computer-implemented methods for performing the above methods. As an example, the method can be implemented in the specific environment discussed above.

[0091] For example, this method can be implemented by operating a computer implemented by digital data processing equipment to execute a sequence of machine-readable instructions. These instructions can reside in various types of signal-bearing media.

[0092] Thus, this aspect of the invention is directed to a programming product comprising a signal bearing storage medium tangibly embodying a program of machine readable instructions executable by a digital data processor in conjunction with the CPU 1110 and the hardware described above to perform the method of the present invention.

[0093] The signal bearing storage medium may include, for example, RAM contained within CPU 1110, such as represented by a fast access storage device.

[0094] Alternatively, the instructions may be contained in another signal-bearing storage medium 1200, such as flash memory 1210 or an optical storage disk 1220 ( Fig.12 ), which can be accessed directly or indirectly by CPU 1110.

[0095] Whether contained in flash memory 1210, optical disk 1220, computer / CPU 1110, or elsewhere, the instructions may be stored on a variety of machine-readable data storage media.

[0096] Therefore, the present invention may be a system, method and / or computer program product.The computer program product may include (one or more) computer-readable storage media having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform aspects of the present invention.

[0097] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, any suitable combination of electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or the aforementioned storage devices. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, such as a punch card or a convex structure in a groove with instructions recorded on it, and any suitable combination of the above devices. Computer readable storage medium as used herein should not be interpreted as a temporary signal itself, such as radio waves or other free propagating electromagnetic waves, electromagnetic waves propagated by waveguides or other transmission media (e.g., light pulses by optical fiber cables), or electrical signals transmitted by wires.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0099] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages, such as Smalltalk, C++, etc.) and process programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network (including local area network (LAN) or wide area network (WAN)), or can be connected to an external computer (for example, using an Internet service provider through the Internet). In certain embodiments, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, so as to perform various aspects of the present invention.

[0100] Various aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to embodiments of the present invention. It will be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0101] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0102] These computer-readable program instructions may also be stored in a computer-readable storage medium, which may direct a computer, a programmable data processing apparatus and / or other device to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0103] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps will be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0104] Flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in the flow chart or block diagram can represent the module, segment or part of instruction, which includes one or more executable instructions for realizing the specified logical function.In some alternative embodiments, the function noted in the frame may not occur in the order noted in the figure.For example, two frames shown continuously can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that the combination of the frames in each frame of the block diagram and / or flow chart illustration and the block diagram and / or flow chart illustration can be realized by a dedicated hardware-based system that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0105] Reference now Fig.13 , a schematic diagram 1400 of an example of a cloud computing node is shown. Cloud computing node 1400 is merely one example of a suitable cloud computing node and is not intended to impose any limitations on the scope of use or functionality of the embodiments of the present invention described herein. Regardless, cloud computing node 1400 can be implemented and / or perform any of the functions set forth above. As previously described, Figure 1 The system 100 can be used in a system such as Fig.13 (as well as Fig.14 and Fig.15) is implemented in a cloud infrastructure of the present invention. In the cloud computing node 1400, there is a computer system / server 1412, which can operate with many other general or special computing system environments or configurations. Examples of known computing systems, environments and / or configurations that may be suitable for use with the computer system / server 1412 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, etc.

[0106] Computer system / server 1412 may be described in the general context of computer system executable instructions, such as program modules, executed by the computer system. In general, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 1412 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in local and remote computer system storage media, including memory storage devices.

[0107] like Fig.13 As shown, the computer system / server 1412 in the cloud computing node 1400 is shown in the form of a general-purpose computing device. The components of the computer system / server 1412 may include, but are not limited to, one or more processors or processing units 1416, a system memory 1428, and a bus 1418 that couples various system components including the system memory 1428 to the processor 1416.

[0108] Bus 1418 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, these architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0109] Computer system / server 1412 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 1412, and it includes volatile and nonvolatile media, removable and non-removable media.

[0110] System memory 1428 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1430 and / or cache memory 1432. Computer system / server 1412 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1434 may be provided for reading from and writing to a non-removable non-volatile magnetic medium (not shown, commonly referred to as a "hard drive"). Although not shown, a disk drive for reading from and writing to a removable non-volatile disk (e.g., a "floppy disk") may be provided, as well as an optical drive for reading from or writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media. In such an example, each may be connected to bus 1418 via one or more data media interfaces. As will be further depicted and described below, memory 1428 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of an embodiment of the present invention.

[0111] By way of example and not limitation, a program / utility 1440 having a set (at least one) of program modules 1442, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 1428. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. Program modules 1442 generally perform the functions and / or methods of embodiments of the invention described herein.

[0112] The computer system / server 1412 may also communicate with one or more external devices 1414, such as a keyboard, a pointing device, a display 1424, etc.; one or more devices that enable a user to interact with the computer system / server 1412; and / or any device that enables the computer system / server 1412 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 1422. In addition, the computer system / server 1412 may communicate with one or more networks (such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet)) via a network adapter 1420. As shown, the network adapter 1420 communicates with other components of the computer system / server 1412 via a bus 1418. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with the computer system / server 1412. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0113] Reference now Fig.14 , depicts an illustrative cloud computing environment 1550. As shown, the cloud computing environment 1550 includes one or more cloud computing nodes 1400 with which a local computing device used by a cloud consumer can communicate, such as a personal digital assistant (PDA) or cellular phone 1554A, a desktop computer 1554B, a laptop computer 1554C, and / or an automobile computer system 1554N. The nodes 1400 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks (such as a private cloud, community cloud, public cloud, or hybrid cloud, or a combination thereof, as described above). This allows the cloud computing environment 1550 to provide infrastructure as a service, platform as a service, and / or software as a service without the cloud consumer having to maintain resources for them on a local computing device. It should be understood that Fig.14 The various types of computing devices 1554A-N shown in the figure are merely illustrative, and the computing node 1400 and cloud computing environment 1550 can communicate with any type of computing device over any type of network and / or network addressable connection (e.g., using a web browser).

[0114] Reference now Fig.15 , showing the cloud computing environment 1550 ( Fig.14 ) provides a set of functional abstraction layers. It should be understood in advance that Fig.15 The components, layers and functions shown are merely illustrative, and embodiments of the present invention are not limited thereto. As shown in the figure, the following layers and corresponding functions are provided:

[0115] The hardware and software layer 1600 includes hardware and software components. Examples of hardware components include: a mainframe, in one example, Systems; servers based on the RISC (Reduced Instruction Set Computer) architecture, in one example the IBM System; IBM System; IBM systems; storage devices; networks and network components. Examples of software components include: network application server software, in one example IBM Application server software; and database software, in one example IBM Database software. (IBM, zSeries, pSeries, xSeries, BladeCenter, WebSphere and DB2 are trademarks of International Business Machines Corporation, registered in many jurisdictions throughout the world).

[0116] Virtualization layer 1620 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and operating systems; and virtual clients.

[0117] In one example, the management layer 1630 may provide the functionality described below. Resource provisioning functionality provides dynamic acquisition of computing resources and other resources for performing tasks in a cloud computing environment. Metering and pricing functionality provides cost tracking of resources used within a cloud computing environment and provides bills or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security functionality provides identity authentication for cloud consumers and tasks and provides protection for data and other resources. User portal functionality provides access to the cloud computing environment for consumers and system administrators. Service level management functionality provides allocation and management of cloud computing resources to meet required service levels. Service level agreement (SLA) planning and fulfillment functionality provides pre-scheduling and procurement of cloud computing resources for which future demand is forecasted in accordance with the SLA.

[0118] Workload layer 1640 provides examples of functions that can utilize cloud computing environments. In this layer, examples of workloads and functions that can be provided include: mapping and navigation; software development and lifecycle management; virtual classroom teaching provision; data analysis processing; transaction processing; and more specifically, with respect to the present invention, APIs and runtime system components that generate search auto-completion suggestions based on contextual input.

[0119] From the detailed description, many features and advantages of the present invention are apparent, therefore, the appended claims are intended to cover all such features and advantages of the present invention that fall within the true spirit and scope of the present invention. Further, since many modifications and variations will be readily apparent to those skilled in the art, it is not desirable to limit the present invention to the exact construction and operation illustrated and described, and therefore, all suitable modifications and equivalents that fall within the scope of the present invention may be adopted.

[0120] It should be understood that the present invention is not limited in its application to the construction details and component arrangements set forth in the following description or shown in the accompanying drawings. The present invention can have embodiments other than those described, and can be practiced and executed in various ways. Moreover, it should be understood that the words and terms used herein and the abstract are for descriptive purposes and should not be considered as limiting.

[0121] Therefore, those skilled in the art will appreciate that the concepts upon which the present disclosure is based can be readily used as a basis for designing other structures, methods and systems for carrying out the several purposes of the present invention. It is therefore important that the claims be regarded as including such equivalent constructions as long as they do not depart from the spirit and scope of the present invention.

Claims

1. A method for preventing out-of-bounds references, comprising: storing boundary information in the boundary information register in the boundary information register file; Generate an index table in a memory according to the boundary information; generating a value and key table in the memory according to the boundary information; The address of the buffer is stored in a general register, and the boundary information BI for the buffer is stored in a boundary information register; When the contents of the general register are used as an address in a load or store operation, using the contents of the boundary information register to determine whether the load or store operation is out of bounds; and The out-of-bounds reference is prevented using the index table and the value and key table.

2. The method according to claim 1, comprising: When a first address in the general register is used in array indexing or pointer arithmetic to calculate a second address, the boundary information for the first address is used as boundary information for the second address.

3. The method according to claim 1, wherein: Which of the index table or the value and key table is accessed is based on a heuristic, Wherein, the index table is accessed through an index, Each entry in the index table includes the starting address and length of the buffer. The boundary information is mapped to the general register.

4. The method according to claim 1, wherein: accessing the value and key table using the pointer value as the key, and Each entry of the value and key table includes a key of a pointer value, a starting address and a length of a buffer.

5. The method according to claim 1, wherein: The boundary information includes the starting address and length of each buffer. Among them, locating the boundary information for the pointer from the original instruction, and The processor includes a boundary processing unit that performs operations for preventing out-of-bounds references.

6. The method according to claim 1, comprising: When the address in the general register is assigned to the second general register, the boundary information for the first register is used as the boundary information for the second register.

7. A system for preventing out-of-bounds references, comprising: memory, which stores computer instructions; as well as A processor configured to execute the computer instructions to implement the method according to any one of claims 1-6.

8. A computer program product for preventing out-of-bounds references, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being readable and executable by a computer to enable the computer to perform the method of any one of claims 1-6.

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