An evaluation method and system for the lifespan of integrated circuit chips based on machine learning

Abstract

An evaluation method and system for the lifespan of integrated circuit chips based on machine learning. The method includes the steps of: recording the true dataset of integrated circuit chips according to the lifespan test and establishing a lifespan distribution function; obtaining the corresponding simulated lifespan values using the lifespan distribution function to obtain a simulated dataset; merging the true dataset and the simulated dataset to form the original dataset for training and optimizing the machine learning regression model; for the parametric data in the original dataset, obtaining parametric feature vectors through feature extraction; converting the two-dimensional structure connection graph into a feature vector to form the structural feature vector of the chip; merging the parametric feature vectors and the structural feature vectors to form a full feature vector set and inputting it into the machine learning regression model for model fusion to obtain a fused regression model; using the training set and the test set to finally form an end-to-end chip lifespan prediction model. The method of the present invention can achieve real-time and accurate prediction and evaluation of the lifespan of integrated circuit chips.

Description

Technical Field

[0001] The present invention relates to a method and system for evaluating the life of an integrated circuit chip, and belongs to the technical field of semiconductor failure analysis. Background Art

[0002] Electronic devices are increasingly widely used in the military and aerospace fields, and their reliability requirements are also constantly improving. With the improvement of the design technology and manufacturing level of integrated circuits, the integration degree of large electronic devices is getting higher and higher, and the functions are getting more and more complex. With the rapid development of electronic chip technology, the process feature size of CMOS devices is becoming more and more miniaturized and integrated, and the problems of interconnect structure failure and thermal stress have become the most challenging problems in nano-integrated circuit design. The increase in integration density and power consumption leads to higher chip temperatures, chip temperature gradients and more complex interconnect structure failures, which in turn affect their reliability. Therefore, it is necessary to evaluate the life of integrated circuit chips.

[0003] Traditional life evaluation test methods generally take stresses such as temperature, humidity or temperature cycle as acceleration conditions. Through accelerated life tests, device parameters are measured regularly, and the device failure time is roughly obtained based on the stage measurement data. Then, data statistical analysis is carried out, and the empirical acceleration factor is deduced through the life distribution model under different gradient test conditions, and then the accelerated life under normal conditions is estimated; or accelerated degradation experiments are adopted, the shear strength of the interconnect structure is detected regularly, the pseudo-life of the interconnect structure is calculated, and then the life of the package under normal use environment is deduced by combining the failure mechanism acceleration model. Using such methods to evaluate the life of integrated circuit chips has the problems of large estimation error and low estimation efficiency.

[0004] 1) Large estimation error: Regularly detecting the sensitive parameters of the package to obtain the parameter degradation trend, and simulating and fitting the final failure time according to the parameter trend. This is not the real failure time of the chip interconnect structure. Its life estimation result is directly related to the rough parameter trend fitting method, so the estimation error is large; The average life is deduced from the simulation life distribution model, which does not meet the requirements of high-reliability inspection. The normal life calculated based on this average life has insufficient credibility; Using the characteristic life obtained from the simulation life distribution to deduce the acceleration factor does not consider the key influence of the failure mechanism. Only through the traditional data statistical analysis reliability prediction method is not scientific; Or directly using the failure mechanism acceleration model substituting rough estimated parameters to calculate the life of the interconnect structure under normal use conditions has insufficient applicability and accuracy;

[0005] 2) Low evaluation efficiency: In the process of simulating the chip life, relevant experimental data need to be obtained through the life test of a limited number of samples of chips, forming a limited number of life distributions. According to the roughly estimated life, substitute it into complex failure mechanism acceleration models such as the electromigration model, the cracking model, and the thermal / vibration fatigue model to calculate the life of the interconnect structure under normal use conditions. The simulation process consumes a large amount of manpower, material resources and time, and it is difficult to solve the complex failure physics model group.

[0006] Therefore, such methods cannot accurately and efficiently evaluate the life of the interconnect structure of integrated circuit chips. Summary of the Invention

[0007] The technical problem to be solved by the present invention is: to overcome the problems of large monitoring data errors, unreasonable average life reliability, and insufficient applicability of the acceleration model existing in the traditional accelerated life test or accelerated degradation experiment when evaluating the package interconnect structure. The present invention proposes a chip life evaluation method and system based on the multi-material stacked chip structure modeling machine learning technology, which can more accurately and specifically evaluate the life of integrated circuit chips.

[0008] The technical solution adopted by the present invention is: an evaluation method for the life of an integrated circuit chip based on machine learning, including:

[0009] Step 1: Record the true data set {c i , y′ i} of the integrated circuit chip according to the life test and establish a life distribution function; where y i ′ is the true life value of the integrated circuit chip corresponding to the relevant parameters of the integrated circuit chip;

[0010] Step 2: According to the use environment conditions of the integrated circuit chip, within the parameter range of the relevant parameters corresponding to the use environment conditions, randomly generate n groups of parameter groups to simulate various possible actual use environment situations, and use the life distribution function to obtain the corresponding simulation life values. The simulation data set is expressed as {c i , y i}, i = 1,..., n; n is a positive integer; where c i is the relevant parameter of the integrated circuit chip, and y i is the corresponding simulation life value of the integrated circuit chip;

[0011] Combine the true data set and the simulation data set to form the original data set for training and optimizing the machine learning regression model;

[0012] Step 3: For the parametric data in the original data set, obtain the parametric feature vectors through feature extraction;

[0013] For the physical structure of the multi-layer longitudinal section of the chip, a two-dimensional structure connection diagram of the three-dimensional chip structure is formed by using a multi-material laminated structure modeling method; the Weissfeiler-Lehman iterative algorithm is used to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip;

[0014] Step 4: Combine the parametric feature vector and the structural feature vector to form a full feature vector set and input it into the machine learning regression model for model fusion to obtain a fused regression model;

[0015] Step 5: Use a% of the original data set as the training set, and the remaining 100% - a% as the test set. Substitute the data used as the training set into the fused regression model to obtain predicted values. Use multiple loss functions to optimize the accuracy of the fused regression model to obtain an optimized fused regression model; use the test set and substitute it into the optimized fused regression model to detect the accuracy, and finally form an end-to-end chip life prediction model, where a is a set value.

[0016] The multi-material laminated structure modeling method models the chip structure with multi-element lamination to form a node connection diagram. The specific modeling method is as follows:

[0017] Abstract and simplify different layer and different element regions into one node, and abstract the adjacent relationship of different element regions into an undirected edge, so that the nodes representing different elements are connected to each other, and the three-dimensional chip structure is modeled into a two-dimensional structure connection diagram model. The specific steps are as follows:

[0018] a. Number all the elements in the physical structure of the multi-layer longitudinal section of the chip in sequence;

[0019] b. Identify the connected regions of the same elements in each layer of the physical structure of the multi-layer longitudinal section of the chip, abstract them into a node in the connection diagram, and mark this node with the label corresponding to its element; if two connected regions of the same element are in contact, add an undirected edge between the corresponding two nodes in the connection diagram.

[0020] The specific steps of using the Weissfeiler-Lehman iterative algorithm to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip are as follows:

[0021] S3.1: Obtain the adjacent nodes of each node in the two-dimensional structure connection diagram; obtain the labels of the adjacent node elements of each node, and put the labels into an unordered list Li; put the element of this node into the infinite list Li;

[0022] S3.2: For each node, encode according to the unordered list Li obtained in S3.1;

[0023] S3.3. Count the number of each code in the two-dimensional structure connection diagram, and form a structure feature vector after arranging the codes in order.

[0024] The machine learning regression model is as follows:

[0025]

[0026] Among them, y is the lifespan of the integrated circuit chip, is the full feature vector obtained after feature extraction.

[0027] In the fourth step, the full feature set is sent into a fusion regression model composed of K machine learning algorithms. Through repeated sampling with replacement K times, K sub-models are trained. Each time, 1 model is randomly sampled and trained, and the results of the K models are fused by Voting / Averaging; K is a positive integer. When K = 1, only one model is used, and the Voting / Averaging method remains unchanged.

[0028] An evaluation system according to the above-mentioned machine learning-based integrated circuit chip lifespan evaluation method, including a data acquisition module, a data storage module, an algorithm application module, and a display module:

[0029] The data acquisition module records the true data set {c i , y' i} of the integrated circuit chip according to the lifespan test and establishes a lifespan distribution function;

[0030] According to the operating conditions of the integrated circuit chip's usage environment, within the parameter range of the relevant parameters corresponding to the usage environment conditions, n groups of parameter sets are randomly generated to simulate various possible usage environment situations in reality. The corresponding simulation lifespan values are obtained using the lifespan distribution function, and the simulation data set is expressed as {c i , y i}, i = 1,..., n; n is a positive integer;

[0031] Merge the true data set and the simulation data set to form the original data set for training and optimizing the machine learning regression model, and send it to the data storage module for storage;

[0032] Among them, y i ' is the true lifespan value of the integrated circuit chip corresponding to the relevant parameters of the integrated circuit chip; c i is the relevant parameter of the integrated circuit chip, and y i is the corresponding simulation lifespan value of the integrated circuit chip;

[0033] The algorithm application module reads the original data set stored in the data storage module, and obtains a parameter-type feature vector by feature extraction of the parameter-type data in the original data set;

[0034] For the physical structure of the multi-layer longitudinal section of the chip, a two-dimensional structure connection diagram of the three-dimensional chip structure is formed by using a multi-material laminated structure modeling method; the two-dimensional structure connection diagram is converted into a feature vector by using the Weissfeiler-Lehman iterative algorithm to form the structural feature vector of the chip;

[0035] The parametric feature vector and the structural feature vector are combined to form a full feature vector set and input into the machine learning regression model for model fusion to obtain a fusion regression model;

[0036] Take a% of the original data set as the training set, and the remaining 100%-a% as the test set. Substitute the data used as the training set into the fusion regression model to obtain predicted values, and use multiple loss functions to optimize the accuracy of the fusion regression model to obtain an optimized fusion regression model; use the test set, substitute it into the optimized fusion regression model, and detect the accuracy, and finally form an end-to-end chip life prediction model;

[0037] The display module is used to display the data sent by the algorithm application module, including the accuracy of the chip life prediction model and the chip life prediction value.

[0038] The advantages of the present invention compared with the prior art are as follows:

[0039] (1) Accurate estimation of the life of integrated circuit chips, specifically manifested in: the input data of the machine learning algorithm is a full data set combining experimental data and simulation data. On the one hand, it solves the problem of insufficient samples in the real data set, and on the other hand, it overcomes the problem of inaccurate life estimation caused by the above-mentioned rough estimation of life distribution and fitting of failure physics model parameters. Greatly reduce the accuracy requirements for traditional statistical analysis and model estimation, generate simulation data, use real data to correct the machine learning model, and increase the accuracy and robustness of the model; based on a multi-material laminated structure modeling method, integrating the Weissfeiler-Lehman iterative algorithm, accurately input the information of the chip structure as features into the machine learning model, greatly improving the model prediction accuracy.

[0040] (2) The present invention can estimate the life of integrated circuit chips with ultra-high efficiency: The present invention integrates a data acquisition module, a data storage module, an algorithm application module, and a display module, and finally forms an integrated circuit chip life prediction system, completing a direct life prediction path from the parameter input end to the life output end, which not only solves the high cost problem caused by traditional experimental methods to obtain accurate results, but also completely replaces traditional simulation methods, breaking through the limitations of time-consuming and laborious repeated simulations of simulations, and improving the prediction speed to the second level, greatly improving the efficiency of integrated circuit chip life prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the chip hierarchical structure;

[0042] Figure 2 Schematic diagram for modeling the chip structure;

[0043] Figure 3 Flow chart of the machine learning algorithm;

[0044] Figure 4 Flow chart of the method of the present invention. Detailed implementation manners

[0045] The following specifically describes the implementation manners in conjunction with the accompanying drawings.

[0046] As Figure 4 shown, a method for evaluating the life of an integrated circuit chip based on machine learning includes the following steps:

[0047] I. Data collection

[0048] The data source consists of two parts: the real data set recorded in the life test, and the simulation data generated according to the life distribution function established from the real data;

[0049] The simulated life values are randomly generated in the fluctuation range of relevant parameters by the life distribution function for n groups (for example, n = 5000). Each group of data contains the relevant parameter data of the chip, denoted as c i , and the corresponding chip life is denoted as y i . The simulation data set is denoted as {c i , y i}, i = 1,..., n. At the same time, the test real data set is represented in the same way, and the real and simulation data sets are combined to form the original data set for training and optimizing the machine learning regression model.

[0050] II. Feature extraction

[0051] Feature extraction is the process of extracting a set of features related to the chip life from each chip data c i . This set of features is usually collected in a vector, called the feature vector, denoted as In the present invention, the features are roughly divided into two categories: parametric and structural. The following details these two categories of features.

[0052] 1. Parametric

[0053] This type of feature is often some parameters describing the chip characteristics. Including but not limited to:

[0054] Epoxy glue coverage width, bump arrangement pattern, number of bumps, relative fatigue coefficient of gold wire, device thermal expansion coefficient ( / K), relative fatigue coefficient of gold wire, substrate thermal expansion coefficient ( / K), etc.

[0055] 2. Structural

[0056] Such features are used to represent the features of the chip structure. The method for extracting structural features is introduced in detail below.

[0057] First, as Figure 1 shown, the chip generally has a hierarchical structure, and different regions of each layer contain different elements.

[0058] Model this structure as follows to convert the chip structure into a graph:

[0059] (1) Treat the regions with the same elements in each layer as a node in the graph, and label this node with the element.

[0060] (2) If each element region is in contact with other element regions, establish an edge between the corresponding nodes.

[0061] In this way, for each chip, we can obtain a graph to reflect the structural features of the chip.

[0062] Figure 2 What is shown is Figure 1 the graph obtained from the chip structure according to our method.

[0063] III. Structural Feature Transformation

[0064] Use the Weisfeiler-Lehman iterative algorithm to convert a graph into a feature vector.

[0065] Take Figure 2 as an example. We perform the following processing, and the intermediate results are placed in Table 1

[0066] (1) For each node, list its own node element label. As shown in the second column of Table 1.

[0067] (2) For each node, list the element labels of all adjacent nodes. As shown in the third column of Table 1.

[0068] (3) Encode according to the combination of the second column and the third column. For each row in the third column, if there are multiple elements, the order does not matter.

[0069] (4) For each structure graph, count the number of each encoding in the fourth column of Table 1. For example, if counted in the order of (H1, H2, H3, H4, H5). Figure 2 The graph in can be represented as (1, 4, 5, 3, 1, 1). This vector is the obtained structural feature vector.

[0070] Table 1 Intermediate Results of the Weisfeiler-Lehman Iterative Algorithm

[0071]

[0072]

[0073] Finally, connecting the parametric features and the structural features together can be used as the finally obtained features

[0074] IV. Process of Machine Learning Algorithm

[0075] As Figure 3 shown, the machine learning algorithm of the present invention consists of two parts: training and prediction.

[0076] The training process is a process of obtaining a regression model by extracting features from historical data. For the training data, assume that n groups of data are collected, and these data can come from experiments or simulations. Each group of data contains the relevant data c of the chip and the corresponding chip life y. For simplicity, the training data set can be represented as {c i , y i}, i = 1,..., n; n is a positive integer;

[0077] The prediction process is for the new chip-related data c new . After passing through the same feature extraction method as the training process, the obtained features are input into the regression model obtained in the training process, so as to obtain the prediction of the life.

[0078] V. Regression Model

[0079] The regression model is to model the model. In the present invention, y refers to the life of the chip, and is the feature vector obtained after feature extraction.

[0080] In the present invention, any regression model can be used. Including but not limited to: linear regression, Bayesian regression, decision tree, random forest, gradient boosting tree, neural network. By sampling with replacement K times, K sub-models are trained (each time a random sample is used to train 1 model), and the results of the K models are fused by Voting / Averaging. K is a positive integer. When K = 1, only one model is used, and the Voting / Averaging method remains unchanged.

[0081] The regression model training algorithm uses the training data set to obtain a model that can more accurately predict new data. Usually, a loss function based on the training data is first defined, and then a numerical optimization algorithm is used to find a set of model parameters to minimize the loss function. For a model, multiple loss functions can be defined according to needs, and multiple numerical optimization algorithms can be used according to needs.

[0082] For example, for a linear regression model, model training aims to make the result Xθ of the weighted combination of feature vectors closest to the true chip lifespan y. Specifically, it can be reduced to the following unconstrained optimization problem:

[0083] For all θ, find (Xθ - y) 2 the minimum value;

[0084] where, is the feature vector obtained after feature extraction, y refers to the chip lifespan, θ is the weight ratio of the feature vector, and i = 1, 2, 3, …, n; n is a positive integer.

[0085] Or it can be transformed into an optimization problem with a penalty term ρθ 2 where ρ is the penalty term weight:

[0086] Minimize (Xθ - y) 2 + ρθ 2 .

[0087] Numerical optimization algorithms that can be used include but are not limited to: gradient descent, stochastic gradient descent, etc.

[0088] VI. System Architecture

[0089] An evaluation system for the lifespan of integrated circuit chips based on machine learning, including a data acquisition module, a data storage module, an algorithm application module, and a display module:

[0090] The data acquisition module records the true dataset {c i , y′ i} of the integrated circuit chips according to the lifespan test and establishes a lifespan distribution function; within the parameter range of the relevant parameters corresponding to the usage environment conditions of the integrated circuit chips, randomly generate n groups of parameter sets to simulate various possible usage environment situations in reality, and use the lifespan distribution function to obtain the corresponding simulation lifespan values, representing the simulation dataset as {c i , y i}, where i = 1, …, n; n is a positive integer; merge the true dataset and the simulation dataset to form the original dataset for training and optimizing the machine learning regression model, and send it to the data storage module for storage;

[0091] where, y i ′ is the true lifespan value of the integrated circuit chip corresponding to the relevant parameters of the integrated circuit chip; c i is the relevant parameter of the integrated circuit chip, and y i is the corresponding simulation lifespan value of the integrated circuit chip;

[0092] The algorithm application module is used to read the original dataset stored in the data storage module, and obtain parametric feature vectors by feature extraction from the parametric data in the original dataset;

[0093] For the physical structure of the multi-layer longitudinal section of the chip, a multi-material stacked structure modeling method is used to form a two-dimensional structure connection diagram of the three-dimensional chip structure; the Weissfeiler-Lehman iterative algorithm is used to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip;

[0094] Merge the parametric feature vector and the structural feature vector to form a full feature vector set and input it into the machine learning regression model for model fusion to obtain a fusion regression model;

[0095] Take a% of the original dataset as the training set, and the remaining 100% - a% as the test set. Substitute the data used as the training set into the fusion regression model to obtain predicted values, and use multiple loss functions to optimize the accuracy of the fusion regression model to obtain an optimized fusion regression model; use the test set, substitute it into the optimized fusion regression model to detect the accuracy, and finally form an end-to-end chip life prediction model;

[0096] The display module is used to display the data sent by the algorithm application module, including the accuracy of the chip life prediction model and the chip life prediction value.

[0097] The method of using the multi-material stacked structure modeling method to model the chip structure with multi-element stacking to form a node connection diagram includes:

[0098] Abstract and simplify different-layer and different-element regions into one node, and abstract the adjacent relationship of different-element regions into an undirected edge, so that the nodes representing different elements are connected to each other, and the three-dimensional chip structure is modeled into a two-dimensional structure connection diagram model, including:

[0099] Number all the elements in the physical structure of the multi-layer longitudinal section of the chip in sequence;

[0100] Identify the connected regions of the same elements in each layer of the physical structure of the multi-layer longitudinal section of the chip, abstract them into a node in the connection diagram, and mark this node with the label corresponding to its element; if two connected regions of the same element are in contact, add an undirected edge between the corresponding two nodes in the connection diagram.

[0101] The method of using the Weissfeiler-Lehman iterative algorithm to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip includes:

[0102] S3.1. Obtain the adjacent nodes of each node in the two-dimensional structure connection diagram; obtain the labels of the adjacent node elements of each node, and put the labels into an unordered list Li; put the element of this node into the infinite list Li;

[0103] S3.2. For each node, encode according to the unordered list Li obtained in S3.1;

[0104] S3.3. Count the quantity of each code in the two-dimensional structure connection diagram, and form a structural feature vector after arranging the codes in order.

[0105] The machine learning regression model is as follows:

[0106]

[0107] Among them, y is the lifespan of the integrated circuit chip, is the full feature vector obtained after feature extraction.

[0108] The combined parametric feature vector and the structural feature vector form a full feature vector set, which is input into the machine learning regression model for model fusion to obtain a fusion regression model, including:

[0109] Send the full feature set into a fusion regression model composed of K machine learning algorithms. Through repeated sampling with replacement K times, train K sub-models. Each time, randomly sample and train 1 model, and perform Voting / Averaging fusion on the results of the K models; K is a positive integer. When K = 1, only one model is used, and the Voting / Averaging method remains unchanged.

[0110] The parts not detailed in the present invention belong to the well-known technologies in the art.

Claims

1. An evaluation method for the lifespan of an integrated circuit chip based on machine learning, characterized in that, Including: According to the true data set {c i , y′ i} of integrated circuit chips recorded in the life test, establish a life distribution function; where c i is the relevant parameter of the integrated circuit chip, and y i ′ is the true life value of the integrated circuit chip corresponding to the relevant parameter of the integrated circuit chip; According to the operating conditions of the integrated circuit chip, within the parameter range of the relevant parameters corresponding to the operating conditions, n groups of parameter sets are randomly generated to simulate various possible actual operating conditions. The corresponding simulation life values are obtained using the life distribution function, and the simulation data set is expressed as {c i , y i}, i = 1, …, n; n is a positive integer; where c i is the relevant parameter of the integrated circuit chip, and y i is the corresponding simulation life value of the integrated circuit chip; Combining the real dataset and the simulation dataset to form the original dataset for training and optimizing the machine learning regression model; For the parametric data in the original dataset, obtaining the parametric feature vectors through feature extraction; For the physical structure of the multi-layer longitudinal section of the chip, adopting the multi-material laminated structure modeling method to form the two-dimensional structure connection diagram of the three-dimensional chip structure; using the Weisfeiler-Lehman iterative algorithm to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip; Combining the parametric feature vectors and the structural feature vectors to form a full feature vector set, inputting it into the machine learning regression model for model fusion to obtain the fusion regression model; Taking a% of the original dataset as the training set and the remaining 100% - a% as the test set, bringing the data used as the training set into the fusion regression model to obtain the predicted values, using multiple loss functions to optimize the accuracy of the fusion regression model to obtain the optimized fusion regression model; using the test set, bringing it into the optimized fusion regression model to detect the accuracy, and finally forming an end-to-end chip life prediction model, where a is a set value; The adopting of the multi-material laminated structure modeling method to form the two-dimensional structure connection diagram of the three-dimensional chip structure includes: Abstracting and simplifying different layer and different element regions into a node, abstracting the adjacent relationship of different element regions into an undirected edge, so that the nodes representing different elements are connected to model the three-dimensional chip structure as a two-dimensional structure connection diagram model, including: Numbering all the elements in the physical structure of the multi-layer longitudinal section of the chip in sequence; Identifying the connected regions of the same elements in each layer of the physical structure of the multi-layer longitudinal section of the chip, abstracting them into a node in the connection diagram, and marking this node with the label corresponding to its element; if two connected regions of the same element are in contact, adding an undirected edge between the corresponding two nodes in the connection diagram; The using of the Weisfeiler-Lehman iterative algorithm to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip includes: S3.1: Obtaining the adjacent nodes of each node in the two-dimensional structure connection diagram; obtaining the labels of the adjacent node elements of each node, and putting the labels into an unordered list Li; putting the element of this node into the unordered list Li; S3.2: For each node, encoding according to the unordered list Li obtained in S3.1; S3.3: Counting the number of each encoding in the two-dimensional structure connection diagram, and forming the structural feature vector after arranging the encodings in order.

2. The evaluation method for the lifespan of an integrated circuit chip based on machine learning according to claim 1, characterized in that, The machine learning regression model is as follows: where y is the lifetime of the integrated circuit chip, is the full feature vector obtained after feature extraction.

3. The evaluation method for the lifespan of an integrated circuit chip based on machine learning according to claim 1, characterized in that, The combining of the parametric feature vectors and the structural feature vectors to form a full feature vector set, inputting it into the machine learning regression model for model fusion to obtain the fusion regression model includes: Sending the full feature set into the fusion regression model composed of K machine learning algorithms, training K sub-models through sampling with replacement K times, randomly sampling and training 1 model each time, and performing Voting / Averaging fusion on the results of the K models; K is a positive integer, when K = 1, only one model is used and the Voting / Averaging method remains unchanged.

4. An evaluation system for the lifespan of an integrated circuit chip based on machine learning, characterized in that, It includes a data acquisition module, a data storage module, an algorithm application module, and a display module: Data acquisition module, according to the life test records the true data set {c i , y′ i} of the integrated circuit chip and establishes a life distribution function; According to the operating conditions of the integrated circuit chip, within the parameter range of the relevant parameters corresponding to the operating conditions, n groups of parameter sets are randomly generated to simulate various actual possible usage environment situations. The corresponding simulation life values are obtained using the life distribution function, and the simulation data set is expressed as {c i , y i}, i = 1, …, n; n is a positive integer; Merge the real dataset and the simulation dataset to form the original dataset for training and optimizing the machine learning regression model, and send it to the data storage module for storage; where y i ′ is the true life value of the integrated circuit chip corresponding to the relevant parameters of the integrated circuit chip; c i is the relevant parameter of the integrated circuit chip, and y i is the simulated life value of the corresponding integrated circuit chip; The algorithm application module reads the original dataset stored in the data storage module, and obtains parametric feature vectors by feature extraction of the parametric data in the original dataset; For the physical structure of the multi-layer longitudinal section of the chip, a multi-material laminated structure modeling method is used to form a two-dimensional structure connection diagram of the three-dimensional chip structure; the Weissfeiler-Lehman iterative algorithm is used to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip; Merge the parametric feature vector and the structural feature vector to form a full feature vector set, input it into the machine learning regression model for model fusion, and obtain a fusion regression model; Take a% of the original dataset as the training set, and the remaining 100% - a% as the test set. Substitute the data used as the training set into the fusion regression model to obtain predicted values. Use multiple loss functions to optimize the accuracy of the fusion regression model to obtain an optimized fusion regression model; use the test set, substitute it into the optimized fusion regression model to detect the accuracy, and finally form an end-to-end chip life prediction model; The display module is used to display the data sent by the algorithm application module, including the accuracy of the chip life prediction model and the chip life prediction value; The method of using the multi-material laminated structure modeling method to form a two-dimensional structure connection diagram of the three-dimensional chip structure includes: Abstract and simplify different layer and different element regions into a node, abstract the adjacent relationship of different element regions into an undirected edge, so that the nodes representing different elements are connected to each other, and model the three-dimensional chip structure as a two-dimensional structure connection diagram model, including: Number all the elements in the physical structure of the multi-layer longitudinal section of the chip in sequence; Identify the connected regions of the same elements in each layer of the physical structure of the multi-layer longitudinal section of the chip, abstract them into a node in the connection diagram, and mark this node with the label corresponding to its element; if two connected regions of the same element are in contact, add an undirected edge between the corresponding two nodes in the connection diagram; The method of using the Weissfeiler-Lehman iterative algorithm to convert the two-dimensional structure connection diagram into a feature vector to form the structural feature vector of the chip includes: S3.1: Obtain the adjacent nodes of each node in the two-dimensional structure connection diagram; obtain the labels of the adjacent node elements of each node, and put the labels into an unordered list Li; put the element of this node into the unordered list Li; S3.2: For each node, encode according to the unordered list Li obtained in S3.1; S3.3: Count the number of each encoding in the two-dimensional structure connection diagram, and form a structural feature vector after arranging the encodings in order.

5. The evaluation system for the lifespan of an integrated circuit chip based on machine learning according to claim 4, wherein, The machine learning regression model is as follows: where y is the lifetime of the integrated circuit chip, is the full feature vector obtained after feature extraction.

6. The evaluation system for the lifespan of an integrated circuit chip based on machine learning according to claim 4, wherein, The method of merging the parametric feature vector and the structural feature vector to form a full feature vector set, inputting it into the machine learning regression model for model fusion, and obtaining a fusion regression model includes: The full feature set is fed into a fusion regression model composed of K machine learning algorithms. Through sampling with replacement repeated K times, K sub-models are trained. Each time, one model is randomly sampled and trained, and the results of the K models are fused using Voting / Averaging; K is a positive integer. When K = 1, only one model is used, and the Voting / Averaging method remains unchanged.

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