A three-dimensional chip layout method, device and terminal equipment

Abstract

This application is applicable to the field of computer technology and provides a three-dimensional chip layout method, apparatus, and terminal device. The method comprises: obtaining at least one initial layout result for multiple chips to be laid out; inputting at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, wherein the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set; and selecting a final layout result from the at least one initial layout result based on the power consumption prediction value corresponding to each initial layout result. The three-dimensional chip layout method provided in this application takes into account the impact of power consumption on the three-dimensional chip layout, thereby not only improving the layout accuracy of the three-dimensional chip but also reducing the power consumption of the three-dimensional chip, thereby extending the service life of the three-dimensional chip.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular relates to a layout method, apparatus, terminal device, and computer-readable storage medium for a three-dimensional chip. Background Art

[0002] In recent years, with the widespread adoption of 3D packaging technology, chip integration and complexity have continued to increase. The number of components integrated on a single chip has continued to grow, and their density has continued to increase. This has also led to increasing heat generation, making chip layout increasingly difficult. Compared to conventional 2D integrated chips, 3D stacked chips of the same area can integrate more chips, significantly increasing power per unit volume and potentially causing overheating and even failure of the stacked chips. Therefore, how to layout 3D chips has become a key issue in integrated circuit electronic design automation.

[0003] However, existing technologies usually simply determine the overall layout of a three-dimensional chip based on an optimal algorithm (such as a particle swarm algorithm or a genetic algorithm), which has problems such as low layout accuracy and increased power consumption of the three-dimensional chip. Summary of the Invention

[0004] The embodiments of the present application provide a three-dimensional chip layout method, apparatus, terminal device, and computer-readable storage medium, which can solve the problems of low layout accuracy and increased power consumption of three-dimensional chips in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a layout method for a three-dimensional chip, comprising:

[0006] Obtaining at least one initial layout result of a plurality of chips to be laid out;

[0007] Inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, wherein the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set;

[0008] A final layout result is selected from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result.

[0009] Optionally, obtaining at least one initial layout result of the plurality of chips to be laid out includes:

[0010] Using the plurality of chips to be laid out as particles in a particle swarm algorithm, and performing an initialization operation on the position and velocity of each particle;

[0011] Determining the optimal position of each particle according to the position and velocity obtained after each particle performs the initialization operation;

[0012] performing an update operation on the position and velocity of each of the particles;

[0013] performing a crossover and mutation operation on each particle using a genetic algorithm according to the updated position and velocity of each particle, and performing an update operation on the optimal position of each particle according to the results of the crossover and mutation operation;

[0014] If the number of times the update operation is performed on the optimal position of each particle is less than the set iteration value, returning to the step of performing the update operation on the position and velocity of each particle, until the number of times the update operation is performed on the optimal position of each particle reaches the iteration value, thereby obtaining the final optimal position of each particle;

[0015] The final optimal position of each particle is determined as the initial layout result.

[0016] Optionally, the target particle is any one of the particles, and updating the optimal position of each particle according to the results of the crossover and mutation operations includes:

[0017] If the fitness value corresponding to the optimal position of the target particle before performing the crossover and mutation operations is greater than the fitness value corresponding to the optimal position of the target particle after performing the crossover and mutation operations, the optimal position of the target particle after performing the crossover and mutation operations is determined as the updated optimal position of the target particle; wherein the fitness value corresponding to the optimal position of each of the particles is used to characterize the temperature of the multiple chips to be laid out.

[0018] Optionally, performing crossover and mutation operations on each particle using a genetic algorithm according to the updated position and velocity of each particle includes:

[0019] Performing a crossover operation on the updated position of the target particle and the optimal position of the target particle according to a preset crossover operator to obtain a first position of the target particle;

[0020] Performing a mutation operation on the updated position of the target particle according to a preset mutation operator to obtain a second position of the target particle;

[0021] respectively calculating a first fitness value corresponding to the first position and a second fitness value corresponding to the second position;

[0022] The smaller value between the first fitness value and the second fitness value is determined as the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed.

[0023] Optionally, before inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, the method further includes:

[0024] Decomposing the at least one initial layout result according to an empirical mode decomposition algorithm to obtain a margin and a plurality of intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result;

[0025] The target layout result is any one of the at least one initial layout result, and the step of inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result includes:

[0026] Inputting a plurality of intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result;

[0027] The power consumption prediction value corresponding to the target layout result is calculated according to the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

[0028] Optionally, the power consumption prediction model includes a first power consumption prediction sub-model and a second power consumption prediction sub-model; after decomposing the at least one initial layout result according to an empirical mode decomposition algorithm to obtain a margin and multiple intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result, the model further includes:

[0029] dividing the plurality of eigenmode function components corresponding to the target layout result into a first frequency eigenmode function component and a second frequency eigenmode function component, wherein the frequency corresponding to the first frequency eigenmode function component is higher than the frequency corresponding to the second frequency eigenmode function component;

[0030] The step of inputting the plurality of intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result includes:

[0031] Inputting the first frequency eigenmode function component into the first power consumption prediction sub-model for processing to obtain a power consumption prediction value of the first frequency eigenmode function component;

[0032] The second frequency eigenmode function component is input into the second power consumption prediction sub-model for processing to obtain a power consumption prediction value of the second frequency eigenmode function component.

[0033] Optionally, selecting a final layout result from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result includes:

[0034] An initial layout result having the smallest corresponding power consumption prediction value is selected from the at least one initial layout result, and is determined as the final layout result.

[0035] In a second aspect, an embodiment of the present application provides a three-dimensional chip layout device, comprising:

[0036] an acquiring unit, configured to acquire at least one initial layout result of a plurality of chips to be laid out;

[0037] a first input unit, configured to input the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, wherein the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set;

[0038] The first selection unit is configured to select a final layout result from the at least one initial layout result according to a power consumption prediction value corresponding to each initial layout result.

[0039] In a third aspect, an embodiment of the present application provides a terminal device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the three-dimensional chip layout method as described in any one of the first aspects above are implemented.

[0040] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the three-dimensional chip layout method as described in any one of the first aspects above are implemented.

[0041] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device can execute the three-dimensional chip layout method described in any one of the first aspects above.

[0042] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0043] An embodiment of the present application provides a three-dimensional chip layout method. By inputting at least one initial layout result of multiple chips to be laid out into a trained power consumption prediction model for processing, a power consumption prediction value corresponding to each of the at least one initial layout result can be obtained. The power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set. Finally, a final layout result can be selected from the at least one initial layout result based on the power consumption prediction value corresponding to each initial layout result. After obtaining at least one initial layout result, the three-dimensional chip layout method provided in the embodiment of the present application takes into account the impact of power consumption on the three-dimensional chip layout and determines the final layout result of the three-dimensional chip based on the power consumption prediction value corresponding to each initial layout result. This not only improves the layout accuracy of the three-dimensional chip, but also reduces the power consumption of the three-dimensional chip, thereby extending the service life of the three-dimensional chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 This is a flowchart of an implementation method for a three-dimensional chip layout provided in one embodiment of the present application;

[0046] Figure 2 This is a specific implementation flow chart of S101 in the three-dimensional chip layout method provided in one embodiment of the present application;

[0047] Figure 3 is a flowchart of an implementation method of a three-dimensional chip layout provided by another embodiment of the present application;

[0048] Figure 4 is a flowchart of a three-dimensional chip layout method provided in yet another embodiment of the present application;

[0049] Figure 5 This is a flowchart of a three-dimensional chip layout method provided in another embodiment of the present application;

[0050] Figure 6 1 is a schematic structural diagram of a three-dimensional chip layout device provided in one embodiment of the present application;

[0051] Figure 7 It is a structural diagram of a terminal device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0052] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0053] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0054] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0055] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0056] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0058] See also Figure 1 , Figure 1This is a flowchart of a three-dimensional chip layout method provided by an embodiment of the present application. In the embodiment of the present application, the execution subject of the three-dimensional chip layout method is a terminal device.

[0059] like Figure 1 As shown, the layout method of a three-dimensional chip provided in one embodiment of the present application may include S101 to S103, which are described in detail as follows:

[0060] In S101 , at least one initial layout result of a plurality of chips to be laid out is obtained.

[0061] In an embodiment of the present application, when a user needs to layout a three-dimensional chip, a three-dimensional chip layout request can be sent to a terminal device.

[0062] It should be noted that the terminal device may detect that a user has sent the above-mentioned 3D chip layout request by: detecting that the user has opened a preset app or detecting that the user has performed a preset operation within the preset app. The preset operation can be determined based on actual needs and is not limited here. For example, the preset operation may be clicking a preset control. That is, if the terminal device detects that the user has clicked a preset control within a preset app, the preset operation is considered to have been detected, i.e., the user has sent a 3D chip layout request.

[0063] In an embodiment of the present application, after detecting a 3D chip layout request, a terminal device can obtain at least one initial layout result for multiple chips to be laid out in the 3D chip. The initial layout result refers to the position information corresponding to each of the multiple chips to be laid out, which can be represented by 3D coordinates.

[0064] In one implementation of the embodiment of the present application, the terminal device can obtain at least one initial layout result of the plurality of chips to be laid out in real time via a server connected to it by wireless or wired communication. The server can be a computer, desktop computer, or other device.

[0065] In another implementation of the embodiment of the present application, the terminal device may pre-acquire at least one initial layout result for the plurality of chips to be arranged and store it in its own memory. When the terminal device detects a 3D chip layout request, it further acquires at least one initial layout result for the plurality of chips to be arranged from its own memory.

[0066] In some possible embodiments, the terminal device may calculate at least one initial layout result of the plurality of chips to be laid out using an optimization algorithm, wherein the optimization algorithm includes but is not limited to a particle swarm algorithm and a genetic algorithm.

[0067] In one embodiment of the present application, in order to further improve the layout accuracy of three-dimensional chips, the terminal device can combine the particle swarm algorithm and the genetic algorithm to calculate and obtain at least one initial layout result of multiple chips to be laid out.

[0068] Specifically, the terminal device can Figure 2 Steps S201 to S206 shown in the figure obtain at least one initial layout result of the plurality of chips to be laid out, as detailed below:

[0069] In S201 , the plurality of chips to be laid out are used as particles in a particle swarm algorithm, and an initialization operation is performed on the position and speed of each particle.

[0070] In this embodiment, since the particle swarm algorithm is a random search algorithm based on group collaboration developed by simulating the foraging behavior of bird flocks, the terminal device needs to treat each of the multiple chips to be laid out as a particle in the particle swarm algorithm and perform an initialization operation on the position and velocity of each particle to obtain the position and velocity of each particle after the initialization operation is performed, namely, the initialization velocity and the initialization position.

[0071] In S202, the optimal position of each particle is determined according to the position and speed obtained after each particle performs the initialization operation.

[0072] In this embodiment, after obtaining the position and velocity of each particle after performing the initialization operation, that is, the initial velocity and initial position corresponding to each particle, the terminal device can calculate the fitness value of each particle according to the fitness function and determine the optimal position of each particle at that time based on this fitness value. The fitness value corresponding to the optimal position of each particle is used to represent the temperature of multiple chips to be placed.

[0073] In practical applications, the fitness function may be a Griewank function, a Schaffer function, etc., which is not limited here.

[0074] In one embodiment of the present application, the design principle of the fitness function can be: first, the temperature of each chip to be placed is replaced by the center temperature of each chip to be placed. The internal and external heat equations of the i-th chip to be placed are:

[0075] T i =bf1+l i / 2B i

[0076] T i+1,i =bf2K(mD i+1,i ),D i+1,i ≥1;

[0077] Among them, Ti represents the temperature of the i-th chip to be laid out, D i+1,i Indicates the distance between the i-th chip to be laid out and the i+1-th chip to be laid out, B i represents the Biot number of the i-th chip to be laid out, l i Indicates the thickness of the i-th chip to be laid out. bf1 and bf2 are constant values ​​obtained by Bessel functions. i+1,i It represents the contribution temperature of the i+1th chip to be laid out to the ith chip to be laid out, h is the heat transfer coefficient, k is the thermal conductivity coefficient, and R is a constant.

[0078] This gives the total temperature of the device:

[0079]

[0080] Where M represents the total number of chips to be laid out.

[0081] After calculating the chip's own temperature, the heat transferred from the upper chip to the lower chip can be calculated using the heat conduction formula:

[0082]

[0083] Where Q represents the heat transferred from the i+1th chip to be placed to the ith chip to be placed, δ represents the heat transfer coefficient, S represents the heat transfer area of ​​the i+1th chip to be placed, ΔT represents the temperature difference between the i+1th chip to be placed and the ith chip to be placed, and ΔL represents the heat conduction distance between the i+1th chip to be placed and the ith chip to be placed.

[0084] It should be noted that after determining the optimal position of each particle at this time, the terminal device can also determine the optimal position of the entire particle group (ie, multiple chips to be laid out) at this time based on the optimal position of each particle at this time.

[0085] In S203 , an update operation is performed on the position and velocity of each particle.

[0086] In this embodiment, after obtaining the optimal position of each particle, the terminal device may update the position and speed of each particle according to the speed update formula and the position update formula to obtain the updated speed and position of each particle.

[0087] In one embodiment of the present application, the updated speed of the i-th particle can be calculated according to the following speed update formula:

[0088] v ik (t+1)=w(t)*v ik (t)+c1r1[P ik (t)-xik (t)]+c2r2[P gk (t)-x ik (t)];

[0089] Among them, v ik (t+1) represents the velocity of the i-th particle after update, v ik (t) represents the velocity of the i-th particle before updating, x ik (t) represents the position of the i-th particle before updating, P ik (t) represents the optimal position of the i-th particle before updating, P gk (t) represents the optimal position of the entire particle swarm before the update, c1 and c2 represent accelerations, with a value of 1.5, r1 and r2 represent random numbers between [0,1], t represents the number of update operations before the update, and w(t) represents the inertia weight value.

[0090] It should be noted that the weight value w(t) can be calculated according to the following formula:

[0091]

[0092] Among them, w(t) represents the weight value, w max Indicates the maximum inertia weight value, w min Represents the minimum inertia weight value, β represents the iteration value, and the value of β can be set to 200.

[0093] In another embodiment of the present application, the updated position of the i-th particle can be calculated according to the following position update formula:

[0094] x ik (t+1)=x ik (t)-v ik (t+1);

[0095] Among them, x ik (t+1) represents the updated position of the i-th particle, x ik (t) represents the position of the i-th particle before updating, v ik (t+1) represents the updated velocity of the i-th particle.

[0096] In S204, a genetic algorithm is used to perform crossover and mutation operations on each particle according to the updated position and speed of each particle, and an update operation is performed on the optimal position of each particle according to the results of the crossover and mutation operations.

[0097] In practical applications, genetic algorithms are computational models of biological evolution that simulate the natural selection and genetic mechanisms of Darwin's theory of evolution. They are a method for searching for optimal solutions by simulating the natural evolutionary process. Through mathematical methods and computer simulation, these algorithms transform the problem-solving process into a process similar to the crossover and mutation of chromosome genes in biological evolution.

[0098] In one embodiment of the present application, the terminal device can specifically Figure 3 Steps S301 to S302 shown perform crossover and mutation operations on the updated position and velocity of each particle, as detailed below:

[0099] In S301 , a crossover operation is performed on the updated position of the target particle and the optimal position of the target particle according to a preset crossover operator to obtain a first position of the target particle.

[0100] In S302 , a mutation operation is performed on the updated position of the target particle according to a preset mutation operator to obtain a second position of the target particle.

[0101] In this embodiment, the preset crossover operator and the preset mutation operator can be determined according to actual needs and are not limited here.

[0102] It should be noted that the target particle can be any particle among the particles, that is, each particle in the entire particle group needs to execute the above steps S301 to S302.

[0103] In another embodiment of the present application, after the terminal device performs crossover and mutation operations on the target particles according to the genetic algorithm and obtains the results of the crossover and mutation operations, it can calculate the fitness value corresponding to the optimal position of the target particles after performing the crossover and mutation operations, as well as the fitness value corresponding to the optimal position of the target particles before performing the crossover and mutation operations (i.e., the updated position obtained by the target particles executing step S203).

[0104] In another embodiment of the present application, in combination with S301 to S302, since the terminal device can obtain the first position of the target particle after performing the cross operation on the target particle, and can obtain the second position of the target particle after performing the mutation operation on the target particle, the terminal device can specifically perform the following steps: Figure 3 Steps S303 to S304 shown in FIG. 3 obtain the fitness value of the optimal position of the target particle after performing the crossover and mutation operations, as detailed below:

[0105] In S303 , a first fitness value corresponding to the first position and a second fitness value corresponding to the second position are calculated respectively.

[0106] In S304, the smaller value between the first fitness value and the second fitness value is determined as the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed.

[0107] In this embodiment, the terminal device may calculate a first fitness value corresponding to the first position of the target particle and a second fitness value corresponding to the second position of the target particle according to the fitness function.

[0108] After obtaining the first fitness value and the second fitness value, the terminal device can compare the first fitness value and the second fitness value, and determine the fitness value with the smaller value of the above two fitness values ​​as the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed. At the same time, the terminal device determines the optimal position corresponding to the fitness value with the smaller value of the above two fitness values ​​as the optimal position of the target particle after the crossover and mutation operations are performed.

[0109] After obtaining the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed, the terminal device can perform an update operation on the optimal position of the target particle according to the fitness values ​​corresponding to the optimal positions before and after the crossover and mutation operations are performed.

[0110] Specifically, the terminal device can compare the fitness value corresponding to the optimal position of the target particle before the crossover and mutation operation is performed with the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operation is performed, and perform an update operation on the optimal position of the target particle according to the comparison result.

[0111] In this embodiment, when the terminal device detects that the fitness value corresponding to the optimal position of the target particle before performing the crossover and mutation operation is greater than the fitness value corresponding to the optimal position of the target particle after performing the crossover and mutation operation, the terminal device can determine the optimal position of the target particle after performing the crossover and mutation operation as the optimal position of the target particle after update.

[0112] When the terminal device detects that the fitness value corresponding to the optimal position of the target particle before the crossover and mutation operations are less than the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed, the optimal position of the target particle before the crossover and mutation operations can be determined as the optimal position of the target particle after the update.

[0113] In this embodiment, after the terminal device updates the optimal position of each particle based on the results of the crossover and mutation operations, it can record the number of times the optimal position of each particle has been updated and compare this number with a set iteration value. The set iteration value can be set according to actual needs. For example, the iteration value can be set to 200.

[0114] In one embodiment of the present application, if the terminal device detects that the number of times the optimal position of each particle is updated is less than a set iteration value, steps S205 to S206 are executed.

[0115] In another embodiment of the present application, if the terminal device detects that the number of times the optimal position of each particle is updated reaches a set iteration value, it stops executing the step of performing the update operation on the position and speed of each particle and the subsequent steps (i.e., S203 to S204), and determines the optimal position of each particle after the update operation as the final optimal position of each particle, and executes step S206.

[0116] In S205, if the number of times the update operation is performed on the optimal position of each particle is less than the set iteration value, the process returns to the step of performing the update operation on the position and velocity of each particle until the number of times the update operation is performed on the optimal position of each particle reaches the iteration value, thereby obtaining the final optimal position of each particle.

[0117] In this embodiment, when the terminal device detects that the number of times the update operation is performed on the optimal position of each particle is less than the set iteration value, it means that the number of update operations is insufficient. In order to improve the accuracy of the final optimal position, thereby improving the layout accuracy of the three-dimensional chip, the terminal device needs to return to the step of performing the update operation on the position and speed of each particle, and perform update operations on the speed and position of each particle after the update operation is performed on the optimal position according to the results of the crossover and mutation operations at this time, until the number of times the update operation is performed on the optimal position of each particle reaches the set iteration value. When the number of times the update operation is performed on the optimal position of each particle reaches the set iteration value, the optimal position after the update operation is performed the number of times at this time is determined as the final optimal position of each particle.

[0118] In S206 , the final optimal position of each particle is determined as the initial layout result.

[0119] In this embodiment, the terminal device may use the final optimal position of each particle as an initial layout result.

[0120] In actual applications, after obtaining an initial layout result, the terminal device may continue to execute steps S201 to S206 to obtain multiple initial layout results.

[0121] It should be noted that when the terminal device executes steps S201 to S206 to obtain the next initial layout result, in order to avoid the next initial layout result being the same as the previous initial layout result, the initial position and initial velocity obtained by performing the initialization operation on the position and velocity of each particle at this time need to be different from the initial position and initial velocity obtained by performing the initialization operation on the previous initial layout result.

[0122] In S102, the at least one initial layout result is input into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result. The power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set.

[0123] In an embodiment of the present application, after obtaining at least one initial layout result, the terminal device may sequentially input each initial layout result into a trained power consumption prediction model for processing, thereby obtaining a power consumption prediction value corresponding to each initial layout result.

[0124] It should be noted that the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set, wherein the neural network may be a Broad Learning System (BLS) network.

[0125] In one embodiment of the present application, the power consumption prediction model can be trained according to the following steps:

[0126] The historical power consumption dataset is divided into a training set, a validation set, and a test set, with the ratio of the training set, validation set, and test set being 2:1:1.

[0127] Normalize the above training set, validation set and test set, and generate new training subsets from the above normalized training set, validation set and test set Validation subset and the test subset Among them, N T represents the training set before normalization, N V represents the validation set before normalization, N C represents the test set before normalization;

[0128] According to the multi-input multi-output method ({x(t+1),x(t+2),...,x(t+p)}=f(x(t),x(t-1),...,x(t-d+1))), d inputs x are input to the initial power consumption prediction model to generate p outputs y to construct a new training set. New validation set and new test set

[0129] Finally, the initial power consumption prediction model is trained using the new training set and the new validation set through the width learning network to obtain the trained power consumption prediction model. The overall expression formula of the width learning system is:

[0130]

[0131] Among them, ξ represents the learning rate set by the width learning network, Y represents the output of the width learning network, W represents the output weight, β represents the bias value, and Z n represents the nth feature, Z i =φ(XW ei +β ei ), i = 1, 2, ..., n, φ i (XW ei +βe i ) represents the characteristic function, H represents the enhanced node, W hi represents the randomly generated connection weight, β hi Indicates bias.

[0132] In S103 , a final layout result is selected from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result.

[0133] In the embodiment of the present application, after obtaining the power consumption prediction value corresponding to each initial layout result, the terminal device can determine the initial layout result that meets the preset conditions as the final layout result. The preset conditions can be set according to actual needs and are not limited here.

[0134] In one embodiment of the present application, the preset condition may be: taking the smallest value, that is, the terminal device may determine the initial layout result with the smallest power consumption prediction value among at least one initial layout result as the final layout result.

[0135] In another embodiment of the present application, the preset condition may be that the value is less than a preset threshold, i.e., the terminal device may determine all initial layout results whose power consumption prediction value is less than the preset threshold as the final layout result. The preset threshold can be set according to actual needs and is not limited here.

[0136] As can be seen from the above, a layout method for a three-dimensional chip provided in an embodiment of the present application can obtain a power consumption prediction value corresponding to each of the at least one initial layout result by inputting at least one initial layout result of multiple chips to be laid out into a trained power consumption prediction model for processing. The power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set; finally, a final layout result can be selected from the at least one initial layout result based on the power consumption prediction value corresponding to each initial layout result. After obtaining at least one initial layout result, the layout method for a three-dimensional chip provided in an embodiment of the present application takes into account the impact of power consumption on the layout of the three-dimensional chip and determines the final layout result of the three-dimensional chip based on the power consumption prediction values ​​corresponding to each initial layout result. This not only improves the layout accuracy of the three-dimensional chip, but also reduces the power consumption of the three-dimensional chip, thereby extending the service life of the three-dimensional chip.

[0137] See also Figure 4 , Figure 4 This is a flowchart of a three-dimensional chip layout method provided by another embodiment of the present application. Figure 1 In a corresponding embodiment, the three-dimensional chip layout method provided in this embodiment may further include S401 before step S102. Accordingly, step S102 may specifically include S402 to S403, which are described in detail as follows:

[0138] In S401 , the at least one initial layout result is decomposed according to an empirical mode decomposition algorithm to obtain a margin and a plurality of intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result.

[0139] In practical applications, the Empirical Mode Decomposition (EMD) algorithm is a novel adaptive signal time-frequency processing method. EMD decomposes complex signals into a finite number of Intrinsic Mode Functions (IMFs), each of which contains local characteristic signals of the original signal at different time scales. EMD can stabilize non-stationary data, then perform a Hilbert transform to obtain a time-frequency spectrum, resulting in physically meaningful frequencies.

[0140] In this embodiment, for any initial layout result, the terminal device may decompose the initial layout result according to the empirical mode decomposition algorithm, thereby obtaining a margin and multiple intrinsic mode function components corresponding to the initial layout result.

[0141] In S402, a plurality of intrinsic mode function components corresponding to the target layout result are input into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

[0142] In this embodiment, the target layout result is any one of the at least one initial layout result. That is, the terminal device needs to perform steps S402 to S403 on any one of the at least one initial layout result.

[0143] It should be noted that the power consumption prediction model may include, but is not limited to: a first power consumption prediction sub-model and a second power consumption prediction sub-model. The first power consumption prediction sub-model is used to predict the power consumption prediction value of the first frequency eigenmode function component, and the second power consumption prediction sub-model is used to predict the power consumption prediction value of the second frequency eigenmode function component. The frequency corresponding to the first frequency eigenmode function component is higher than the frequency corresponding to the second frequency eigenmode function component.

[0144] In some possible embodiments, the frequency corresponding to the first frequency eigenmode function component may be greater than a preset frequency threshold, and the frequency corresponding to the second frequency eigenmode function component may be less than the preset frequency threshold. The preset frequency threshold can be set according to actual needs and is not limited here.

[0145] Based on this, in one embodiment of the present application, the terminal device can specifically Figure 5 Steps S501 to S503 shown in FIG. 5 obtain the power consumption prediction value of each eigenmode function component, as detailed below:

[0146] In S501, multiple eigenmode function components corresponding to the target layout result are divided into first-frequency eigenmode function components and second-frequency eigenmode function components, where the frequency corresponding to the first-frequency eigenmode function component is higher than the frequency corresponding to the second-frequency eigenmode function component.

[0147] In S502, the first frequency eigenmode function component is input into the first power consumption prediction sub-model for processing to obtain a power consumption prediction value of the first frequency eigenmode function component.

[0148] In S503, the second frequency eigenmode function component is input into the second power consumption prediction sub-model for processing to obtain a power consumption prediction value of the second frequency eigenmode function component.

[0149] In this embodiment, since the terminal device decomposes the target layout result according to the empirical mode decomposition algorithm, the frequency of each of the multiple eigenmode function components obtained is different. Therefore, the terminal device can divide the above-mentioned multiple eigenmode function components according to the preset frequency threshold to obtain a first frequency eigenmode function component and a second frequency eigenmode function component.

[0150] After the terminal device obtains the first frequency eigenmode function component and the second frequency eigenmode function component, in order to improve the accuracy of the power consumption prediction values ​​of the eigenmode function components of different frequencies, the terminal device can input the first frequency eigenmode function component into the first power consumption prediction sub-model for processing to obtain the power consumption prediction value of the first frequency eigenmode function component, and input the second frequency eigenmode function component into the second power consumption prediction sub-model for processing to obtain the power consumption prediction value of the second frequency eigenmode function component.

[0151] In practical applications, there may be one or more first-frequency eigenmode function components, and there may also be one or more second-frequency eigenmode function components.

[0152] Therefore, in one embodiment of the present application, when there are multiple first-frequency eigenmode function components, the terminal device can input each of the multiple first-frequency eigenmode function components into the first power consumption prediction sub-model for processing in turn, obtain the power consumption prediction value of each of the multiple first-frequency eigenmode function components, and sum the power consumption prediction values ​​of each first-frequency eigenmode function component to obtain the power consumption prediction values ​​of the multiple first-frequency eigenmode function components.

[0153] When there are multiple frequency eigenmode function components in the second step, the terminal device can input each of the multiple second frequency eigenmode function components into the second power consumption prediction sub-model for processing in turn, obtain the power consumption prediction value of each second frequency eigenmode function component in the multiple second frequency eigenmode function components, and sum the power consumption prediction values ​​of each second frequency eigenmode function component to obtain the power consumption prediction values ​​of the multiple second frequency eigenmode function components.

[0154] In S403, a power consumption prediction value corresponding to the target layout result is calculated based on the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

[0155] In this embodiment, after obtaining the power consumption prediction value of each eigenmode function component corresponding to the target layout result, the terminal device may sum the power consumption prediction values ​​of each eigenmode function component to obtain the power consumption prediction value corresponding to the target layout result.

[0156] From the above, it can be seen that the present embodiment provides a layout method for a three-dimensional chip, which decomposes the target initial layout result according to the empirical mode decomposition algorithm to obtain a margin and multiple intrinsic mode function components corresponding to the target initial layout result, and inputs the multiple intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result; based on the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result, a power consumption prediction value corresponding to the target layout result is calculated, which can improve the calculation accuracy of the power consumption prediction value, thereby improving the layout accuracy of the three-dimensional chip.

[0157] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0158] Corresponding to the layout method of a three-dimensional chip described in the above embodiment, Figure 6 The structure block diagram of a three-dimensional chip layout device provided by an embodiment of the present application is shown. For the sake of convenience, only the parts related to the embodiment of the present application are shown. Figure 6 The three-dimensional chip layout device 600 includes: an acquisition unit 61, a first input unit 62 and a first selection unit 63.

[0159] The acquisition unit 61 is configured to acquire at least one initial layout result of a plurality of chips to be laid out.

[0160] The first input unit 62 is used to input the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result. The power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set.

[0161] The first selection unit 63 is configured to select a final layout result from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result.

[0162] In one embodiment of the present application, the acquisition unit 61 specifically includes: an initialization unit, a first calculation unit, a first update unit, a second update unit, a first determination unit, and a second determination unit.

[0163] The initialization unit is used to use the multiple chips to be laid out as particles in the particle swarm algorithm and perform an initialization operation on the position and speed of each particle.

[0164] The first calculation unit is used to determine the optimal position of each particle according to the position and speed obtained after each particle performs the initialization operation.

[0165] The first updating unit is used to perform an updating operation on the position and velocity of each particle.

[0166] The second updating unit is used to perform crossover and mutation operations on each particle using a genetic algorithm according to the updated position and speed of each particle, and to perform an update operation on the optimal position of each particle according to the results of the crossover and mutation operations.

[0167] The first determining unit is configured to return to the step of performing an updating operation on the position and velocity of each particle if the number of times the updating operation is performed on the optimal position of each particle is less than a set iteration value, until the number of times the updating operation is performed on the optimal position of each particle reaches the iteration value, thereby obtaining a final optimal position of each particle.

[0168] The second determining unit is used to determine the final optimal position of each particle as an initial layout result.

[0169] In one embodiment of the present application, the target particle is any one of the particles, and the second updating unit is specifically used to: if the fitness value corresponding to the optimal position of the target particle before performing the crossover and mutation operations is greater than the fitness value corresponding to the optimal position of the target particle after performing the crossover and mutation operations, then determine the optimal position of the target particle after performing the crossover and mutation operations as the optimal position of the target particle after update; wherein the fitness value corresponding to the optimal position of each of the particles is used to characterize the temperature of the multiple chips to be laid out.

[0170] In one embodiment of the present application, the second updating unit specifically includes: a crossover unit, a mutation unit, a second calculation unit, and a third determination unit.

[0171] The crossover unit is configured to perform a crossover operation on the updated position of the target particle and the optimal position of the target particle according to a preset crossover operator to obtain a first position of the target particle.

[0172] The mutation unit is used to perform a mutation operation on the updated position of the target particle according to a preset mutation operator to obtain a second position of the target particle.

[0173] The second calculation unit is used to respectively calculate a first fitness value corresponding to the first position and a second fitness value corresponding to the second position.

[0174] The third determining unit is configured to determine the smaller value between the first fitness value and the second fitness value as the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed.

[0175] In one embodiment of the present application, the layout apparatus 600 for a three-dimensional chip further includes: a decomposition unit; accordingly, the target layout result is any one of the at least one initial layout result, and the first input unit 62 specifically includes: a second input unit and a third calculation unit. Among them:

[0176] The decomposition unit is configured to decompose the at least one initial layout result according to an empirical mode decomposition algorithm to obtain a margin and a plurality of intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result.

[0177] The second input unit is used to input the multiple intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing, so as to obtain the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

[0178] The third calculation unit is configured to calculate the power consumption prediction value corresponding to the target layout result according to the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

[0179] In one embodiment of the present application, the power consumption prediction model includes a first power consumption prediction sub-model and a second power consumption prediction sub-model; the three-dimensional chip layout device 600 further includes: a partitioning unit; and correspondingly, the second input unit specifically includes: a first input sub-unit and a second input sub-unit.

[0180] The division unit is used to divide the multiple eigenmode function components corresponding to the target layout result into a first frequency eigenmode function component and a second frequency eigenmode function component, wherein the frequency corresponding to the first frequency eigenmode function component is higher than the frequency corresponding to the second frequency eigenmode function component.

[0181] The first input sub-unit is used to input the first frequency eigenmode function component into the first power consumption prediction sub-model for processing to obtain a power consumption prediction value of the first frequency eigenmode function component.

[0182] The second input sub-unit is used to input the second frequency eigenmode function component into the second power consumption prediction sub-model for processing to obtain the power consumption prediction value of the second frequency eigenmode function component.

[0183] In one embodiment of the present application, the first selection unit 63 specifically includes: a second selection unit.

[0184] The second selection unit is configured to select an initial layout result having the smallest corresponding power consumption prediction value from the at least one initial layout result, and determine the result as the final layout result.

[0185] As can be seen from the above, the layout device for a three-dimensional chip provided by the embodiment of the present application can obtain a power consumption prediction value corresponding to each of the at least one initial layout result by inputting at least one initial layout result of multiple chips to be laid out into a trained power consumption prediction model for processing. The power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set; finally, a final layout result can be selected from the at least one initial layout result based on the power consumption prediction value corresponding to each initial layout result. After obtaining at least one initial layout result, the layout method for a three-dimensional chip provided by the embodiment of the present application takes into account the impact of power consumption on the layout of the three-dimensional chip and determines the final layout result of the three-dimensional chip based on the power consumption prediction values ​​corresponding to each initial layout result. This not only improves the layout accuracy of the three-dimensional chip, but also reduces the power consumption of the three-dimensional chip, thereby extending the service life of the three-dimensional chip.

[0186] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0187] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0188] Figure 7 This is a schematic diagram of the structure of a terminal device provided in one embodiment of the present application. Figure 7 As shown, the terminal device 7 of this embodiment includes: at least one processor 70 ( Figure 7Only one is shown in the figure) a processor, a memory 71, and a computer program 72 stored in the memory 71 and executable on the at least one processor 70, wherein the processor 70 implements the steps of any of the above-mentioned three-dimensional chip layout method embodiments when executing the computer program 72.

[0189] The terminal device may include, but is not limited to, a processor 70 and a memory 71. Those skilled in the art will understand that Figure 7 It is only an example of the terminal device 7 and does not constitute a limitation on the terminal device 7. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0190] The processor 70 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0191] In some embodiments, the memory 71 may be an internal storage unit of the terminal device 7, such as the memory of the terminal device 7. In other embodiments, the memory 71 may also be an external storage device of the terminal device 7, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device 7. Furthermore, the memory 71 may also include both an internal storage unit of the terminal device 7 and an external storage device. The memory 71 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program. The memory 71 may also be used to temporarily store data that has been output or is about to be output.

[0192] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.

[0193] An embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0194] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program, when executed by the processor, can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to a terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, a computer-readable medium cannot be an electric carrier signal or a telecommunication signal.

[0195] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0196] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0197] In the embodiments provided in this application, it should be understood that the disclosed three-dimensional chip layout device and method can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0198] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0199] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A three-dimensional chip layout method, characterized in that: include: Obtaining at least one initial layout result of a plurality of chips to be laid out; Inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, wherein the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set; Selecting a final layout result from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result; The obtaining of at least one initial layout result of the plurality of chips to be laid out includes: Using the plurality of chips to be laid out as particles in a particle swarm algorithm, and performing an initialization operation on the position and velocity of each particle; Determine the optimal position of each particle based on the position and speed obtained after each particle performs an initialization operation; the optimal position of each particle is determined by the fitness value of each particle, and the fitness value corresponding to the optimal position of each particle is used to characterize the temperature of the multiple chips to be arranged; the temperature of the multiple chips to be arranged includes the total temperature of each chip to be arranged and the heat transferred from the upper chip to the lower chip, and the total temperature of the i-th chip to be arranged includes the temperature of the i-th chip to be arranged and the temperature contributed by the (i+1)-th chip to be arranged to the i-th chip to be arranged; performing an update operation on the position and velocity of each of the particles; performing a crossover and mutation operation on each particle using a genetic algorithm according to the updated position and velocity of each particle, and performing an update operation on the optimal position of each particle according to the results of the crossover and mutation operation; If the number of times the update operation is performed on the optimal position of each particle is less than the set iteration value, returning to the step of performing the update operation on the position and velocity of each particle, until the number of times the update operation is performed on the optimal position of each particle reaches the iteration value, thereby obtaining the final optimal position of each particle; The final optimal position of each particle is determined as the initial layout result.

2. The three-dimensional chip layout method according to claim 1, wherein: The target particle is any one of the particles, and the updating operation is performed on the optimal position of each particle according to the results of the crossover and mutation operations, including: If the fitness value corresponding to the optimal position of the target particle before performing the crossover and mutation operations is greater than the fitness value corresponding to the optimal position of the target particle after performing the crossover and mutation operations, the optimal position of the target particle after performing the crossover and mutation operations is determined as the updated optimal position of the target particle; wherein the fitness value corresponding to the optimal position of each of the particles is used to characterize the temperature of the multiple chips to be laid out.

3. The three-dimensional chip layout method according to claim 2, wherein: The method of performing crossover and mutation operations on each particle using a genetic algorithm according to the updated position and velocity of each particle comprises: Performing a crossover operation on the updated position of the target particle and the optimal position of the target particle according to a preset crossover operator to obtain a first position of the target particle; Performing a mutation operation on the updated position of the target particle according to a preset mutation operator to obtain a second position of the target particle; respectively calculating a first fitness value corresponding to the first position and a second fitness value corresponding to the second position; The smaller value between the first fitness value and the second fitness value is determined as the fitness value corresponding to the optimal position of the target particle after the crossover and mutation operations are performed.

4. The three-dimensional chip layout method according to claim 1, wherein: Before inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, the method further includes: Decomposing the at least one initial layout result according to an empirical mode decomposition algorithm to obtain a margin and a plurality of intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result; The target layout result is any one of the at least one initial layout result, and the step of inputting the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result includes: Inputting a plurality of intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result; The power consumption prediction value corresponding to the target layout result is calculated according to the power consumption prediction value of each intrinsic mode function component corresponding to the target layout result.

5. The three-dimensional chip layout method according to claim 4, wherein: The power consumption prediction model includes a first power consumption prediction sub-model and a second power consumption prediction sub-model; after decomposing the at least one initial layout result according to an empirical mode decomposition algorithm to obtain a margin and multiple intrinsic mode function components corresponding to each initial layout result in the at least one initial layout result, the model further includes: dividing the plurality of eigenmode function components corresponding to the target layout result into a first frequency eigenmode function component and a second frequency eigenmode function component, wherein the frequency corresponding to the first frequency eigenmode function component is higher than the frequency corresponding to the second frequency eigenmode function component; The step of inputting the plurality of intrinsic mode function components corresponding to the target layout result into the power consumption prediction model for processing to obtain a power consumption prediction value of each intrinsic mode function component corresponding to the target layout result includes: Inputting the first frequency eigenmode function component into the first power consumption prediction sub-model for processing to obtain a power consumption prediction value of the first frequency eigenmode function component; The second frequency eigenmode function component is input into the second power consumption prediction sub-model for processing to obtain a power consumption prediction value of the second frequency eigenmode function component.

6. The three-dimensional chip layout method according to any one of claims 1 to 5, characterized in that: The selecting a final layout result from the at least one initial layout result according to the power consumption prediction value corresponding to each initial layout result includes: An initial layout result having the smallest corresponding power consumption prediction value is selected from the at least one initial layout result, and is determined as the final layout result.

7. A three-dimensional chip layout device, characterized in that: include: an acquiring unit, configured to acquire at least one initial layout result of a plurality of chips to be laid out; a first input unit, configured to input the at least one initial layout result into a trained power consumption prediction model for processing to obtain a power consumption prediction value corresponding to each of the at least one initial layout result, wherein the power consumption prediction model is a neural network trained using chip layout results with power consumption prediction values ​​as a training set; A first selection unit, configured to select a final layout result from the at least one initial layout result according to a power consumption prediction value corresponding to each initial layout result; The acquisition unit specifically includes: An initialization unit, configured to use the plurality of chips to be laid out as particles in a particle swarm algorithm and perform an initialization operation on the position and velocity of each particle; a first calculation unit, configured to determine an optimal position of each particle based on a position and velocity obtained after each particle performs an initialization operation; the optimal position of each particle is determined by a fitness value of each particle, and the fitness value corresponding to the optimal position of each particle is used to characterize the temperature of the plurality of chips to be arranged; the temperature of the plurality of chips to be arranged includes a total temperature of each chip to be arranged and heat transferred from an upper chip to a lower chip; the total temperature of the i-th chip to be arranged includes the temperature of the i-th chip to be arranged and a temperature contribution of the (i+1)-th chip to be arranged to the i-th chip to be arranged; A first updating unit, configured to perform an updating operation on the position and velocity of each particle; a second updating unit, configured to perform a crossover and mutation operation on each particle using a genetic algorithm according to the updated position and velocity of each particle, and perform an updating operation on the optimal position of each particle according to the result of the crossover and mutation operation; a first determining unit, configured to, if the number of times the update operation is performed on the optimal position of each particle is less than a set iteration value, return to the step of performing the update operation on the position and velocity of each particle, until the number of times the update operation is performed on the optimal position of each particle reaches the iteration value, thereby obtaining a final optimal position of each particle; The second determining unit is configured to determine the final optimal position of each particle as an initial layout result.

8. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the three-dimensional chip layout method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the three-dimensional chip layout method according to any one of claims 1 to 6 are implemented.

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