Integrated circuit based on 3D packaging

Abstract

Embodiments of the present application provide a 3D package-based integrated circuit, which comprises a memory and a chip, the memory and the chip respectively comprise a first interface module and a second interface module, the first interface module and the second interface module are connected through a 3D package connection line and respectively comprise a first readout circuit and a second readout circuit, at least one of the first readout circuit and the second readout circuit comprises: a first-in-first-out sub-circuit, a flip-flop, a first multiplexer and a second multiplexer. Wherein, the first readout circuit and the second readout circuit are both adapted to filter delay differences and have multiple working modes, in actual operation, the multiple working modes in the first readout circuit and the second readout circuit can be combined with each other to be applied to different normal working stages and test stages. At the same time, the 3D package can also realize the direct interconnection between the dies and greatly reduce the capacitance, thereby effectively reducing the area and power consumption of the circuit board in the integrated circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit based on 3D packaging. BACKGROUND

[0002] In the prior art, a memory packaged in a traditional way uses a high-speed port physical layer to interact with a chip, and a large number of wirings are needed in a printed circuit board, which not only increases the area of the circuit board, but also increases the power consumption of the entire circuit. SUMMARY

[0003] An embodiment of the present application aims to provide an integrated circuit based on 3D packaging.

[0004] The integrated circuit based on 3D packaging comprises a memory and a chip, the memory and the chip respectively comprise a first interface module and a second interface module, the first interface module and the second interface module are connected through a 3D packaging connection line and respectively comprise a first readout circuit and a second readout circuit, wherein at least one of the first readout circuit and the second readout circuit comprises: a first-in-first-out sub-circuit adapted to receive a readout data signal, a readout clock signal and a data selection pulse signal located on a readout path, and adapted to make the readout data signal be output after being sampled by the data selection pulse signal and the readout clock signal in turn; a flip-flop adapted to receive the readout data signal and the readout clock signal located on the readout path, and adapted to make the readout data signal be output after being sampled by the readout clock signal; a first multiplexer, a first input end of which is adapted to receive the readout data signal located on the readout path, and a second input end of which is adapted to receive the readout data signal output by the flip-flop; a second multiplexer, a first input end of which is adapted to receive the readout data signal output by the first-in-first-out sub-circuit, a second input end of which is adapted to receive the readout data signal output by the first multiplexer, and an output end of which is adapted to output a corresponding readout data signal to the chip; the first and second multiplexers are both adapted to select the readout data signal received by the first input end to output when being configured as a first value, and to select the readout data signal received by the second input end to output when being configured as a second value.

[0005] Optionally, the first readout circuit further comprises a third multiplexer, a first input end of which is adapted to receive the readout clock signal located on the readout path, a second input end of which is adapted to receive the data selection pulse signal located on the readout path, and an output end of which is adapted to output a corresponding readout clock signal or data selection pulse signal to the chip; the third multiplexer is adapted to select the readout clock signal received by the first input end to output when being configured as the first value, and to select the data selection pulse signal received by the second input end to output when being configured as the second value.

[0006] Optionally, the first value is 0, and the second value is 1.

[0007] Optionally, the multiplexer is a two-way multiplexer.

[0008] Optionally, the first interface module comprises a first output circuit connected to the first readout circuit, which is adapted to receive the readout data signal output by the first readout circuit and the data selection pulse signal aligned with the readout data signal, and output them to the second interface module through the 3D package connection line.

[0009] Optionally, the second interface module comprises a second input circuit, which is adapted to receive the readout data signal output by the first interface module and the data selection pulse signal aligned with the readout data signal through the 3D package connection line, and output them to the second readout circuit.

[0010] Optionally, the second interface module comprises a second output circuit, which is adapted to receive the readout clock signal output by the chip and output it to the first interface module through the 3D package connection line.

[0011] Optionally, the first interface module comprises a first input circuit, which is adapted to receive the readout clock signal through the 3D package connection line and output it to the first readout circuit.

[0012] Optionally, the second output circuit is further adapted to receive the readout control signal output by the chip and output it to the first input circuit through the 3D package connection line, and the first input circuit is further adapted to output the readout control signal to the memory, so that the memory outputs the readout data signal and the data selection pulse signal to the first readout circuit based on the readout control signal.

[0013] Optionally, the second output circuit is further adapted to receive the write data signal and the write clock signal on the write path output by the chip and output them to the first input circuit through the 3D package connection line; and the first interface module further comprises a write circuit connected to the first input circuit, which is adapted to receive the write data signal and the write clock signal and output the write data signal sampled by the write clock signal to the memory.

[0014] Optionally, the second output circuit is further adapted to receive the write control signal on the write path output by the chip and output it to the first input circuit through the 3D package connection line; and the first input circuit is further adapted to output the write control signal to the memory, so that the memory writes the write data signal output by the write circuit into its array based on the write control signal.

[0015] Compared with the prior art, the technical scheme of the embodiment of the present application has beneficial effects. For example, the memory and the chip using 3D packaging can realize direct interconnection between dies, and the capacitance is much smaller than the wiring in the printed circuit board in the traditional packaging mode, thereby greatly reducing the area and power consumption of the circuit board.

[0016] For another example, the memory side and the chip side are both provided with readout circuits suitable for filtering delay differences, and each readout circuit has multiple working modes. In actual operation, the multiple working modes of the readout circuits of the memory side and the chip side can be combined with each other to be applied to different normal working stages and test stages.

[0017] For another example, through the mutual combination of the multiple working modes of the readout circuits of the memory side and the chip side, not only the transmission speed and reliability of the interface can be increased, but also the test time of the test stage can be reduced.

[0018] For another example, the mutual combination of the multiple working modes of the readout circuits of the memory side and the chip side is very flexible and convenient, and has strong practicability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a structure schematic diagram of an integrated circuit based on 3D packaging in an embodiment of the present application;

[0020] Figure 2 is a structure schematic diagram of a first readout circuit in an embodiment of the present application;

[0021] Figure 3 is a structure schematic diagram of a second readout circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, features and beneficial effects of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0023] With reference to Figure 1 Embodiments of the present application provide an integrated circuit 10. The integrated circuit 10 includes a memory 100 and a chip 200 suitable for performing read and write operations on the memory 100.

[0024] In one or more embodiments, the memory 100 can be a random access memory (RAM). For example, it can be a dynamic random access memory (DRAM), or a static random access memory (SRAM).

[0025] In one or more embodiments, the chip 200 can be a logic chip. For example, it can be a system on a chip (SOC).

[0026] In a specific implementation, the integrated circuit 10 is formed by packaging the memory 100 and the chip 200 together through a 3D packaging technology. In this case, the interface modules between the memory 100 and the chip 200 are connected through the 3D packaging lines 300.

[0027] In one or more embodiments, the memory 100 and the chip 200 can be packaged together by using a 3D packaging technology such as Hybrid Bonding (HB), Through Silicon Via (TSV), etc. For example, in the example shown in FIG. 1, the memory 100 and the chip 200 are packaged together by using the HB packaging technology, and the interface modules between the memory 100 and the chip 200 are connected together through the HB connection lines. Figure 1

[0028] In a specific implementation, the memory 100 can include a first interface module 101, and the chip 200 can include a second interface module 201. The first interface module 101 and the second interface module 201 are connected through the 3D packaging connection lines 300 (e.g., the HB connection lines).

[0029] Referring to FIG. 2, the first interface module 101 can include a first readout (READOUT) circuit 110 and a first output (PAD_OUT) circuit 120 located on a readout path, and a first input (PAD_IN) circuit 130 and a first write-in (WRITE IN) circuit 140 located on a write-in path. The second interface module 201 can include a second readout (READOUT) circuit 210 and a second input (PAD_IN) circuit 220 located on the readout path, and a second output (PAD_OUT) circuit 230 located on the write-in path. Figure 1

[0030] In particular, the second output circuit 230 of the second interface module 201 is adapted to receive the readout clock signal CLK and the readout control signal CONTROL outputted in the subsequent circuit of the chip 200, and output them to the first interface module 101 through the 3D packaging connection lines 300.

[0031] ​​The first input circuit 130 of the first interface module 101 is adapted to receive the readout clock signal CLK and the readout control signal CONTROL output by the second interface module 201 through the 3D packaging connection line 300, and output the readout clock signal CLK to the first readout circuit 110, and output the readout control signal CONTROL to the subsequent circuit of the memory 100 to make the subsequent circuit of the memory 100 output corresponding readout signals to the first readout circuit 110 based on the readout control signal CONTROL. The readout signals include the readout data signal DARA_R and the data selection pulse signal DQS aligned with the readout data signal DARA_R.

[0032] In a specific implementation, the memory 100 further includes a read-write (RW) module 150 and an array module 160 in the subsequent circuit thereof.

[0033] Specifically, the array module 160 is connected with the read-write module 150. The read-write module 150 is connected with the first input circuit 130 and the first readout circuit 110 respectively, and is adapted to receive the readout control signal CONTROL output by the first input circuit 130, and obtain corresponding readout data signal DARA_R from the array module 160 based on the readout control signal CONTROL, and output the readout data signal DARA_R and the data selection pulse signal DQS aligned with the readout data signal DARA_R to the first readout circuit 110.

[0034] In the embodiment of the application, the first readout circuit 110 is adapted to filter the delay difference existing in the data signal transmission process. There are various working modes, but eventually the corresponding readout signals, i.e. the corresponding readout data signal DARA_R and the data selection pulse signal DQS aligned with the readout data signal DARA_R, are output.

[0035] The first output circuit 120 of the first interface module 101 is adapted to receive the readout signals output by the first readout circuit 110, and output the readout signals to the second interface module 201 through the 3D packaging connection line 300.

[0036] The second input circuit 220 of the second interface module 201 is adapted to receive the readout signals output by the first interface module 101 through the 3D packaging connection line 300, and output the readout signals to the second readout circuit 210.

[0037] In the embodiment of the present application, the second readout circuit 210 is also adapted to filter the delay difference existing in the data signal transmission process, and there are also various working modes, but eventually the corresponding readout signals, i.e. the corresponding readout data signal DARA_R and the data selection pulse signal DQS aligned with the readout data signal DARA_R, are output to the subsequent circuit of the chip 200.

[0038] Further, the second output circuit 230 of the second interface module 201 is also adapted to receive the write data signal DATA_W, the write clock signal CLK and the write control signal CONTROL output by the subsequent circuit of the chip 200 on the write path, and output the three through the 3D packaging connection line 300 to the first interface module 101.

[0039] The first input circuit 130 of the first interface module 101 is adapted to receive the write data signal DATA_W, the write clock signal CLK and the write control signal CONTROL output by the second interface module 201 through the 3D packaging connection line 300, and output the write data signal DATA_W and the write clock signal CLK to the write circuit 140 so that the write data signal DATA_W is sampled by the write clock signal CLK and then output to the read-write module 150 through the write circuit 140, and output the write control signal CONTROL directly to the read-write module 150.

[0040] The read-write module 150 is connected with the write circuit 140 and the first input circuit 130 respectively, and is adapted to receive the write data signal DATA_W output by the write circuit 140 and the write control signal CONTROL output by the first input circuit 130, and can write the write data signal DATA_W output by the write circuit 140 into the array module 160 based on the write control signal CONTROL.

[0041] Therefore, in the embodiment of the present application, along the direction of data readout, the array module 160, the read-write module 150, the first readout circuit 110, the first output circuit 120, the 3D packaging connection line 300, the second input circuit 220 and the second readout circuit 210 are connected in sequence; along the direction of data writing, the second output circuit 230, the 3D packaging connection line 300, the first input circuit 130, the write circuit 140, the read-write module 150 and the array module 160 are connected in sequence.

[0042] In performing a read operation, the chip 200 sends a read clock signal CLK and a read control signal CONTROL to the second output circuit 230, and then outputs the read clock signal CLK and the read control signal CONTROL to the first input circuit 130 of the memory 100 through the 3D packaging connection line 300. The first input circuit 130 sends the read control signal CONTROL to the read-write module 150 and sends the read clock signal CLK to the first read circuit 110. The read-write module 150 is adapted to obtain a corresponding read data signal DATA_R from the array module 160 based on the received read control signal CONTROL, and output the read data signal DATA_R and a data selection pulse signal DQS aligned with the read data signal DATA_R to the first read circuit 110. There are various working modes in the first read circuit 110, but eventually the corresponding read data signal DATA_R and the data selection pulse signal DQS aligned with the read data signal DATA_R are sequentially output to the second input circuit 220 of the chip 200 through the first output circuit 120 and the 3D packaging connection line 300. The second input circuit 220 outputs the corresponding read data signal DATA_R and the data selection pulse signal DQS aligned with the read data signal DATA_R to the second read circuit 210. There are various working modes in the second read circuit 210, but eventually the corresponding read data signal DATA_R is output to the subsequent circuit of the chip 200.

[0043] In performing a write operation, the chip 200 sends a write data signal DATA_W, a write clock signal CLK, and a write control signal CONTROL to the second output circuit 230, and then outputs the write data signal DATA_W, the write clock signal CLK, and the write control signal CONTROL to the first input circuit 130 of the memory 100 through the 3D packaging connection line 300. The first input circuit 130 sends the write control signal CONTROL to the read-write module 150 and sends the write data signal DATA_W and the write clock signal CLK to the write circuit 140. In the write circuit 140, the write data signal DATA_W is sampled by the write clock signal CLK. The sampled write data signal DATA_W is sent to the read-write module 150, and under the action of the read-write module 150, the sampled write data signal DATA_W is finally written into the array module 160.

[0044] Generally, the integrated circuit 10 will deviate due to different manufacturing processes of the memory 100, the chip 200, and the 3D packaging, thereby causing a delay difference in performing a write and / or read operation.

[0045] In the embodiment of the application, the delay difference can be filtered by the first read circuit 110 and / or the second read circuit 210.

[0046] In a specific implementation, at least one of the first readout circuit 110 and the second readout circuit 210 comprises a First In First Out (FIFO) sub-circuit, a flip-flop, a first multiplexer (MUX1) and a second multiplexer (MUX2).

[0047] Referring to Figure 2 In one or more embodiments, the first readout circuit 110 can comprise a first FIFO sub-circuit 111, a first flip-flop 112, a first multiplexer 113 and a second multiplexer 114 for the memory 100.

[0048] Referring to Figure 3 In one or more embodiments, the second readout circuit 210 can comprise a second FIFO sub-circuit 211, a second flip-flop 212, a first multiplexer 213 and a second multiplexer 214 for the chip 200.

[0049] In particular, the first FIFO sub-circuit 111 and / or the second FIFO sub-circuit 211 are adapted to receive a readout data signal DQR_IN (i.e., the readout data signal DARA_R outputted by the read-write module 150) on the readout path, a readout clock signal CLK (i.e., the readout clock signal CLK outputted by the first input module 130), and a data selection pulse signal DQS_IN (i.e., the data selection pulse signal DQS aligned with the readout data signal DARA_R outputted by the read-write module 150), and to output the readout data signal DQR_IN sequentially sampled by the data selection pulse signal DQS_IN and the readout clock signal CLK.

[0050] The first flip-flop 112 and / or the second flip-flop 212 are adapted to receive a readout data signal DQR_IN (i.e., the readout data signal DARA_R outputted by the read-write module 150) on the readout path, a readout clock signal CLK (i.e., the readout clock signal CLK outputted by the first input module 130), and to output the readout data signal DQR_IN sampled by the readout clock signal CLK.

[0051] In one or more embodiments, the flip-flop can be a D Flip-Flop (DFF).

[0052] The first multiplexer 113 for the memory 100 and / or the first multiplexer 213 for the chip 200 comprises at least two input terminals and one output terminal, wherein the first input terminal is adapted to receive the read data signal DQR_IN located on the read path (i.e. the read data signal DARA_R outputted by the read-write module 150), the second input terminal is adapted to receive the read data signal outputted by the corresponding flip-flop, and the output terminal is adapted to output the corresponding read data signal to the corresponding second multiplexer.

[0053] The second multiplexer 114 for the memory 100 and / or the second multiplexer 214 for the chip 200 comprises at least two input terminals and one output terminal, wherein the first input terminal is adapted to receive the read data signal outputted by the corresponding first-in-first-out sub-circuit, the second input terminal is adapted to receive the read data signal outputted by the corresponding first multiplexer, and the output terminal is adapted to output the corresponding read data signal DQR_OUT to the chip 200.

[0054] In one or more embodiments, the first and second multiplexers are adapted to output the read data signal received by the first input terminal when configured as a first value, and output the read data signal received by the second input terminal when configured as a second value.

[0055] In one or more embodiments, the first value can be 0, and the second value can be 1.

[0056] With reference to Figure 2 , the first read circuit 110 further comprises a third multiplexer (Multiplexer 3, MUX 3) 115. The third multiplexer 115 comprises at least two input terminals and one output terminal, wherein the first input terminal is adapted to receive the read clock signal CLK located on the read path (i.e. the read clock signal CLK outputted by the first input module 130), the second input terminal is adapted to receive the data selection pulse signal DQS_IN located on the read path (i.e. the data selection pulse signal DQS aligned with the read data signal DARA_R outputted by the read-write module 150), and the output terminal is adapted to output the corresponding read clock signal CLK or data selection pulse signal DQS_IN to the chip 200.

[0057] In one or more embodiments, the third multiplexer 115 is adapted to output the read clock signal CLK received by the first input terminal when configured as a first value, and output the data selection pulse signal DQS_IN received by the second input terminal when configured as a second value.

[0058] In one or more embodiments, the first value can be 0, and the second value can be 1.

[0059] In one or more embodiments, the first, second, and third multiplexers can each be a two-way multiplexer.

[0060] In embodiments of the present application, the first readout circuit 110 and the second readout circuit 210 each have multiple working modes.

[0061] The following describes three important working modes of the first readout circuit 110 and the second readout circuit 210 respectively. For ease of description, the first values for configuring the first, second, and third multiplexers can each be set to 0, and the second values can each be set to 1.

[0062] For the first working mode of the first readout circuit 110:

[0063] Referring to Figure 2 In the first readout circuit 110, when Cl is set to 0, C2 is set to 0, and C3 is set to 0, the readout data signal DQR IN is first sampled by the data selection pulse signal DQS IN, then sampled by the readout clock signal CLK, and finally output as the readout data signal DQR OUT (output to the first output circuit 120) output by the first readout circuit 110 through the second multiplexer 114 for the memory 100. At the same time, the readout clock signal CLK is output as the data selection pulse signal DQS OUT (output to the first output circuit 120) aligned with the readout data signal DQR OUT through the third multiplexer 115.

[0064] For the second working mode of the first readout circuit 110:

[0065] Referring to Figure 2 In the first readout circuit 110, when Cl is set to 1, C2 is set to 1, and C3 is set to 0, the readout data signal DQR IN is sampled by the readout clock signal CLK after being sampled by the readout clock signal CLK in the first flip-flop 112, and then output as the readout data signal DQR OUT (output to the first output circuit 120) output by the first readout circuit 110 through the first multiplexer 113 and the second multiplexer 114 for the memory 100. At the same time, the readout clock signal CLK is output as the data selection pulse signal DQS OUT (output to the first output circuit 120) aligned with the readout data signal DQR OUT through the third multiplexer 115.

[0066] For the third working mode of the first readout circuit 110:

[0067] Referring to Figure 2In the first readout circuit 110, when Cl is set to 0, C2 is set to 1, and C3 is set to 1, the readout data signal DQR_IN is output directly as the readout data signal DQR_OUT output from the first readout circuit 110 (output to the first output circuit 120) through the first multiplexer 113 and the second multiplexer for the memory 100. At the same time, the data selection pulse signal DQS_IN is output as the data selection pulse signal DQS_OUT output in alignment with the readout data signal DQR_OUT (output to the first output circuit 120) through the third multiplexer 115.

[0068] For the first mode of operation of the second readout circuit 210:

[0069] Referring to Figure 3 In the second readout circuit 210, when Cl is set to 0 and C2 is set to 0, the readout data signal DQR_IN is first sampled by the data selection pulse signal DQS_IN in the second first-in-first-out sub-circuit 211, then sampled by the readout clock signal CLK, and finally output as the readout data signal DQR_OUT output from the second readout circuit 210 through the second multiplexer 214 for the chip 200.

[0070] For the second mode of operation of the second readout circuit 210:

[0071] Referring to Figure 3 In the second readout circuit 210, when Cl is set to 1 and C2 is set to 1, the readout data signal DQR_IN is sampled by the readout clock signal CLK in the second flip-flop 212, and then output as the readout data signal DQR_OUT output from the second readout circuit 210 through the first multiplexer 213 and the second multiplexer 214 for the chip 200 in turn.

[0072] For the third mode of operation of the second readout circuit 210:

[0073] Referring to Figure 3 In the second readout circuit 210, when Cl is set to 0 and C2 is set to 1, the readout data signal DQR_IN is output directly as the readout data signal DQR_OUT output from the second readout circuit 210 through the first multiplexer 213 and the second multiplexer 214 for the chip 200.

[0074] Generally, when using a first-in-first-out circuit to filter the delay difference (the first mode of operation of the first readout circuit 110 and the second readout circuit 210), the delay time is increased, and the delay time can be extended to 3 cycles or more. This is inevitable and acceptable in the normal working phase.

[0075] Specifically, in the normal working phase, the third working mode (i.e., the third working mode of the first readout circuit 110) can be selected at the memory 100 end, and the first working mode (i.e., the first working mode of the second readout circuit 210) can be selected at the chip 200 end. In this configuration, the readout data signal of the memory 100 can be directly transmitted to the chip 200, and the second FIFO sub-circuit 211 is used at the chip 200 end. At this time, the delay difference caused by the memory 100 and the 3D packaging connection line 300 will be filtered out in the second FIFO sub-circuit 211 of the chip 200.

[0076] In the normal working phase, the first working mode (i.e., the first working mode of the first readout circuit 110) can be selected at the memory 100 end, and the third working mode (i.e., the third working mode of the second readout circuit 210) can be selected at the chip 200 end. In this configuration, the readout data signal of the memory 100 is first filtered by the first FIFO sub-circuit 111 to eliminate the delay difference, and then transmitted to the chip 200. The chip 200 directly transmits the received readout data signal to the subsequent circuit.

[0077] In the normal working phase, the first working mode (i.e., the first working mode of the first readout circuit 110) can be selected at the memory 100 end, and the first working mode (i.e., the first working mode of the second readout circuit 210) can be selected at the chip 200 end. In this configuration, the readout data signal is first filtered by the first FIFO sub-circuit 111, and then filtered by the second FIFO sub-circuit 211. The delay difference is filtered twice, and at this time, the reliability of the readout data signal is maximally guaranteed.

[0078] However, in the test phase, the clock frequency is much lower than the normal working frequency. If the FIFO circuit is used to filter the delay difference, the delay time will be extended to 3 cycles or more, thereby wasting a large amount of test time. Therefore, in the test phase, the flip-flop (the second working mode of the first readout circuit 110 and the second readout circuit 210) can be selected to filter the delay difference, so as to compress the delay time to 1 cycle.

[0079] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if a single embodiment is described with respect to a particular feature. The features provided in the present disclosure are intended to be illustrative rather than limiting, unless otherwise specified. In the specific implementation, one or more technical features of the dependent claims can be combined with the technical features of the independent claims, and the technical features from the corresponding independent claims can be combined in any appropriate manner rather than only through the specific combinations listed in the claims, if technically feasible.

[0080] While the application has been disclosed with reference to various implementations, it will be understood that various other modifications can be made without departing from the spirit and scope of the application. Therefore, it is not intended that the application be limited to the specific disclosed embodiments.

Claims

1. A 3D package-based integrated circuit, characterized by, The memory includes a first interface module, and the chip includes a second interface module, the first interface module and the second interface module are connected through a 3D packaging connection line, and the first interface module includes a first readout circuit, and the second interface module includes a second readout circuit, at least one of the first readout circuit and the second readout circuit includes: A first-in-first-out subcircuit adapted to receive a readout data signal, a readout clock signal and a data selection pulse signal located on a readout path, and adapted to cause the readout data signal to be output after being sampled by the data selection pulse signal and the readout clock signal in turn; A flip-flop adapted to receive the readout data signal and the readout clock signal located on the readout path, and adapted to cause the readout data signal to be output after being sampled by the readout clock signal; A first multiplexer, a first input end of which is adapted to receive the readout data signal located on the readout path, and a second input end of which is adapted to receive the readout data signal output by the flip-flop; A second multiplexer, a first input end of which is adapted to receive the readout data signal output by the first-in-first-out subcircuit, a second input end of which is adapted to receive the readout data signal output by the first multiplexer, and an output end of which is adapted to output a corresponding readout data signal to the chip; Wherein, the first multiplexer and the second multiplexer are both adapted to select the readout data signal received by the first input end to output when being configured as a first value, and select the readout data signal received by the second input end to output when being configured as a second value; The first interface module includes a first output circuit connected with the first readout circuit, which is adapted to receive the readout data signal output by the first readout circuit and a data selection pulse signal aligned with the readout data signal, and output them to the second interface module through the 3D packaging connection line; the first interface module further includes a first input circuit adapted to receive the readout clock signal through the 3D packaging connection line and output it to the first readout circuit; The second interface module includes a second input circuit and a second output circuit, the second input circuit is adapted to receive the readout data signal and a data selection pulse signal aligned with the readout data signal through the 3D packaging connection line, and output them to the second readout circuit; the second output circuit is adapted to receive the readout clock signal output by the chip and output it to the first interface module through the 3D packaging connection line.

2. The integrated circuit of claim 1, wherein, The first readout circuit further includes: a third multiplexer having a first input adapted to receive the readout clock signal on the readout path, a second input adapted to receive the data select pulse signal on the readout path, and an output adapted to output a corresponding one of the readout clock signal or the data select pulse signal to the chip; the third multiplexer being adapted to output the readout clock signal received at its first input when configured to a first value and to output the data select pulse signal received at its second input when configured to a second value.

3. The integrated circuit of any one of claims 1 or 2, wherein, the first value is 0 and the second value is 1.

4. The integrated circuit of any one of claims 1 or 2, wherein, the multiplexer is a two-way multiplexer.

5. The integrated circuit of claim 1, wherein, the second output circuit is further adapted to receive a readout control signal output by the chip and to output it to the first input circuit via the 3D package connection line, and the first input circuit is further adapted to output the readout control signal to the memory to cause the memory to output the readout data signal and the data select pulse signal to the first readout circuit based on the readout control signal.

6. The integrated circuit of claim 1, wherein, the second output circuit is further adapted to receive a write data signal and a write clock signal output by the chip on a write path and to output them to the first input circuit via the 3D package connection line; the first interface module further comprises a write circuit coupled to the first input circuit and adapted to receive the write data signal and the write clock signal and to cause the write data signal to be output to the memory after being sampled by the write clock signal.

7. The integrated circuit of claim 6, wherein, the second output circuit is further adapted to receive a write control signal output by the chip on a write path and to output it to the first input circuit via the 3D package connection line; the first input circuit is further adapted to output the write control signal to the memory to cause the memory to write the write data signal output by the write circuit into its array based on the write control signal.

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