Multi-resistance-state nonvolatile memory device and boolean logic implementation method thereof

Abstract

The application relates to a multi-resistance-state nonvolatile memory device and a Boolean logic implementation method thereof. The multi-resistance-state nonvolatile memory device comprises a multi-resistance-state storage unit, a gating unit, a word line and a bit line. The gating unit comprises a drain end, a source end and a gate end. The gate end of the gating unit is connected with the word line, and the source end is grounded. One end of the multi-resistance-state storage unit is connected with the drain end of the gating unit, and the other end is connected with the bit line. The bit line is used for inputting a control signal B to determine the execution of AND, OR and XOR logical operations of the multi-resistance-state storage unit. The word line is used for inputting a binary signal W to control the opening or closing of the gating unit. The application does not need to pre-configure the state of the multi-resistance-state storage unit, has the characteristics of multi-level input, parallel operation and cascade operation, and is expected to be used for the weight value update of a neural morphological device synapse and the implementation of in-memory computing of a high-throughput memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of in-memory computing of non-volatile memory, in particular to a multi-resistance state non-volatile memory device and a Boolean logic implementation method thereof. BACKGROUND

[0002] With the advent of the information age, the demand for mass data storage and processing capacity is growing. Under the traditional von Neumann structure, the information interaction bandwidth and operation speed between the processor and the memory greatly limit the further improvement of computing efficiency, and due to the uneven development of processor performance and memory performance, the bottleneck effect of memory performance will become more and more serious. Non-volatile memory has the characteristics of large storage capacity and fast operation speed, which is expected to break the existing storage architecture and solve the problem of "memory wall".

[0003] Phase change memory utilizes the large difference in resistance (3 orders of magnitude) and reflectivity (~30%) between crystalline and amorphous states of chalcogenide compounds to store information. The crystalline phase material has the characteristics of high reflectivity and low resistance value, while in the amorphous state it shows low reflectivity and high resistance value. The conversion between crystalline and amorphous states is generally completed by using the Joule heat of electrical pulses. Phase change memory has the characteristics of good miniaturization, three-dimensional stacking, multi-level storage, and compatibility with traditional CMOS process, and is considered to be the most potential next-generation non-volatile storage technology. Phase change memory is expected to be applied to storage class memory, filling the gap between memory and hard disk in storage capacity and operation speed, and ultimately breaking the traditional von Neumann architecture to form a new storage architecture. A phase change memory device generally consists of a phase change memory cell, a gating device, a word line, a bit line, a peripheral driving circuit, a sensitive amplification circuit and the like. By applying different signal pulses to the word line and the bit line, the phase change memory cell can be read and written. The storage principle of the phase change memory cell provides the phase change memory device with inherent computing capability, so that the same cell has the ability to compute and store data at the same time. The existing method is time-consuming, inefficient and complex, and the non-volatility and multi-resistance state of the device are not fully utilized. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a multi-resistance state non-volatile memory device and a Boolean logic implementation method thereof, which does not need to pre-configure the state of the multi-resistance state storage cell, has the characteristics of multi-level input, parallel operation and cascading operation, and is expected to be used for weight update of neural morphological device synapse and implementation of high-throughput in-memory computing of memory.

[0005] The technical scheme adopted by the present application to solve its technical problems is: a multi-resistance state nonvolatile memory device is provided, comprising a multi-resistance state storage unit, a gating unit, a word line and a bit line, the gating unit comprises a drain end, a source end and a gate end, the gate end of the gating unit is connected with the word line, and the source end is grounded, one end of the multi-resistance state storage unit is connected with the drain end of the gating unit, and the other end is connected with the bit line; the bit line is used for inputting a control signal B to determine that the multi-resistance state storage unit performs AND, OR or XOR logical operation, and the word line is used for inputting a binary signal W to control the opening or closing of the gating unit.

[0006] The multi-resistance state storage unit comprises at least four resistance states, and each resistance state corresponds to a different binary state (X i ,Y i ) of the multi-resistance state storage unit.

[0007] The number of the multi-resistance state storage units is several, and the multi-resistance state storage units share one bit line, each multi-resistance state storage unit is connected with a gating unit, and each gating unit is connected with a different word line.

[0008] The multi-resistance state storage unit is a phase change memory or a resistive random access memory.

[0009] The gating unit is a transistor.

[0010] The technical scheme adopted by the present application to solve its technical problems is: a Boolean logic implementation method of the multi-resistance state nonvolatile memory device, comprising:

[0011] When the input binary signal is W and the control signal B is B HR , the multi-resistance state storage unit performs AND operation on its binary state (X i ,Y i ) and the binary signal W; wherein the control signal B HR is used for setting the multi-resistance state storage unit to the highest resistance state.

[0012] When the input binary signal is W and the control signal B is B HS , the multi-resistance state storage unit performs OR operation on its binary state (X i ,Y i ) and the binary signal W; wherein the control signal B HS is used for setting the multi-resistance state storage unit to the lowest resistance state.

[0013] When the input binary signal is W and the control signal B is signal B LR or B LS , the multi-resistance state storage unit performs XOR operation on its binary state (X i ,Y i ); wherein the control signal B iand a binary signal W; wherein the control signal B LS for converting the multi-resistance state memory cell to an adjacent low resistance state, the control signal B LR for converting the multi-resistance state memory cell to an adjacent high resistance state;

[0014] storing the result of the and, or, or xor operation in the multi-resistance state memory cell.

[0015] when the multi-resistance state memory cell is in the lowest resistance state, the control signal B HS or B LS does not change the resistance state of the multi-resistance state memory cell.

[0016] when the multi-resistance state memory cell is in the highest resistance state, the control signal B HR or B LR does not change the resistance state of the multi-resistance state memory cell.

[0017] when the multi-resistance state memory cell is in the lowest resistance state, no xor operation is performed.

[0018] when the gating unit is closed, the resistance state of the multi-resistance state memory cell does not change.

[0019] Advantages

[0020] Compared with the prior art, the present application has the following advantages and positive effects: the present application does not need to pre-configure the state of the multi-resistance state memory cell and directly performs operation in the multi-resistance state memory cell; the present application does not need to additionally design a peripheral logic circuit for calculation, can greatly save the transmission bandwidth between the processor and the memory, and improves the computer processing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a multi-resistance non-volatile memory device structure schematic diagram of an embodiment of the present application;

[0022] Fig. 2(a) is a truth table diagram corresponding to an and logic operation of a multi-resistance non-volatile memory of an embodiment of the present application;

[0023] Fig. 2(b) is a truth table diagram corresponding to an or logic operation of a multi-resistance non-volatile memory of an embodiment of the present application;

[0024] Fig. 2(c) is a truth table diagram corresponding to an xor logic operation of a multi-resistance non-volatile memory of an embodiment of the present application;

[0025] Fig. 3(a) is a schematic diagram of an and logic operation of a multi-resistance non-volatile memory of an embodiment of the present application;

[0026] Figure 3(b) is a schematic diagram of an OR logic operation of the multi-resistive state non-volatile memory of the present application;

[0027] Figure 3(c) is a schematic diagram of an XOR logic operation of the multi-resistive state non-volatile memory of the present application;

[0028] Figure 4(a) is a schematic diagram of a multi-resistive state phase change memory implementing parallel XOR logic computation of the present application;

[0029] Figure 4(b) is a table of multi-resistive state phase change memory implementing parallel XOR logic computation of the present application;

[0030] Figure 5(a) is a schematic diagram of a multi-resistive state phase change memory implementing cascade AND logic computation of the present application;

[0031] Figure 5(b) is a schematic diagram of a multi-resistive state phase change memory implementing cascade AND and OR logic computation logic gate of the present application. DETAILED DESCRIPTION

[0032] The present application will be further described with reference to the following examples. It should be understood that these examples are intended to illustrate the application and are not intended to limit the scope of the application. Additionally, it is contemplated that various alterations and modifications of the present application will occur to others upon reading the teachings of the present application. It is therefore intended that the present application be construed as including all such alterations and modifications as fall within the scope of the appended claims.

[0033] Embodiments of the present application relate to a multi-resistive state non-volatile memory device, as shown in Figure 1 , the basic structure of the multi-resistive state non-volatile memory includes a non-volatile memory cell (i.e. multi-resistive state memory cell 1), a pass-gate cell 2, a word line 4 and a bit line 3, the pass-gate cell 2 includes a drain, a source and a gate, the gate of the pass-gate cell 2 is connected to the word line 4 and the source is connected to ground, one end of the multi-resistive state memory cell 1 is connected to the drain of the pass-gate cell 2 and the other end is connected to the bit line 3. The bit line 3 is used to input a control signal B to determine the multi-resistive state memory cell 1 to perform AND, OR or XOR logic operation (i.e. the bit line can change the resistance state of the multi-resistive state memory cell 1 by electrical pulse), the word line 4 is used to input a binary signal W to control the opening or closing of the pass-gate cell 2. The resistance state of the multi-resistive state memory cell 1 of the present embodiment is set to 4, each resistance state corresponds to a different binary state (X i ,Y i ) of the multi-resistive state memory cell 1: the highest resistance state corresponds to (0,0), the second highest resistance state corresponds to (0,1), the second lowest resistance state corresponds to (1,0) and the lowest resistance state corresponds to (1,1), or vice versa.

[0034] Furthermore, the gating unit 2 typically uses a transistor to control access to the multi-resistive state memory cell 1. Its gate terminal is connected to the word line 4, and its source terminal is grounded. By inputting a binary signal W through the word line 4, the transistor (i.e., the gating unit 2) can be turned on or off.

[0035] Furthermore, the multi-resistance state storage unit 1 is a phase-change memory or a resistive switching memory.

[0036] This embodiment also provides a Boolean logic implementation method for the above-mentioned multi-resistive non-volatile memory device. The Boolean logic operation of the multi-resistive non-volatile memory will be described in detail below with reference to Figures 2, 3, 4, and 5:

[0037] The Boolean logic implementation method of the multi-resistance non-volatile memory in this embodiment is related to the control signal B input to bit line 3 and the resistance state (X) of the multi-resistance storage cell 1. i ,Y i (i.e., binary state), related to the binary signal W input to word line 4: as shown in Figure 2(a), when the control signal B is B HR At that time, multi-resistive state memory cell 1 performs an AND operation, and the logical expression is: As shown in Figure 2(b), when the control signal B is B HS When the multi-resistive state memory cell 1 performs an OR operation, the logical expression is X. i+1 =W+X i Y i+1 =W+Y i As shown in Figure 2(c), when the control signal B is signal B... LR Or B LS At that time, the multi-resistive state memory cell 1 implements the XOR operation, and the logical expression is: The result of Boolean logic operations is non-volatilely stored in the resistance state Y of multi-resistance state memory cell 1. i+1 In the middle, the next operation can be performed or the output can be directly output through the read circuit.

[0038] Furthermore, when the multi-resistance storage cell is in its lowest resistance state, the control signal B... HS Or B LS The resistance state of the multi-resistance memory cell remains unchanged; when the multi-resistance memory cell is in its highest resistance state, the control signal B... HR Or B LR The resistance state of the multi-resistance storage cell remains unchanged.

[0039] Implementation Method 1: Taking a multi-resistance phase-change memory as an example, a Boolean logic method for multi-resistance non-volatile memory devices is implemented.

[0040] like Figure 1As shown, the multi-resistivity phase-change memory consists of a phase-change memory cell and a transistor. In Embodiment 1, the highest resistance state of the multi-resistivity memory cell 1 corresponds to (0,0), the second highest resistance state corresponds to (0,1), the second lowest resistance state corresponds to (1,0), and the lowest resistance state corresponds to (1,1). When the binary input signal W on word line 4 is high, the transistor (i.e., the gating unit 2) is turned on; when the binary input signal W on word line 4 is low, the transistor (i.e., the gating unit 2) is turned off. Here, the high level of the input binary signal W is recorded as "1", and the low level is recorded as "0".

[0041] As shown in Figure 3(a), when performing multi-resistance phase-change memory and logic calculations, the control signal B is input to B. HR The word line 4 inputs a binary signal W, and the initial state of the multi-resistive state storage cell 1 is (X). i ,Y i After calculation, the state of multi-resistive state memory cell 1 is (X). i+1 ,Y i+1 From the truth table relation, we can obtain that... Implementation and operation of multi-resistive state memory cell 1.

[0042] As shown in Figure 3(b), when performing multi-resistance phase-change memory and logic calculations, the control signal B is input to B. HS The word line 4 inputs a binary signal W, and the initial state of the multi-resistive state storage cell 1 is (X). i ,Y i After calculation, the state of multi-resistive state memory cell 1 is (X). i+1 ,Y i+1 From the truth table relation, we can obtain that X i+1 =W+X i Y i+1 =W+Y i The multi-resistive state memory cell 1 implements or operates.

[0043] As shown in Figure 3(c), when performing XOR logic calculations in a multi-resistance phase-change memory, the control signal B is input to B. LS Or B LR The word line 4 inputs a binary signal W, and the initial state of the multi-resistive state storage cell 1 is (X). i ,Y i Before the XOR operation, the resistance state of the multi-resistance state storage cell 1 is read in advance. When the control signal B is input to B... LS If the value is (1,1), an operation failure signal is returned; when control signal B is input to B... LR If the value is (0,0), an operation failure signal is returned. After calculation, the state of multi-resistive state memory cell 1 is (X... i+1 ,Y i+1 From the truth table relation, we can obtain that... The multi-resistive state memory cell 1 implements the XOR operation.

[0044] Embodiment two: taking the implementation of XOR logic function in multi-resistance state phase change memory array as an example, the embodiment can realize the function of parallel calculation of multiple multi-resistance state storage units.

[0045] As shown in Fig. 4(a), three multi-resistance state storage units 1 (first multi-resistance state storage unit, second multi-resistance state storage unit, third multi-resistance state storage unit) are controlled by a bit line 3, the bit line 3 inputs a control signal B=B LS ; three multi-resistance state storage units 1 input signals W1, W2, W3 respectively; the states of three multi-resistance state storage units 1 are respectively denoted as (X i , Y i ), (A i , B i ), (C i , D i ), in the embodiment, the highest resistance state of multi-resistance state phase change memory corresponds to (0, 0), the second highest resistance state corresponds to (0, 1), the second lowest resistance state corresponds to (1, 0), and the lowest resistance state corresponds to (1, 1). The first multi-resistance state storage unit is in the highest resistance state, denoted as (0, 0); the second multi-resistance state storage unit is in the second highest resistance state, denoted as (0, 1); and the third multi-resistance state storage unit is in the second lowest resistance state, denoted as (0, 1).

[0046] As shown in Fig. 4(b), after inputting control signal B=B LS and binary signals W1 (1), W2 (0), W3 (1), the states of multi-resistance state storage units 1 are changed to (0, 1), (0, 1), (1, 0) respectively, and the logic operation formula is The XOR operation function is realized in parallel, and the states of multi-resistance state storage units do not need to be pre-configured.

[0047] The principle of Fig. 4(b) is that both AND and OR operations need to calculate two binary bits, but XOR operation only needs to consider the second bit of two binary bits, and the control signal B=B LS , and the Boolean logic operation process needs to consider the condition of "adjacent lower resistance state" (if B=B LR , the condition of "adjacent higher resistance state" needs to be considered): (1) the first multi-resistance state storage unit (X i , Y i ) corresponds to (0, 0), and the input signal W1 is 1, according to Y i+1 is 1, and considering that the adjacent low resistance state of (0, 0) is (0, 1), X i →X i+1 still remains 0; (2) the second multi-resistance state storage unit (A i , B i) and the input signal W2 is 0, according to B i+1 is 1, and since the input signal W2 is 0, A i → A i+1 does not need to be changed; (3) the third multi-resistance state memory unit (C i ,D i ) corresponds to (0, 1), and the input signal W3 is 1, according to D i+1 is 0, and considering that the adjacent low resistance state of (0, 1) is (1, 0), C i → C i+1 is to be changed to 1.

[0048] Embodiment three: taking a multi-resistance state phase change memory array as an example, the embodiment can realize the function of logic unit cascade calculation.

[0049] As shown in Fig. 5(a), one end of the multi-resistance state memory unit 1 is connected with a bit line, the bit line first inputs a control signal B=B HR , and then inputs a control signal B=B HS ; the drain end of the gating unit 2 is connected with the other end of the multi-resistance state memory unit 1, the gate end is connected with a word line 4, the word line 4 inputs a binary signal W1 when the control signal B=B HR is input, the word line 4 inputs a binary signal W2 when the control signal B=B HS is input, and the source end is grounded; the state of the multi-resistance state memory unit 1 is recorded as (X i ,Y i ).

[0050] As shown in Fig. 5(b), the expression of the logic unit of Fig. 5(a) is: The expression form of the basic circuit of the logic gate is an AND gate and an OR gate in series.

[0051] As can be seen from the above embodiment, the core feature of the present application is that, compared with the Boolean logic operation method of the traditional non-volatile memory, the multi-resistance state memory unit does not need to be initialized in advance, and the storage data in the multi-resistance state memory unit can be directly operated, which effectively shortens the logic operation time and the complexity of the design of the in-memory computing chip.

Claims

1. A multi-resistance state nonvolatile memory device, characterized by, The multi-resistance state storage unit, a gating unit, a word line and a bit line are included, the gating unit includes a drain end, a source end and a gate end, the gate end of the gating unit is connected with the word line, and the source end is grounded, one end of the multi-resistance state storage unit is connected with the drain end of the gating unit, and the other end is connected with the bit line; The multi-resistance state memory unit includes at least four resistance states, each of which corresponds to a different binary state (X i ,Y i ) of the multi-resistance state memory unit; the word line is used to input a binary signal W to control the opening or closing of the gating unit; and the bit line is used to input a control signal B to determine the binary state of the multi-resistance state memory unit and perform AND, OR or XOR logical operations with the binary signal W.

2. The multi-resistance state nonvolatile memory device of claim 1, wherein, The number of the multi-resistance state storage units is several, and the multi-resistance state storage units share one bit line, each multi-resistance state storage unit is connected with a gating unit, and each gating unit is connected with a different word line.

3. The multi-resistance state nonvolatile memory device of claim 1, wherein, The multi-resistance state storage unit is a phase change memory or a resistive random access memory.

4. The multi-resistance state nonvolatile memory device of claim 1, wherein, The gating unit is a transistor.

5. A method for implementing a multi-resistance state nonvolatile memory device as claimed in any one of claims 1 to 4 in Boolean logic, characterized by, The multi-resistance state storage unit is connected with a word line and a bit line. When the input binary signal is W, and the control signal B is B HR , the multi-resistance state storage unit performs an AND operation on its binary state (X i , Y i ) and the binary signal W; wherein the control signal B HR is used to place the multi-resistance state storage unit in the highest resistance state; When the input binary signal is W, and the control signal B is B HS , the multi-resistance state storage unit will perform an OR operation on its binary state (X i , Y i ) and the binary signal W; wherein the control signal B HS is used to place the multi-resistance state storage unit in the lowest resistance state; When the input binary signal is W, and the control signal B is signal B LR or B LS , the multi-resistance state storage unit performs an exclusive or operation between the second bit Y i of the binary state (X i , Y i ) of itself and the binary signal W; wherein the control signal B LS is used to change the multi-resistance state storage unit to an adjacent low resistance state, and the control signal B LR is used to change the multi-resistance state storage unit to an adjacent high resistance state. The result of the AND, OR or XOR operation is stored in the multi-resistance state storage unit.

6. The method of claim 5, wherein the plurality of resistive states are implemented as Boolean logic operations. When the multi-resistance state storage unit is in the lowest resistance state, the control signal B HS or B LS does not change the resistance state of the multi-resistance state storage unit.

7. The method of claim 5, wherein the plurality of resistive states are represented by a plurality of logic states. When the multi-resistance state memory cell is in the highest resistance state, the control signal B HR or B LR does not change the resistance state of the multi-resistance state memory cell.

8. The method of claim 5, wherein the plurality of resistive states are implemented as Boolean logic operations. When the multi-resistance state storage unit is in the lowest resistance state, the XOR operation is not performed.

9. The method of claim 5, wherein the plurality of resistive states are implemented as Boolean logic operations. When the gating unit is closed, the resistance state of the multi-resistance state storage unit does not change.

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