Flash Memory Controller, Flash Memory Module, and Electronic Device

Abstract

The present invention discloses an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is used to access the flash memory module. When the flash memory controller sends a read command to the flash memory module to request data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller. The flash memory module of the present invention can output the multi-bit information of each memory cell to the flash memory controller in response to a read command, and the multi-bit information of each memory cell can indicate the threshold voltage or state of the memory cell, thereby improving the read efficiency.

Description

[0001] This application is a divisional application of a Chinese invention application with an application date of July 17, 2019, an application number of 201910647336.X, and an invention title of "Flash Memory Controller, Flash Memory Module, and Electronic Device". Technical Field

[0002] The present invention relates to access control of flash memory, and particularly to a method for access management of a flash memory module, a flash memory controller, and an electronic device. Background Art

[0003] In recent years, due to the continuous development of memory technologies, various portable or non-portable memory devices (for example, memory cards compliant with SD / MMC, CF, MS, XD, and UFS standards respectively; for another example, solid state drives (SSDs); for another example, embedded memory devices compliant with UFS and EMMC specifications respectively) have been widely implemented in many applications. Therefore, access control of the memory in these memory devices has become a quite popular topic.

[0004] In the case of commonly used NAND flash memory, it mainly includes two major categories of flash memory: single level cell (SLC) and multiple level cell (MLC). Each transistor regarded as a memory cell in the SLC flash memory has only two charge values, which are used to represent logical value 0 and logical value 1 respectively. In addition, the storage capacity of each transistor regarded as a memory cell in the MLC flash memory is fully utilized, and a higher voltage is used for driving to record at least two bits of information (such as 00, 01, 11, 10) in one transistor through different levels of voltage. Theoretically, the recording density of the MLC flash memory can reach at least twice that of the SLC flash memory, which is very good news for the related industries of NAND flash memory that once encountered bottlenecks in the development process.

[0005] Compared with the SLC flash memory, since the MLC flash memory is cheaper and can provide a larger capacity in a limited space, the MLC flash memory quickly becomes the mainstream adopted by memory devices on the market. However, problems caused by the instability of the MLC flash memory also emerge one by one. In order to ensure that the access control of the flash memory in the memory device complies with relevant specifications, the controller of the flash memory usually has certain management mechanisms to properly manage data access.

[0006] According to the prior art, memory devices with the above management mechanisms still have deficiencies. For example, when triple level cells (TLC) are applied to memory devices, problems such as an increase in bit error rate occur. Although traditional sensing schemes for reading data from triple level cell flash memories have been proposed to try to solve these problems, they are not effective for memory devices with quadruple level cell (QLC) flash memories. In particular, traditional sensing schemes are not good for the high-level per memory cell in quadruple level cell flash memories. Therefore, a novel method and related architecture are needed to enhance the overall performance without side effects or with fewer side effects. Summary of the Invention

[0007] An object of the present invention is to disclose a method for accessing management of a memory device, which can efficiently obtain sufficient information for decoding operations even under a high-density storage arrangement to solve the above problems.

[0008] According to an embodiment of the present invention, an electronic device is disclosed, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is used to access the flash memory module. During the operation of the electronic device, when the flash memory controller sends a read instruction to the flash memory module to request data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

[0009] According to another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is coupled to a flash memory module, the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages. The flash memory controller includes a memory and a microprocessor, wherein the memory is used to store a program code, and the microprocessor is used to execute the program code to access the flash memory module through a control logic circuit. During the operation of the flash memory controller, after the microprocessor sends a read instruction to the flash memory module to request data on at least one page, the control logic circuit receives the multi-bit information of each memory cell of the at least one page from the flash memory module, and the control logic circuit de-randomizes and decodes the multi-bit information of each memory cell of the at least one page.

[0010] According to another embodiment of the present invention, a flash memory module is disclosed. The flash memory module includes at least one flash memory chip. Each flash memory chip in the at least one flash memory chip includes at least one memory array, a plurality of sense amplifiers, and a peripheral circuit. The at least one memory array includes a plurality of blocks, each block includes a plurality of pages, and the plurality of sense amplifiers are used to read data from a plurality of memory cells in the at least one memory array. During the operation of the flash memory module, when the at least one flash memory chip receives a read command from a flash memory controller, the plurality of sense amplifiers use a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller through the peripheral circuit. Brief Description of the Drawings

[0011] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 Schematic diagram of a three-dimensional NAND flash memory according to an embodiment of the present invention.

[0013] Figure 3 Illustrated according to an embodiment of the present invention Figure 2 Certain partial structures of the three-dimensional NAND flash memory shown.

[0014] Figure 4 Illustrated according to an embodiment of the present invention Figure 2 Certain implementation details of one memory cell among a plurality of memory cells of the three-dimensional NAND flash memory shown.

[0015] Figure 5 Schematic diagram of multiple states (programming states) of one memory cell of a fourth-order cell block according to an embodiment of the present invention.

[0016] Figure 6 Schematic diagram of a flash memory chip according to an embodiment of the present invention.

[0017] Figure 7 Schematic diagram of a sense amplifier according to a first embodiment of the present invention.

[0018] Figure 8 According to an embodiment of the present invention Figure 7 Timing diagram of certain signals of the sense amplifier shown.

[0019] Figure 9 Schematic diagram of a counter and a mapping circuit according to an embodiment of the present invention.

[0020] Figure 10 Schematic diagram of states S0 to S15 and corresponding most significant bit and multiple least significant bits according to an embodiment of the present invention.

[0021] Figure 11 Timing diagram of transfer read instruction and most significant bit / least significant bit according to an embodiment of the present invention.

[0022] Figure 12 Schematic diagram of a sense amplifier according to a second embodiment of the present invention.

[0023] Figure 13 According to an embodiment of the present invention Figure 12 Timing diagram of certain signals of the sense amplifier shown.

[0024] Among them, the reference numerals are explained as follows:

[0025] 10 Electronic device

[0026] 50 Master device

[0027] 52 Processor

[0028] 54 Power supply circuit

[0029] 100 Memory device

[0030] 110 Memory controller

[0031] 112 Microprocessor

[0032] 112C Program code

[0033] 112M Read-only memory

[0034] 114 Control logic circuit

[0035] 132 Encoder

[0036] 134 Decoder

[0037] 136 Randomizer

[0038] 138 Derandomizer

[0039] 116 Random access memory

[0040] 118 Transmission interface circuit

[0041] 120 Flash memory module

[0042] 122-1, 122-2, …, 122-N Flash memory chips

[0043] M(1, 1, 1), M(2, 1, 1), …, M(Nx, 1, 1),

[0044] M(1, 2, 1), …, M(Nx, 2, 1), …,

[0045] M(1, Ny, 1), …, M(Nx, Ny, 1),

[0046] M(1, 1, 2), M(2, 1, 2), …, M(Nx, 1, 2),

[0047] M(1, 2, 2), …, M(Nx, 2, 2), …,

[0048] M(1, Ny, 2), …, M(Nx, Ny, 2), …,

[0049] M(1, 1, Nz), …, M(Nx, 1, Nz),

[0050] M(1, 2, Nz), …, M(Nx, 2, Nz), …,

[0051] M(1, Ny, Nz), …, M(Nx, Ny, Nz),

[0052] Memory cells M(nx, ny, nz), MBLS(1, 1), …, MBLS(Nx, 1), MBLS(1, 2), …, MBLS(Nx, 2), …, MBLS(1, Ny), …, MBLS(Nx, Ny), upper selection circuits MSLS(1, 1), …, MSLS(Nx, 1), MSLS(1, 2), …, MSLS(Nx, 2), …, MSLS(1, Ny), …, MSLS(Nx, Ny), lower selection circuits BL(1), …, BL(Nx), bit lines WL(1, 1), WL(2, 1), …, WL(Ny, 1), WL(1, 2), WL(2, 2), …, WL(Ny, 2), …, WL(1, Nz), WL(2, Nz), …, WL(Ny, Nz), word lines BLS(1), BLS(2), …, BLS(Ny), upper selection lines SLS(1), SLS(2), …, SLS(Ny), lower selection lines SL(1), SL(2), …, SL(Ny), source lines PS2D(1), PS2D(2), …, PS2D(Ny), circuit modules S(1, 1), …, S(Nx, 1),

[0053] S(1, 2), …, S(Nx, 2), …,

[0054] S(1,Ny),…,S(Nx,Ny), secondary circuit module Mch, bar segment Md, upper side Ms of the bar segment, lower side Mfg of the bar segment, first tubular local structure Mcg, second tubular local structure VR1, VR2, VR3, VR4, VR5,

[0055] VR6, VR7, VR8, VR9, VR10,

[0056] VR11, VR12, VR13, VR14, VR15, read voltages S0, S1, S2, S3, S4, S5, S6, S7,

[0057] S8, S9, S10, S11, S12, S13, S14, S15, status

[0058] 600, flash memory chip

[0059] 610, 620, memory arrays

[0060] 612, 614, 622, 624, sense amplifiers

[0061] 632, 634, peripheral circuits

[0062] 700, 1200, sense amplifiers

[0063] 710, 1210, operational amplifiers

[0064] 712, 1212, voltage sources

[0065] 714, control circuit

[0066] 716, counter

[0067] 910, mapping circuit, 1214, digital - to - analog converter, Vout, output signal, Vsen, Vpre, VBL, voltages, VR, read voltage, CNT, count value, CBL, parasitic capacitance, SW1, switch, I_cell, current

[0068] T0, T1, T2, time

[0069] CNT_EN, DAC_EN, enable signals Detailed implementation mode

[0070] Figure 1Schematic diagram of an electronic device 10 according to an embodiment of the present invention. The electronic device 10 may include a main device 50 and a memory device 100. The main device 50 may include at least one processor (e.g., one or more processors), collectively referred to as the processor 52, and may further include a power supply circuit 54 coupled to the processor 52. The processor 52 may be used to control the operation of the main device 50, and the power supply circuit 54 may be used to supply power to the processor 52 and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the main device 50, and obtain the one or more driving voltages from the main device 50 as the power supply for the memory device 100. Examples of the host 50 may include (but are not limited to): multifunctional mobile phones, tablets, and personal computers such as desktop computers and laptop computers. Examples of the memory device 100 may include (but are not limited to): solid state drives (SSDs) and various types of embedded memory devices such as embedded memory devices compliant with the Peripheral Component Interconnect Express (PCIe) standard, and so on. According to this embodiment, the memory device 100 may include a flash memory controller 110, and may further include a flash memory module 120. The flash memory controller 110 is used to control the operation of the memory device 100 and access the flash memory module 120, and the flash memory module 120 is used to store information. The flash memory module 120 may include at least one flash memory chip such as a plurality of flash memory chips 122-1, 122-2, …, and 122-N, where "N" may represent a positive integer greater than one.

[0071] As Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a Read Only Memory (ROM) 112M, a control logic circuit 114, a Random Access Memory (RAM) 116, and a transmission interface circuit 118, where these components may be coupled to each other through a bus. The random access memory 116 is implemented as a Static Random Access Memory (SRAM), but the present invention is not limited thereto. The random access memory 116 can be used to provide internal storage space for the flash memory controller 110. For example, the random access memory 116 can be used as a buffer memory to buffer data. In addition, the read only memory 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. Note that in some examples, the program code 112C can be stored in the random access memory 116 or any form of memory. In addition, the control logic circuit 114 can be used to control the flash memory module 120, and may include an encoder 132, a decoder 134, a randomizer, a de-randomizer 138, and other circuits. The transmission interface circuit 118 may conform to a specific communication standard (such as the Serial Advanced Technology Attachment (SATA) standard, the Peripheral Component Interconnect (PCI) standard, the Express Peripheral Component Interconnect standard, the Universal Flash Storage (UFS) standard, etc.), and may communicate according to the specific communication standard. For example, for the memory device 100, it communicates with the host device 50, where the host device 50 may include a corresponding transmission interface circuit that conforms to the specific communication standard to communicate with the memory device 100 and the host device 50.

[0072] In this embodiment, the host device 50 may transmit a host command and a corresponding logical address to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host command and the logical address, translates the host command into a memory operation command (which may be simply referred to as an operation command), and then controls the flash memory module 120 with the operation command to read, write / program memory units (such as data pages) at certain physical addresses in the flash memory module 120, where the physical addresses correspond to the logical addresses. When the memory controller 110 performs an erase operation on any one of the flash memory chips 122-1, 122-2, …, and 122-N (the symbol "n" may represent any integer in the range [1, N]), at least one block among the multiple blocks of the flash memory chip 122-n is erased, where each of the multiple blocks may include multiple pages (such as data pages), and an access operation (such as reading or writing) may be performed on one or more pages.

[0073] Figure 2 FIG. is a schematic diagram of a three-dimensional (3D) NAND flash memory according to an embodiment of the present invention. For example, any memory component in at least one of the above-mentioned flash memory chips 122-1, 122-2, …, and 122-N may be implemented based on Figure 2 the three-dimensional NAND flash memory shown, but the present invention is not limited thereto.

[0074] According to this embodiment, the three-dimensional NAND flash memory may include a plurality of memory cells arranged in a three-dimensional architecture, such as (Nx*Ny*Nz) memory cells {{M(1,1,1),…,M(Nx,1,1)},{M(1,2,1),…,M(Nx,2,1)},…,{M(1,Ny,1),…,M(Nx,Ny,1)}}, {{M(1,1,2),…,M(Nx,1,2)},{M(1,2,2),…,M(Nx,2,2)},…,{M(1,Ny,2),…,M(Nx,Ny,2)}}, …, and {{M(1,1,Nz),…,M(Nx,1,Nz)},{M(1,2,Nz),…,M(Nx,2,Nz)},…,{M(1,Ny,Nz),…,M(Nx,Ny,Nz)}} respectively arranged in Nz layers along the vertical Z-axis and aligned in three directions corresponding to the X-axis, Y-axis, and Z-axis. Additionally, it may further include a plurality of selector circuits for selection control, such as (Nx*Ny) upper selector circuits {MBLS(1,1),…,MBLS(Nx,1)}, {MBLS(1,2),…,MBLS(Nx,2)}, …, and {MBLS(1,Ny),…,MBLS(Nx,Ny)} arranged in an upper layer above the Nz layer, and (Nx*Ny) lower selector circuits {MSLS(1,1),…,MSLS(Nx,1)}, {MSLS(1,2),…,MSLS(Nx,2)}, …, and {MSLS(1,Ny),…,MSLS(Nx,Ny)} arranged in a lower layer below the Nz layer. Furthermore, the three-dimensional NAND flash memory may include a plurality of bit lines and a plurality of word lines for access control, such as Nx bit lines BL(1), …, and BL(Nx) arranged in a top layer above the upper layer, and (Ny*Nz) word lines {WL(1,1),WL(2,1),…,WL(Ny,1)}, {WL(1,2),WL(2,2),…,WL(Ny,2)}, …, and {WL(1,Nz),WL(2,Nz),…,WL(Ny,Nz)} respectively arranged in the Nz layer.In addition, the three-dimensional NAND flash memory may include a plurality of selection lines for selection control, such as Ny upper selection lines BLS(1), BLS(2),..., and BLS(Ny) arranged in the upper layer, and Ny lower selection lines SLS(1), SLS(2),..., and SLS(Ny) arranged in the lower layer, and may further include a plurality of source lines for providing a plurality of reference levels, such as Ny source lines SL(1), SL(2),..., and SL(Ny) arranged in a bottom layer below the lower layer.

[0075] Such as Figure 2As shown, the three-dimensional NAND flash memory can be divided into Ny circuit modules PS2D(1), PS2D(2), …, and PS2D(Ny) distributed along the Y-axis. For ease of understanding, the circuit modules PS2D(1), PS2D(2), …, and PS2D(Ny) may have some electrical characteristics similar to a planar NAND flash memory (whose memory cells are arranged in a single layer), and thus can be regarded as multiple virtual two-dimensional (pseudo-2D) circuit modules respectively, but the present invention is not limited thereto. Additionally, any one of the circuit modules PS2D(1), PS2D(2), …, and PS2D(Ny), such as PS2D(ny), may include Nx secondary circuit modules S(1,ny), …, and S(Nx,ny), where "ny" can represent any integer in the range [1, Ny]. For example, circuit module PS2D(1) may include Nx secondary circuit modules S(1,1), …, and S(Nx,1), circuit module PS2D(2) may include Nx secondary circuit modules S(1,2), …, and S(Nx,2), …, and circuit module PS2D(Ny) may include Nx secondary circuit modules S(1,Ny), …, and S(Nx,Ny). In circuit module PS2D(ny), any one of the secondary circuit modules S(1,ny), …, and S(Nx,ny), such as S(nx,ny), may include Nz memory cells M(nx,ny,1), M(nx,ny,2), …, and M(nx,ny,Nz), and may include a set of selector circuits corresponding to the memory cells M(nx,ny,1), M(nx,ny,2), …, and M(nx,ny,Nz), such as an upper selector circuit MBLS(nx,ny) and a lower selector circuit MSLS(nx,ny), where "nx" can represent any integer in the range [1, Nx]. The upper selector circuit MBLS(nx,ny), the lower selector circuit MSLS(nx,ny), and the memory cells M(nx,ny,1), M(nx,ny,2), …, and M(nx,ny,Nz) can be implemented by transistors. For example, the upper selector circuit and the lower selector circuit MSLS(nx,ny) can be implemented by ordinary transistors without any floating gate, and any one of the memory cells M(nx,ny,1), M(nx,ny,2), …, and M(nx,ny,Nz), such as M(nx,ny,nz), can be implemented by a floating gate transistor, where "nz" can represent any integer in the range [1, Nz], but the present invention is not limited thereto.In addition, the upper selector circuits MBLS(1,ny), …, and MBLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signals on the corresponding selection line BLS(ny), and the lower selector circuits MSLS(1,ny), …, and MSLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signals on the corresponding selection line SLS(ny).

[0076] Figure 3 Shown according to an embodiment of the present invention Figure 2 Some local structures of the three-dimensional NAND flash memory shown. The three-dimensional NAND flash memory can be designed to have a plurality of rod-shaped local structures such as Figure 3 The rod-shaped local structures shown, and the plurality of rod-shaped local structures can be respectively arranged to pass through the secondary circuit modules {S(1,1), …, S(Nx,1)}, {S(1,2), …, S(Nx,2)}, …, and {S(1,Ny), …, S(Nx,Ny)}. For ease of understanding, the plurality of rod-shaped local structures can be respectively regarded as Figure 2 The channels of the relevant transistors of the secondary circuit modules {S(1,1), …, S(Nx,1)}, {S(1,2), …, S(Nx,2)}, …, and {S(1,Ny), …, S(Nx,Ny)} in the architecture shown, such as the channels of the ordinary transistors for implementing the upper selector circuit MBLS(nx,ny) and the lower selector circuit MSLS(nx,ny), and the channels of the floating gate transistors for implementing the memory cell M(nx,ny,nz). According to some embodiments, the number of the plurality of rod-shaped local structures can be equal to the total number (Nx*Ny) of the secondary circuit modules {S(1,1), …, S(Nx,1)}, {S(1,2), …, S(Nx,2)}, …, and {S(1,Ny), …, S(Nx,Ny)}, but the present invention is not limited thereto. For example, the arrangement of the plurality of memory cells can be changed, and the number of the plurality of rod-shaped local structures can be changed correspondingly.

[0077] In addition, the three-dimensional NAND flash memory can be designed to have a plurality of pipe-shaped local structures, and the plurality of pipe-shaped local structures can be arranged to encircle the plurality of rod-shaped local structures to form each component of the secondary circuit modules {S(1,1), …, S(Nx,1)}, {S(1,2), …, S(Nx,2)}, …, and {S(1,Ny), …, S(Nx,Ny)}, especially to form Figure 2In the architecture shown, each control gate of the multiple memory cells, each floating gate, and each gate of the multiple selector circuits. Memory cells {{M(1,1,1),M(2,1,1),…},{M(1,1,2),M(2,1,2),…},…} and word lines {WL(1,1),WL(1,2),…} are illustrated in Figure 3 and Figure 3 the shown tubular local structure may indicate that there are certain additional local structures surrounding each of the multiple rod-shaped local structures, and details of these additional local structures will be further described in subsequent embodiments.

[0078] Figure 4 is illustrated according to an embodiment of the present invention Figure 2 certain implementation details of one of the multiple memory cells in the shown three-dimensional NAND flash memory. As Figure 4 shown, the memory cell M(nx,ny,nz) may include a part of one of the multiple rod-shaped local structures, such as a rod segment Mch in the rod-shaped local structure corresponding to the secondary circuit module S(nx,ny), and may further include certain tubular local structures having the same axis of symmetry. For example, the upper side Md and the lower side Ms of the rod segment Mch can be used as the drain and source of the floating gate transistor for implementing the memory cell M(nx,ny,nx), and a first tubular local structure Mfg and a second tubular local structure Mcg among these tubular local structures can be used as the floating gate and the control gate of this floating gate transistor. Other tubular local structures among these tubular local structures, such as the tubular local structure between the rod segment Mch and the first tubular local structure Mfg and the tubular local structure between the first tubular local structure Mfg and the second tubular local structure Mcg, can be implemented by one or more insulating materials.

[0079] According to certain embodiments, Figure 2 any selector circuit in the shown architecture of the multiple selector circuits can be implemented by modifying Figure 4 the shown architecture. For example, the upper side Md and the lower side Ms of the rod segment Mch can be used as the drain and source of a common transistor for implementing this selector circuit, and the second tubular local structure Mcg among these tubular local structures can be used as the gate of this common transistor, where the first tubular local structure Mfg should be removed from the one or more insulating materials. Therefore, there will be only one tubular local structure between the rod segment Mch and the second tubular local structure Mcg, but the present invention is not limited thereto.

[0080] In the flash memory module 120, when a block of any one of the flash memory chips 122-1 to 122-N serves as a single-level cell block, each of the multiple physical pages in the block corresponds to one logical page, that is, each of the multiple memory cells of the page is configured to store only one bit, and one physical page may include all transistors controlled by a word line (for example, the memory cells M(1,1,Nz) to M(Nx,1,Nz) corresponding to the word line WL(1,Nz) form a physical page). When a block of any one of the flash memory chips 122-1 to 122-N serves as a multi-level cell block, each of the multiple physical pages in the block corresponds to two logical pages, that is, each of the multiple memory cells of the page is configured to store two bits. When a block of any one of the flash memory chips 122-1 to 122-N serves as a three-level cell block, each of the multiple physical pages in the block corresponds to three logical pages, that is, each of the multiple memory cells of the page is configured to store three bits. When a block of any one of the flash memory chips 122-1 to 122-N serves as a four-level cell block, each of the multiple physical pages in the block corresponds to four logical pages, that is, each of the multiple memory cells of the page is configured to store four bits.

[0081] Figure 5 FIG. is a schematic diagram of multiple states (programming states) of a memory cell of the four-level cell block according to an embodiment of the present invention. As Figure 5 shown, each memory cell can have sixteen states, and each state represents a different combination of four bits (named top bit, upper bit, middle bit, and lower bit respectively). In Figure 5In the illustrated embodiment, when the memory cell is programmed to have state S0, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 1, 1, 1); when the memory cell is programmed to have state S1, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 1, 1, 0); when the memory cell is programmed to have state S2, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 0, 1, 0); when the memory cell is programmed to have state S3, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 0, 0, 0); when the memory cell is programmed to have state S4, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 0, 0, 1); when the memory cell is programmed to have state S5, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 0, 0, 1); when the memory cell is programmed to have state S6, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 0, 0, 0); when the memory cell is programmed to have state S7, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 0, 1, 0); when the memory cell is programmed to have state S8, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 1, 1, 0); when the memory cell is programmed to have state S9, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 1, 0, 0); when the memory cell is programmed to have state S10, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 1, 0, 0); when the memory cell is programmed to have state S11, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 1, 0, 1); when the memory cell is programmed to have state S12, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 1, 0, 1); when the memory cell is programmed to have state S13, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 1, 1, 1); when the memory cell is programmed to have state S14, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (0, 0, 1, 1); and when the memory cell is programmed to have state S15, the top bit, upper bit, middle bit, and lower bit stored in the memory cell are (1, 0, 1, 1).

[0082] In the prior art, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR5, VR10, VR12, and VR15 to read the memory cell. If the memory cell is conductive when the read voltage VR5 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR5 is applied and the memory cell is conductive when the read voltage VR10 is applied, the top bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR10 is applied and the memory cell is conductive when the read voltage VR12 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR12 is applied and the memory cell is conductive when the read voltage VR15 is applied, the top bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR15 is applied, the top bit is determined to be "1". When the upper bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply three read voltages VR2, VR8, and VR14 to read the memory cell. If the memory cell is conductive when the read voltage VR2 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR2 is applied and the memory cell is conductive when the read voltage VR8 is applied, the upper bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR8 is applied and the memory cell is conductive when the read voltage VR14 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR14 is applied, the upper bit is determined to be "0". When the middle bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR3, VR7, VR9, and VR13 to read the memory cell. If the memory cell is conductive when the read voltage VR3 is applied, the middle bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR3 is applied and the memory cell is conductive when the read voltage VR7 is applied, the middle bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR7 is applied and the memory cell is conductive when the read voltage VR9 is applied, the middle bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR9 is applied and the memory cell is conductive when the read voltage VR13 is applied, the middle bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR13 is applied, the middle bit is determined to be "1".When the lower bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR1, VR4, VR6, and VR11 to read the memory cell. If the memory cell is conductive when the read voltage VR1 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR1 is applied and the memory cell is conductive when the read voltage VR4 is applied, the lower bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR4 is applied and the memory cell is conductive when the read voltage VR6 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR6 is applied and the memory cell is conductive when the read voltage VR11 is applied, the lower bit is determined to be "0"; and if the memory cell is non-conductive when the read voltage VR11 is applied, the lower bit is determined to be "1".

[0083] It should be noted that Figure 5 The Gray code shown is for illustrative purposes only and is not a limitation of the present invention. Any suitable Gray code can be used in the memory device 100, and the read voltages used to determine the top bit, upper bit, middle bit, and lower bit can be changed accordingly.

[0084] Bits read from the memory cells by using portions of the read voltages VR1 to VR15 can be regarded as a sign bit, and the sign bits obtained from a plurality of memory cells (for example, four thousand (4K) memory cells) are processed by a derandomizer 138 and error correction operations are performed by a decoder 134 to generate decoded data. However, since the state intervals of the memory cells in the multi-level cell block are very small, these states will have serious variations due to read interference, program interference, or data retention problems occurring in the flash memory module 120, and the error correction operations may fail. To solve this problem, additional read voltages are applied in the prior art to read the memory cells to obtain a plurality of soft bits, so as to increase the success rate of the error correction operations. For example, if the decoder 134 cannot decode the plurality of sign bits obtained from the plurality of memory cells, the flash memory controller 110 can control the flash memory module 120 to use additional read voltages to re-read the plurality of memory cells to obtain a first set of soft bits, and the decoder 134 uses a low-density parity-check code (LDPC) method to decode the plurality of sign bits with the first set of soft bits. For example, if the flash memory controller 110 attempts to read the top page of the block (i.e., the top bits of the plurality of memory cells), the flash memory controller 110 can control the flash memory module 120 to use additional read voltages (VR5-Δ), (VR10-Δ), (VR12-Δ), and (VR15-Δ) to obtain the first set of soft bits. If the decoder 134 still cannot decode, the flash memory controller 110 can control the flash memory module 120 to use additional read voltages (VR5+Δ), (VR10+Δ), (VR12+Δ), and (VR15+Δ) to re-read the plurality of memory cells to obtain a second set of soft bits, and the decoder 134 can use the low-density parity-check code method to decode the plurality of sign bits with the first set of soft bits and the second set of soft bits, and so on.

[0085] In view of the above situation, if the flash memory controller 110 needs to read data from a four-level cell block in the flash memory module 120, the flash memory controller 110 can read the plurality of memory cells and perform multiple decodings on the data to obtain soft bits to successfully decode the data. Each time the flash memory controller 110 reads the plurality of memory cells, a read instruction needs to be transmitted to the flash memory module 120, and the flash memory module 120 needs a read busy time to read the sign bits or soft bits. Therefore, the read mechanism in the prior art for high-density storage (such as a four-level cell block with three-dimensional NAND flash technology) is not efficient.

[0086] To solve the above problems, embodiments of the present invention disclose a read mechanism and a decoding method to efficiently access the flash memory module 120.

[0087] Figure 6 Schematic diagram of a flash memory chip 600 according to an embodiment of the present invention, where the flash memory chip 600 can be Figure 1 any one of the flash memory chips 122-1 to 122-N shown. As Figure 6 shown, the flash memory chip 600 includes two memory arrays 610 and 620, sense amplifiers 612, 614, 622 and 624, and peripheral circuits 632 and 634, where the memory arrays 610 and 620 include Figure 2 memory cells shown, and the sense amplifiers 612, 614, 622 and 624 are used to read data from the memory arrays 610 and 620, and the peripheral circuits 632 and 634 include pads, associated control circuits, and other interface circuits.

[0088] Figure 7 Schematic diagram of a sense amplifier 700 according to a first embodiment of the present invention. In Figure 7 it, the sense amplifier 700 includes an operational amplifier 710, a voltage source 712, a control circuit 714, a counter 716, and a switch SW1. In this embodiment, the sense amplifier 700 is used to read Figure 1 the memory cell M(1,1,Nz) corresponding to the bit line BL(1) and the word line WL(1,Nz) shown. When the memory cell M(1,1,Nz) is to be read, the control circuit 714 is used to generate a read voltage VR to Figure 1 the memory cell M(1,1,Nz) shown, and the upper selector circuit MBLS(1,1) and other memory cells M(1,1,1) to M(1,1,(Nz-1)) are controlled to be turned on.

[0089] Refer to both Figure 7 and Figure 8 , Figure 8Timing diagram of certain signals of the sense amplifier 700 according to an embodiment of the present invention. In the operation of the sense amplifier 700, the read voltage VR initially equals zero (i.e., the memory cell M(1,1,Nz) is disabled), the switch SW1 is controlled to connect the bit line BL(1) to the voltage source 712, and the voltage source 712 starts charging the parasitic capacitor CBL such that the voltage VBL at one terminal of the parasitic capacitor CBL equals the voltage Vpre provided by the voltage source 712 at time T0. Then, at time T1, the switch SW1 is controlled to connect the bit line BL(1) to the negative terminal of the operational amplifier 710, the control circuit 714 starts generating a ramp signal serving as the read voltage VR to the word line WL(1,Nz) to control the memory cell M(1,1,Nz), and the control circuit 714 generates an enable signal CNT_EN such that the counter 716 starts operating and provides an incremented count value CNT when the output signal Vout becomes high. For example, assume that the memory cell M(1,1,Nz) stores data corresponding to the state S8 (whose critical voltage is approximately 3V). When the read voltage VR starts rising from 0V to 3V, since the read voltage VR is not high enough to enable the memory cell M(1,1,Nz), the voltage VBL remains at the voltage Vpre, and since VBL / Vpre is greater than the reference voltage Vsen at the positive terminal of the operational amplifier 710, the output signal Vout generated by the operational amplifier 710 equals "0". When the read voltage VR is greater than the critical voltage of the memory cell M(1,1,Nz) at time T2, the memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge the parasitic capacitor CBL, and the voltage VBL will decrease. When the voltage VBL decreases and becomes lower than the reference voltage Vsen, the output signal Vout becomes "1" to trigger the counter 716 to output the current count value CNT. In Figure 8 In the illustrated embodiment, if the memory cell M(1,1,Nz) stores data corresponding to the state S8, the count value CNT is approximately "28".

[0090] In Figure 7 and Figure 8In the illustrated embodiment, since the slope of the read voltage VR, the discharge time, and the circuit delay are known, the count value CNT output by the counter 716 can accurately represent the critical voltage of the memory cell M(1,1,Nz). Additionally, if the counter 716 is a counter with a large resolution such as an eight-bit counter (i.e., the frequency used by the counter 716 has a high frequency), the count value CNT can represent the sign bit and the soft bit of the memory cell M(1,1,Nz). Therefore, compared with the prior art that uses multiple read operations to obtain the sign bit and the soft bit, the embodiment of the present invention can obtain the sign bit and the soft bit with a single read instruction, and the read efficiency can be greatly improved. Additionally, since the count value CNT output by the counter 716 can represent the critical voltage of the memory cell M(1,1,Nz), that is, the state of the memory cell M(1,1,Nz) can be obtained, the information carried by the count value CNT is much more than the sign bit obtained by the prior art (i.e., the sign bit in the prior art cannot accurately indicate which state the memory cell M(1,1,Nz) has). Specifically, if the top bit of the memory cell M(1,1,Nz) is to be read, the prior art uses the read voltages VR5, VR10, VR12, and VR15 to read the memory cell M(1,1,Nz), and the flash memory module only sends the top bit to the flash memory controller. For example, if the flash memory module of the prior art outputs the top bit "1" (i.e., the sign bit) to the flash memory controller, the flash memory controller only knows that the memory cell M(1,1,Nz) has one of the states S0 to S4, S10 to S11, and S15, but the flash memory controller cannot accurately know which state the memory cell M(1,1,Nz) has.

[0091] It should be noted that although Figure 8 shows using the ramp signal as the read voltage VR, the present invention is not limited thereto. In other embodiments, the control circuit 714 can apply read voltages VR with different voltage levels to the memory cell M(1,1,Nz) respectively (i.e., the read voltages VR with different voltage levels can be regarded as multiple read voltages respectively), each voltage level of the read voltage VR corresponds to a count value CNT, and the read voltage VR can have any other suitable design. In one embodiment, the number of voltage levels of the read voltage VR (or the number of read voltages) is equal to or greater than the number of states of the memory cell M(1,1,Nz).

[0092] In one embodiment, the sense amplifier 700 further includes Figure 9The mapping circuit 910 shown. The mapping circuit 910 is used to convert the count value into eight-bit information indicating the critical voltage or state of the memory cell M(1,1,Nz), where four bits are the most significant bits (MSB), and the other four bits are the least significant bits (LSB). For example, the count value "1" is mapped to the eight-bit information (0,0,0,0,0,0,0,0), the count value "2" is mapped to the eight-bit information (0,0,0,0,0,0,0,1), the count value "3" is mapped to the eight-bit information (0,0,0,0,0,0,1,0), …, the count value "255" is mapped to the eight-bit information (1,1,1,1,1,1,1,0), and the count value "256" is mapped to the eight-bit information (1,1,1,1,1,1,1,1). Figure 10 FIG. is a schematic diagram of states S0 to S15 and corresponding most significant bits and least significant bits according to an embodiment of the present invention. In Figure 10 the embodiment shown, the most significant bits are used to indicate the state of the memory cell M(1,1,Nz), that is, the most significant bits (0,0,0,0) represent the state S0, the most significant bits (0,0,0,1) represent the state S1, the most significant bits (0,0,1,0) represent the state S2, …, the most significant bits (1,1,1,0) represent the state S14, and the most significant bits (1,1,1,1) represent the state S15. In addition, the range defined by the most significant bits is further divided into sixteen sub-ranges represented by the least significant bits, and the least significant bits can act as the soft bits described above.

[0093] In one embodiment, the flash memory module 120 can transfer the most significant bits and the least significant bits to the flash memory controller 110 in response to the read instruction when only one read instruction is received. Refer to Figure 11, if the flash memory controller 110 desires to read data in a page (such as a logical page), the flash memory controller 110 transmits a read instruction to the flash memory module 120, and the flash memory module 120 uses the above mechanism to read the memory cells of the page to generate the most significant bit and the least significant bit for each memory cell. Assuming that the page includes a plurality of chunks (such as sixty-four chunks) and each chunk is an encoding / decoding unit, the flash memory module 120 can sequentially transmit the most significant bits of each memory cell in a first chunk, the most significant bits of each memory cell in a second chunk, …, and the most significant bits of each memory cell in a last chunk to the flash memory controller 110 for subsequent de-randomize operation and decoding operation. After the most significant bits of all the memory cells in the page have been transmitted to the flash memory controller 110, the flash memory module 120 starts to sequentially transmit the least significant bits of each memory cell in the first chunk, the least significant bits of each memory cell in the second chunk, …, and the least significant bits of each memory cell in the last chunk to the flash memory controller 110 for subsequent de-randomize operation and decoding operation.

[0094] In the above embodiment, if the decoder 134 of the flash memory controller 110 can successfully decode the data only by using the most significant bits of the plurality of memory cells of the page, the least significant bits of the plurality of memory cells may not be used for the decoding operation, or the flash memory controller 110 can notify the flash memory module 120 to stop transmitting the least significant bits.

[0095] In Figure 9 the illustrated embodiment, the mapping circuit 910 is disposed in the flash memory module 120, and the flash memory module 120 transmits the information output by the mapping circuit 910 to the flash memory controller 110. In another embodiment of the present invention, the mapping circuit 910 can be disposed in the control logic circuit 114 of the flash memory controller 110, and the flash memory module 120 transmits the count value CNT to the flash memory controller 110.

[0096] Figure 12 Schematic diagram of a sense amplifier 1200 according to a second embodiment of the present invention. In Figure 12 it, the sense amplifier 1200 includes an operational amplifier 1210, a voltage source 1212, a digital-to-analog converter 1214, and a switch SW1. In this embodiment, the sense amplifier 1200 is used to read Figure 1 the memory cell M(1,1,Nz) corresponding to the bit line BL(1) and the word line WL(1,Nz) shown in Figure 1The memory cell M(1,1,Nz) shown, while the other memory cells M(1,1,1) to M(1,1,(Nz - 1)) are controlled to be conductive.

[0097] Refer to Figure 12 as well as Figure 13 , Figure 13 is a timing diagram of certain signals of the sense amplifier 1200 according to an embodiment of the present invention. In the operation of the sense amplifier 1200, the digital - to - analog converter 1214 does not work initially and the read voltage VR is initially equal to zero (i.e., the memory cell M(1,1,Nz) is deactivated). The switch SW1 is controlled to connect the bit line BL(1) to the voltage source 1212, and the voltage source 1212 starts charging the parasitic capacitor CBL so that the voltage VBL at one terminal of the parasitic capacitor CBL is equal to the voltage Vpre provided by the voltage source 1212 at time T0. Then, at time T1, the switch SW1 is controlled to connect the bit line BL(1) to the negative terminal of the operational amplifier 1210, and the digital - to - analog converter 1214 starts generating a ramp signal as the read voltage VR to the word line WL(1,Nz) according to the enable signal DAC_EN to control the memory cell M(1,1,Nz). For example, assume that the memory cell M(1,1,Nz) stores data corresponding to state S8 (whose critical voltage is about 3V). When the read voltage VR starts to rise from 0V to 3V, since the read voltage VR is not high enough to enable the memory cell M(1,1,Nz), the voltage VBL remains at the voltage Vpre, and since VBL / Vpre is greater than the reference voltage Vsen at the positive terminal of the operational amplifier 1210, the output signal Vout generated by the operational amplifier 1210 is equal to "0". When the read voltage VR is greater than the critical voltage of the memory cell M(1,1,Nz) at time T2, the memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge the parasitic capacitor CBL, and the voltage VBL will decrease. When the voltage VBL decreases and becomes lower than the reference voltage Vsen, the output signal Vout becomes "1" to trigger the digital - to - analog converter 1214 to output a digital value corresponding to the current read voltage VR.

[0098] Note that although Figure 13 shows using the ramp signal as the read voltage VR, the present invention is not limited thereto. In other embodiments, the digital - to - analog converter 1214 can apply read voltages VR with different voltage levels to the memory cell M(1,1,Nz) respectively (i.e., read voltages VR with different voltage levels can be regarded as multiple read voltages respectively), and the read voltage VR can have any other suitable design. In one embodiment, the number of voltage levels of the read voltage VR (or the number of read voltages) is equal to or greater than the number of states of the memory cell M(1,1,Nz).

[0099] In Figure 12 the Figure 13 embodiment shown, the digital value output by the digital-to-analog converter 1214 can represent the critical voltage of the memory cell M(1,1,Nz) (i.e., the analog voltage corresponding to the digital value output by the digital-to-analog converter 1214 is very close to the critical voltage of the memory cell M(1,1,Nz)), so the digital value can be effectively used for subsequent decoding operations. Additionally, assuming that the digital-to-analog converter 1214 is an eight-bit digital-to-analog converter, the digital value may have Figure 10 the four most significant bits and four least significant bits shown, and the flash memory module 120 can directly transfer the digital value (i.e., the multiple most significant bits and multiple least significant bits) to the flash memory controller 110 with a read instruction. The timing diagram for transferring the read instruction and the multiple most significant bits / least significant bits can be referred to Figure 11 . Additionally, due to circuit delay and discharge time, the digital value output by the digital-to-analog converter 1214 can be slightly adjusted so that the adjusted digital value is closer to the critical voltage of the memory cell M(1,1,Nz).

[0100] The above embodiment takes a fourth-order cell block as an example. However, the above read mechanism can also be applied to third-order cell blocks, multi-order cell blocks, and single-order cell blocks. Those skilled in the art should be able to understand how to use the above steps to read the memory cells in third-order cell blocks, multi-order cell blocks, and single-order cell blocks, and other details will not be elaborated here.

[0101] In summary, in the flash memory controller and flash memory module of the present invention, the flash memory module can output the multi-bit information of each memory cell to the flash memory controller in response to a read instruction, and the multi-bit information of each memory cell can indicate the critical voltage or state of the memory cell. Therefore, the read efficiency can be greatly improved.

[0102] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electronic device, characterized in that, Comprising: A flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages; and A flash memory controller for accessing the flash memory module; Wherein when the flash memory controller sends a read command to the flash memory module to request data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller; Wherein the at least one page includes a plurality of chunks, the multi-bit information includes a plurality of most significant bits and a plurality of least significant bits, and the flash memory module sequentially transmits the plurality of most significant bits of each memory cell of the plurality of chunks to the flash memory controller; then, after all the plurality of most significant bits of each memory cell of the plurality of chunks are transmitted to the flash memory controller, the flash memory module sequentially transmits the plurality of least significant bits of each memory cell of the plurality of chunks to the flash memory controller.

2. The electronic device according to claim 1, wherein The flash memory module uses the plurality of read voltages to read each memory cell of the at least one page to obtain the multi-bit information of each memory cell according to the read command without any other read command.

3. The electronic device according to claim 1, wherein Each memory cell of the at least one page is used to store a plurality of bits, each memory cell has a plurality of states, the plurality of states are used to indicate different combinations of the plurality of bits, and the number of the plurality of read voltages is equal to or greater than the number of the plurality of states.

4. The electronic device according to claim 3, wherein The flash memory module uses a ramp signal as the plurality of read voltages to read each memory cell of the at least one page to obtain the multi-bit information of each memory cell.

5. The electronic device according to claim 3, wherein, The multi-bit information of each memory cell corresponds to one of the plurality of read voltages that causes the memory cell to start conducting.

6. The electronic device according to claim 5, wherein The at least one page is in a four-level cell block, and the multi-bit information of each memory cell includes at least four bits.

7. The electronic device according to claim 6, wherein The multi-bit information of each memory cell includes eight bits.

8. A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the flash memory controller is characterized by including: A memory for storing a program code; And A microprocessor for executing the program code to access the flash memory module through a control logic circuit; Wherein when the microprocessor sends a read command to the flash memory module to request data on at least one page, the control logic circuit receives the multi-bit information of each memory cell of the at least one page from the flash memory module, and the control logic circuit performs derandomization and decoding on the multi-bit information of each memory cell of the at least one page. Wherein the at least one page includes a plurality of chunks, the multi-bit information includes a plurality of most significant bits and a plurality of least significant bits, and the flash memory module sequentially transfers the plurality of most significant bits of each memory cell of the plurality of chunks to the flash memory controller; then, after all of the plurality of most significant bits of each memory cell of the plurality of chunks are transferred to the flash memory controller, the flash memory module sequentially transfers the plurality of least significant bits of each memory cell of the plurality of chunks to the flash memory controller.

9. The flash memory controller according to claim 8, wherein The multi-bit information of each memory cell of the at least one page from the flash memory module is obtained according to the read instruction without any other read instructions.

10. A flash memory module, characterized in that, Comprising: At least one flash memory chip, wherein each flash memory chip includes: At least one memory array, wherein the at least one memory array includes a plurality of blocks, and each block includes a plurality of pages; A plurality of sense amplifiers for reading data from a plurality of memory cells in the at least one memory array; and A peripheral circuit coupled between the plurality of sense amplifiers; Wherein when the at least one flash memory chip receives a read instruction from a flash memory controller, the plurality of sense amplifiers use a plurality of read voltages to read each memory cell of at least one page to obtain the multi-bit information of each memory cell, and the flash memory module transfers the multi-bit information of each memory cell of the at least one page to the flash memory controller through the peripheral circuit; Wherein the at least one page includes a plurality of chunks, the multi-bit information includes a plurality of most significant bits and a plurality of least significant bits, and the flash memory module sequentially transfers the plurality of most significant bits of each memory cell of the plurality of chunks to the flash memory controller; then, after all of the plurality of most significant bits of each memory cell of the plurality of chunks are transferred to the flash memory controller, the flash memory module sequentially transfers the plurality of least significant bits of each memory cell of the plurality of chunks to the flash memory controller.

11. The flash memory module according to claim 10, characterized in that, The flash memory module uses the plurality of read voltages to read each memory cell of the at least one page to obtain the multi-bit information of each memory cell according to the read instruction without any other read instructions.

12. The flash memory module according to claim 10, wherein, Each memory cell of the at least one page is used to store a plurality of bits, each memory cell has a plurality of states, the plurality of states are used to indicate different combinations of the plurality of bits, and the number of the plurality of read voltages is equal to or greater than the number of the plurality of states.

13. The flash memory module according to claim 12, wherein The flash memory module uses a ramp signal as the plurality of read voltages to read each memory cell of the at least one page to obtain the multi-bit information of each memory cell.

14. The flash memory module as claimed in claim 12, wherein, The multi-bit information of each memory cell corresponds to one of the plurality of read voltages that causes the memory cell to start conducting.

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