Split-gate memory cell

Abstract

A memory may include: a memory cell array having a plurality of serially connected split-gate memory cell strings, each of the plurality of serially connected split-gate memory cell strings including a main memory cell portion and an auxiliary memory cell portion; a plurality of main access lines, each connected to a control gate of the main memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings; and a plurality of auxiliary access lines, each connected to a control gate of the auxiliary memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 131,340, filed on December 29, 2020, which is hereby incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure generally relates to integrated circuits, and more specifically, in one or more embodiments, to devices comprising split-gate memory cells and methods of operating thereof. Background Technology

[0003] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0004] Flash memory has evolved into a popular source of non-volatile memory for a wide variety of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. By programming (often referred to as writing) the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0005] NAND flash memory is a common type of flash memory device, so named because of the logical form of its basic memory cell configuration. Typically, the memory cell array for NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., a source select transistor and a drain select transistor). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0006] During memory programming, memory cells can be programmed into memory cells commonly referred to as Single-Level Cells (SLCs). An SLC can use a single memory cell to represent a single digit (e.g., one bit) of data. For example, in an SLC, a Vt of 2.5V or higher can indicate a programmed memory cell (e.g., representing logic 0), while a Vt of -0.5V or lower can indicate an erased memory cell (e.g., representing logic 1). Such memories can achieve higher levels of storage capacity by incorporating Multi-Level Cells (MLCs), Three-Level Cells (TLCs), Four-Level Cells (QLCs), and combinations thereof, where memory cells have multiple levels that allow more bits of data to be stored in each memory cell. For example, an MLC can be configured to store two-digit data per memory cell represented by a range of four Vt, a TLC can be configured to store three-digit data per memory cell represented by a range of eight Vt, a QLC can be configured to store four-digit data per memory cell represented by a range of sixteen Vt, and so on.

[0007] Sensing (e.g., reading or verifying) the data state of a target memory cell typically involves responding to a specific voltage level applied to the control gate of the target memory cell, for example, detecting whether the target memory cell is activated by detecting whether a data line connected to the target memory cell experiences a voltage level change caused by current flowing through the memory cell. This typically involves applying a voltage level to the control gate of each of the remaining memory cells in a string of cascaded memory cells containing the target memory cell, the voltage level intended to activate each of these remaining memory cells regardless of their data state. Such a voltage level may be referred to as a pass voltage. However, some memory cells may be overprogrammed, for example, having a threshold voltage level higher than the desired voltage level, and may not be activated in response to a pass voltage applied to their control gate. This can lead to inaccurate determination of the data state of the target memory cell, where the target memory cell may be considered deactivated even if it has been activated. Summary of the Invention

[0008] In one aspect, this application provides a memory comprising: a memory cell array including a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings includes a main memory cell portion and an auxiliary memory cell portion, and wherein, for each split-gate memory cell in the plurality of serially connected split-gate memory cell strings, the main memory cell portion of the split-gate memory cell is configured to store data states accessible by a read operation during normal operation of the memory, and the data states of the auxiliary memory cell portion of the split-gate memory cell are configured to be inaccessible by the read operation during normal operation of the memory; a plurality of main access lines, wherein each of the plurality of main access lines is connected to a control gate of the main memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings; and a plurality of auxiliary access lines, wherein each of the plurality of auxiliary access lines is connected to a control gate of the auxiliary memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings.

[0009] In another aspect, this application further provides a memory comprising: a memory cell array including a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings includes a main memory cell portion and an auxiliary memory cell portion; a plurality of main access lines, wherein each of the plurality of main access lines is connected to a control gate of the main memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings; and a plurality of auxiliary access lines, wherein each of the plurality of auxiliary access lines is connected to each string in the plurality of serially connected split-gate memory cell strings. A control gate for the auxiliary memory cell portion of a corresponding split-gate memory cell in a string of split-gate memory cells; and a controller for accessing the memory cell array; wherein, during an erase operation on the plurality of strings of serially connected split-gate memory cells, the controller is configured such that the memory: actively biases each of the plurality of main access lines when an erase voltage is applied to each of the plurality of strings of serially connected split-gate memory cells; and electrically floats each of the plurality of auxiliary access lines when the erase voltage is applied to each of the plurality of strings of serially connected split-gate memory cells.

[0010] In another aspect, this application further provides a memory comprising: a memory cell array including a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings includes a main memory cell portion and an auxiliary memory cell portion; a plurality of main access lines, wherein each of the plurality of main access lines is connected to a control gate of the main memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings; a plurality of auxiliary access lines, wherein each of the plurality of auxiliary access lines is connected to a control gate of the auxiliary memory cell portion of a corresponding split-gate memory cell in each of the plurality of serially connected split-gate memory cell strings; and a controller for accessing the memory cell array; wherein, in accessing a selected split-gate memory cell in a particular serially connected split-gate memory cell string of the plurality of serially connected split-gate memory cell strings... During a read operation, the controller is configured such that the memory: applies a first voltage level to a selected main access line of the plurality of main access lines connected to the control gate of the main memory cell portion of the selected split-gate memory cell, wherein the first voltage level is configured to selectively activate the main memory cell portion depending on the data state of the main memory cell portion of the selected split-gate memory cell; applies a second voltage level to a selected auxiliary access line of the plurality of auxiliary access lines connected to the control gate of the auxiliary memory cell portion of the selected split-gate memory cell, wherein the second voltage level is configured to deactivate the auxiliary memory cell portion of the selected split-gate memory cell; and applies a third voltage level to a non-selected auxiliary access line of the plurality of auxiliary access lines connected to the control gate of the auxiliary memory cell portion of a non-selected split-gate memory cell in the read operation, wherein the third voltage level is configured to activate the auxiliary memory cell portion of the non-selected split-gate memory cell. Attached Figure Description

[0011] Figure 1 This is a simplified block diagram of a memory according to an embodiment, which communicates with a processor as part of an electronic system.

[0012] Figures 2A to 2C It can be used as a reference. Figure 1 A schematic diagram of a portion of the memory cell array used in the type of memory described.

[0013] Figure 3A This is a schematic diagram of a split-gate memory cell according to an embodiment.

[0014] Figures 3B to 3C This is a plan view of a split-gate memory cell according to an embodiment.

[0015] Figure 4A This is a perspective view of the array structure according to an embodiment.

[0016] Figure 4B According to the embodiments Figure 4A A planar diagram of the array structure.

[0017] Figure 5 This is a cross-sectional view of a portion of a split-gate memory cell array according to an embodiment.

[0018] Figure 6 It can be used as a reference. Figure 1 A schematic diagram of a portion of the memory cell array and string driver used in the described type of memory device.

[0019] Figures 7A to 7B This is a conceptual depiction of the threshold voltage distribution of multiple memory cells used in the embodiments.

[0020] Figure 8 A flowchart depicting a method for operating a memory according to an embodiment.

[0021] Figure 9 A flowchart depicting a method for operating a memory according to another embodiment. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments by means of description. Throughout the drawings, the same reference numerals describe substantially similar components. Other embodiments and structural, logical, and electrical changes may be utilized without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0023] For example, the term "semiconductor" as used herein may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0024] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0025] This paper recognizes that even when values ​​are presumably equal, the variability and accuracy of industrial processing and operation can still cause discrepancies with their expected values. These variability and accuracy will generally depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are presumably equal, then those values ​​are considered equal regardless of their resulting values.

[0026] The various embodiments disclosed herein include a memory with split-gate memory cells, each having a main memory cell portion and an auxiliary memory cell portion. Data can be written to the main memory cell portion during a programming operation in response to a write command and its associated data, and can be read from the main memory cell portion during a read operation in response to a read command for outputting the data. The auxiliary memory cell portion may not be accessible during normal operation of the memory and may store predetermined data, such as a predetermined threshold voltage range. For example, each auxiliary memory cell portion may have a threshold voltage within a predefined threshold voltage range. As used herein, a read operation that includes reading data from memory output is different from a verification operation, which is used during a programming or erasing operation to determine whether a memory cell has a predetermined data state and does not include outputting data from memory during normal operation.

[0027] Figure 1 A simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 communicating as part of a third device in the form of an electronic system with a second device in the form of a processor 130, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The processor 130, such as a controller external to the memory device 100, may be a memory controller or other external host device.

[0028] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. The memory cell array 104 includes strings of split-gate memory cells connected in series according to embodiments. Memory cells in a logical row are typically connected to the same access line (often referred to as a word line), while memory cells in a logical column are typically selectively connected to the same data line (often referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0029] exist Figure 1 In this example, row decoding circuitry 108 and column decoding circuitry 110 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 100 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to the memory device 100, as well as the output of data and status information from the memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch the address signal before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0030] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control them in response to an address. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

[0031] Control logic 116 may also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data accordingly. During programming operations (e.g., write operations), data may be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data may be latched from I / O control circuitry system 112 into cache register 118. During read operations, data may be transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; subsequently, new data may be transferred from data register 120 back to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1 (Not shown) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0032] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0033] For example, commands can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134, and the commands can then be written to command register 124. Addresses can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134, and the addresses can then be written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and the data can then be written to cache register 118. Data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0034] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0035] In addition, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0036] Figure 2A It can be, for example, part of memory cell array 104 in reference Figure 1This is a schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in a memory of the described type. The memory array 200A includes main access lines (e.g., main word lines) 2020 to 2023, secondary access lines (e.g., secondary word lines) 2030 to 2033, and data lines (e.g., bit lines) 2040 to 2043. The main access lines 2020 can be connected in a many-to-one relationship to... Figure 2A Global primary access lines not shown (e.g., global primary word lines). Secondary access lines 202 can be connected in a many-to-one relationship to... Figure 2A Global auxiliary access lines (e.g., global auxiliary word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity to form a p-well, or n-type conductivity to form an n-well, for example.

[0037] The memory array 200A can be arranged in rows (each row corresponds to a main access line 202 and a corresponding auxiliary access line 203) and columns (each column corresponds to a data line 204). Each column may contain a string of split-gate memory cells (e.g., split-gate nonvolatile memory cells) connected in series, and may be referred to as NAND string 206. NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216, and in Figure 2A An example may include a memory cell 208 for a NAND string 2060. 00 To 208 03 Memory cell 208 for NAND string 2061 10 To 208 13 Memory cell 208 for NAND string 2062 20 To 208 23 Or for memory cell 208 of NAND string 2063 30 To 208 33 Memory cell 208 can be represented and referred to as a split-gate memory cell. Memory cells 2080 to 208 N It may include memory cells specifically designed for storing data, and may further include other memory cells not specifically designed for storing data, such as dummy memory cells. Dummy memory cells are typically not accessible to the user of the memory, but are usually incorporated into the NAND string to gain well-known operational advantages.

[0038] Each memory cell 208 of the NAND string 206 may be connected in series between a select gate 210 (e.g., a field-effect transistor) of one of select gates 2100 to 2103 (e.g., which may be a source select transistor, commonly referred to as select gate source) and a select gate 212 (e.g., a field-effect transistor) of one of select gates 2120 to 2123 (e.g., which may be a drain select transistor, commonly referred to as select gate drain). Select gates 2100 to 2103 may be commonly connected to select line 214, such as a source select line or select gate source (SGS), and select gates 2120 to 2123 may be commonly connected to select line 215, such as a drain select line or select gate drain (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 may utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 may represent a plurality of select gates connected in series, wherein each select gate is configured in series to receive the same or independent control signals.

[0039] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 208 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 208 of the corresponding NAND string 2060. 00 Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0040] The drain of each select gate 212 can be connected to a data line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to a data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208 for the corresponding NAND string 206. For example, the source of select gate 2120 can be connected to a memory cell 208 for the corresponding NAND string 2060. 03 Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0041] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a substantially parallel plane. Alternatively, Figure 2AThe memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the data line 204, and the plane containing the data line is substantially parallel to the plane containing the common source 216.

[0042] A column of memory cells 208 may be one or more NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given main access line 202. A row of memory cells 208 may, but does not necessarily, contain all memory cells 208 commonly connected to a given main access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given main access line 202. For example, a memory cell 208 that is commonly connected to main access line 2023 and selectively connected to even-numbered data lines 204 (e.g., data lines 2040 and 2042) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while a memory cell 208 that is commonly connected to main access line 2023 and selectively connected to odd-numbered data lines 204 (e.g., data lines 2041 and 2043) can be another physical page of memory cell 208 (e.g., an odd-numbered memory cell). Other groups of memory cells 208 that are commonly connected to a given main access line 202 can also define physical pages of memory cells 208. For some memory devices, all memory cells that are commonly connected to a given main access line can be considered as physical pages of memory cells. A block of memory cells can contain those memory cells configured to be erased together, such as all memory cells connected to main access lines 2020 through 2023 (e.g., all NAND strings 206 sharing a common main access line 202). Unless explicitly specified, the reference to a memory cell page herein refers to a memory cell within a logical page of memory cells. Although the memory cell array 200A depicts four main access lines 202, four secondary access lines 203, four data lines 204, and four memory cells 208 in each NAND string 206, other smaller or larger numbers of such elements may be used. Similarly, while the number of memory cells 208 in the NAND string 206 will generally be equal to the number of main access lines 202 and secondary access lines 203 in the memory cell array 200A, the number of data lines 204 may be independent of the number of memory cells 208, the number of main access lines 202, and the number of secondary access lines 203 in the NAND string 206. The main access lines 202 and their corresponding secondary access lines 203 may be referred to as access line pairs 205, 2050, and 2053.

[0043] Figure 2B It can be, for example, part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200B used in the type of memory described. Figure 2B Elements with the same number in the middle correspond to about Figure 2A The description provided. Figure 2B Additional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, wherein a portion of the pillars may serve as the channel region for both the main memory cell portion and the auxiliary memory cell portion of the split-gate memory cells of the NAND string 206.

[0044] NAND strings 206 can each be selectively connected to data lines 2040 to 204 by a select transistor 212 (e.g., a drain select transistor, often referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected via bias selection lines 2150 to 215. K Selective selection transistors 212, each located between NAND string 206 and data line 204, are selectively activated to connect to their respective data lines 204. Selection transistors 210 can be activated via bias selection line 214. Each access line pair 205 (e.g., main access line 202 and corresponding auxiliary access line 203) can be connected to multiple rows of memory cells in memory array 200B. Rows of split-gate memory cells that are commonly connected to each other via specific access line pairs 205 can be collectively referred to as layers.

[0045] A three-dimensional NAND memory array 200B may be formed above a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel transistors and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0046] Figure 2C It can be, for example, part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200C used in the type of memory described. Figure 2CElements with the same number in the middle correspond to about Figure 2A The provided description indicates that the memory cell array 200C may include a series-connected split-gate memory cell string (e.g., NAND string) 206, access line pairs (e.g., word line pairs) 205, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown below. Figure 2A As depicted in the diagram. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C. Figure 2C The NAND string 206 is divided into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a group of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can be selectively connected to source 216. The access line pair 205 and select lines 214 and 215 of a memory cell block 250 can be selectively connected to memory cell blocks 2500 to 2500 respectively. L Access line pair 205 and select lines 214 and 215 of any other memory cell block are not directly connected.

[0047] Data cable 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 230, which may be part of a data buffer in the memory. Buffer portion 230 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer section 230 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the text).

[0048] Although Figure 2C Each memory cell block 250 is depicted as having only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are typically associated with more than one select line 215. For example, the select lines 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2BSelection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 230 in response to its respective select line 215.

[0049] Figure 3A This is a schematic diagram of a split-gate memory cell 208 according to an embodiment. The memory cell 208 includes a main memory cell portion 340, whose control gate 344 is connected to (and in some cases forms) a main access line 202. The memory cell 208 further includes an auxiliary memory cell portion 342, whose control gate 346 is connected to (and in some cases forms) an auxiliary access line 203.

[0050] The main memory cell portion 340 includes a data storage structure 3500 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the main memory cell portion 340 (e.g., by changing a threshold voltage). The data storage structure 3500 may include both conductive and dielectric structures, while the control gate 344 is typically formed of one or more conductive materials.

[0051] The auxiliary memory cell portion 342 includes a data storage structure 3501 (e.g., a floating gate, charge trap, or other structure configured to store charge) for adjusting a threshold voltage of the auxiliary memory cell portion 342. The data storage structure 3501 may include both conductive and dielectric structures, while the control gate 346 is typically formed of one or more conductive materials. In some embodiments, the data storage structure 3500 and data storage structure 3501 may be isolated from each other. In other embodiments, the data storage structure 3500 and data storage structure 3501 may be connected to each other, for example, they may be a single data storage structure. For example, a data storage structure having bulk dielectric properties, such as a data storage structure made solely of dielectric materials or a data storage structure made of discontinuous instances of conductive materials (e.g., conductive nanodots or conductive crystals) contained within a continuous dielectric structure, may allow a single data storage structure to store independent charge levels between the control gate 344 and the data storage structure, and between the control gate 346 and the data storage structure.

[0052] Figures 3B to 3C This is a plan view of the split-gate memory cell 208 according to an embodiment. Figures 3B to 3C Elements with the same number in the middle correspond to about Figure 2A and 3A The description provided. Figures 3B to 3CAdditional details are provided regarding the possible structure of the split-gate memory cell 208.

[0053] exist Figure 3B In one example, memory cell 208 includes a main memory cell portion 340, whose control gate 344 is connected to (and in some cases forms) a main access line 202. Memory cell 208 further includes an auxiliary memory cell portion 342, whose control gate 346 is connected to (and in some cases forms) an auxiliary access line 203. The main access line 202 and the auxiliary access line 203 may be formed of one or more conductive materials. The main access line 202 and the auxiliary access line 203 may each comprise, consist of, or be primarily composed of conductive doped polysilicon, and / or may comprise, consist of, or be primarily composed of: metals, such as refractory metals; or metallic materials, such as refractory metal silicides or metal nitrides, such as refractory metal nitrides; and any other conductive materials.

[0054] The main memory cell portion 340 and the auxiliary memory cell portion 342 may share a common charge-blocking structure 348. The charge-blocking structure 348 may contain a dielectric material. The charge-blocking structure 348 may include, for example, an oxide of silicon dioxide (SiO2), composed of or primarily composed of oxides, and / or may include, composed of or primarily composed of, high-k dielectric materials, such as aluminum oxide (AlO2). x ), Hafnium oxide (HfO) x ), Hafnium aluminum oxide (HfAlO) x ), hafnium silicon oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), Zirconia aluminum (ZrAlO) x ) or yttrium oxide (Y2O3), and any other dielectric material. As used herein, a high-K dielectric means a material with a dielectric constant greater than that of silicon dioxide.

[0055] The main memory cell portion 340 and the auxiliary memory cell portion 342 may further share a common data storage structure 350 (e.g., a charge trap or other dielectric structure configured to store charge). The data storage structure 350 may (e.g., by changing a threshold voltage) determine the data state of the main memory cell portion 340 and may be used to adjust the threshold voltage of the auxiliary memory cell portion 342. The main memory cell portion 340 and the auxiliary memory cell portion 342 may further share a common gate dielectric structure 352. The gate dielectric structure 352 may contain a dielectric material, for example, that described in the reference charge blocking structure 348.

[0056] The main memory cell portion 340 and the auxiliary memory cell portion 342 may further share a common semiconductor pillar 354. The semiconductor pillar 354 may be formed of a semiconductor material of a specific conductivity type. As an example, the semiconductor pillar 354 may be formed of a silicon-containing material, such as P-type polysilicon. Although the semiconductor pillar 354 in... Figure 3B The image depicts a solid core, but the semiconductor pillar 354 may have a ring shape similar to the shape of the gate dielectric structure 352, such as a hollow core.

[0057] like Figure 3B As depicted, the charge-blocking structure 348, data storage structure 350, gate dielectric structure 352, and semiconductor pillar 354 extend the full length of the NAND string containing memory cells 208. Alternatively, the charge-blocking structure 348, data storage structure 350, and gate dielectric structure 352 of the memory cells 208 for the NAND string may be isolated from the charge-blocking structure 348, data storage structure 350, and / or gate dielectric structure 352 of the different memory cells 208 for the NAND string, wherein only the semiconductor pillar 354 extends the full length of the NAND string.

[0058] Isolation region 356 may extend between main access line 202 and auxiliary access line 203, for example, to achieve electrical isolation between main access line 202 and auxiliary access line 203. Isolation region 356 may contain a dielectric material, for example, as described in reference charge blocking structure 348. Isolation region 356 may extend to... Figure 3B The outer surface of the charge blocking structure 348 is depicted. The isolation region 356 may further extend beyond the outer surface of the charge blocking structure 348.

[0059] exist Figure 3C In one example, memory cell 208 includes a main memory cell portion 340, whose control gate 344 is connected to (and in some cases forms) a main access line 202. Memory cell 208 further includes an auxiliary memory cell portion 342, whose control gate 346 is connected to (and in some cases forms) an auxiliary access line 203. The main access line 202 and the auxiliary access line 203 may be formed of one or more conductive materials. The main access line 202 and the auxiliary access line 203 may each comprise, consist of, or be primarily composed of conductive doped polysilicon, and / or may comprise, consist of, or be primarily composed of: metals, such as refractory metals; or metallic materials, such as refractory metal silicides or metal nitrides, such as refractory metal nitrides; and any other conductive materials.

[0060] The main memory cell portion 340 may include a charge-blocking structure 3480, and the auxiliary memory cell portion 342 may include a charge-blocking structure 3481. The charge-blocking structures 348 (e.g., 3480 and 3481) may each contain a dielectric material. The charge-blocking structure 348 may include, for example, an oxide of silicon dioxide (SiO2), composed of or primarily composed of oxides, and / or may include, composed of or primarily composed of, high-k dielectric materials, such as aluminum oxide (AlO2). x ), Hafnium oxide (HfO) x ), Hafnium aluminum oxide (HfAlO) x ), hafnium silicon oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), Zirconia aluminum (ZrAlO) x ) or yttrium oxide (Y2O3), and any other dielectric material. As used herein, a high-K dielectric means a material with a dielectric constant greater than that of silicon dioxide.

[0061] The main memory cell portion 340 may further include a data storage structure 3500, and the auxiliary memory cell portion 342 may include a data storage structure 3501. The data storage structures 350 (e.g., 3500 and 3501) may each include a floating gate, a charge trap, or other structures configured to store charge. The data storage structure 3500 may determine the data state of the main memory cell portion 340 (e.g., by changing a threshold voltage), and the data storage structure 3501 may be used to adjust the threshold voltage of the auxiliary memory cell portion 342. The main memory cell portion 340 and the auxiliary memory cell portion 342 may further share a common gate dielectric structure 352. The gate dielectric structure 352 may contain a dielectric material, for example, as described in the reference charge blocking structure 348.

[0062] The main memory cell portion 340 and the auxiliary memory cell portion 342 may further share a common semiconductor pillar 354. The semiconductor pillar 354 may be formed of a semiconductor material of a specific conductivity type. As an example, the semiconductor pillar 354 may be formed of a silicon-containing material, such as P-type polysilicon. Although the semiconductor pillar 354 in... Figure 3B The image depicts a solid core, but the semiconductor pillar 354 may have a ring shape similar to the shape of the gate dielectric structure 352, such as a hollow core.

[0063] like Figure 3CAs depicted, charge-blocking structures 3480 and 3481, data storage structures 3500 and 3501, gate dielectric structure 352, and semiconductor pillar 354 extend the full length of the NAND string containing memory cells 208. Alternatively, the charge-blocking structures 3480 and 3481, data storage structures 3500 and 3501, and gate dielectric structure 352 of the memory cells 208 for the NAND string may be isolated from the charge-blocking structures 3480 and 3481, data storage structures 3500 and 3501, and / or gate dielectric structure 352 of the different memory cells 208 for the NAND string, wherein only the semiconductor pillar 354 extends the full length of the NAND string.

[0064] Isolation region 356 may extend between main access line 202 and auxiliary access line 203, for example, to achieve electrical isolation between main access line 202 and auxiliary access line 203. Isolation region 356 may contain a dielectric material, for example, as described in reference charge blocking structure 348. Isolation region 356 may extend to... Figure 3C The outer surface of the gate dielectric structure 352 is depicted. The isolation region 356 may extend further beyond the outer surface of the gate dielectric structure 352 and may extend to contact the semiconductor pillar 354, thus dividing the gate dielectric structure 352 into two isolation structures.

[0065] Figure 4 is a perspective view of the array structure according to an embodiment. The elements with the same number in Figure 4 correspond to... Figure 2A and 3A Refer to the description provided by 3C. Figure 4 provides additional details regarding the array structure of the split-gate memory cell 208.

[0066] Figure 4 depicts a portion of a memory cell array 400, which may have corresponding... Figure 2B A schematic diagram of the structure of a portion of the memory cell array 200B. Main access line 202. X and 202 X-1 And auxiliary access line 203 X and 203 X-1 They can correspond to respectively Figure 2B Any two adjacent main access lines from 2020 to 202 N And auxiliary access lines 2030 to 203 N Where X is an integer value from 1 to N. For example, the main memory line 202 in Figure 4... X and auxiliary access line 203 X They can correspond to respectively Figure 2B The primary access line 2021 and the secondary access line 2031 are shown in Figure 4, while the primary access line 2021 is shown in Figure 4. X-1 and auxiliary access line 203 X-1 They can correspond to respectively Figure 2BPrimary access line 2020 and secondary access line 2030.

[0067] Each memory cell group 460 (e.g., memory cell groups 4600 to 4603) may correspond to a column of memory cells, each of which is selectively connected to the same data line. For example, memory cell group 4600 of FIG4 may depict the selective connections of two NAND strings to the same data line. Figure 2B The data line 2040 portion, and the memory cell group 4601 in Figure 4, can depict the selective connection of each of the two NAND strings to... Figure 2B The same applies to data cable 2041.

[0068] Each memory cell group 462 (e.g., memory cell groups 4620 to 4621) may correspond to a subarray of memory cells, each subarray being selectively connected to a corresponding data line in response to the same select line. For example, memory cell group 4620 of FIG4 may depict four NAND strings being selectively connected in response to a control signal on select line 2150. Figure 2B The corresponding data line 204 portion, and the memory cell group 4621 of FIG4 can depict four NAND strings, each selectively connected in response to a control signal on the select line 2151. Figure 2B The corresponding data line 204.

[0069] Figure 4B According to the embodiments Figure 4A A planar diagram of the array structure. Figure 4BExamples are depicted for the electrical connections of portions 464 (e.g., portions 4640 to 4642) of the main access line 202 and portions 466 (e.g., portions 4660 to 4661) of the auxiliary access line 203. For example, portions 464 may each be commonly connected to collectively form the main access line 202, and portions 466 may each be commonly connected to collectively form the auxiliary access line 203. Portions 464 and 466 are interleaved, and one portion 464 or portion 466 may form the control gate for two memory cell groups 460 or columns of memory cells. For example, portion 4660 of the auxiliary access line 203 may form the control gate for auxiliary memory cell portions of memory cell groups 4600 and 4601. Similarly, portion 4641 of the main access line 202 may form the control gate for the main memory cell portions of memory cell groups 4601 and 4602. Although three parts 464 and two parts 466 are depicted, the main access line 202 and the auxiliary access line 203 can be formed by a higher number of parts 464 and 466, respectively. The number X of parts 464 and the number Y of parts 466 can satisfy one of the following relationships: X equals Y, X is one less than Y, or X is one greater than Y.

[0070] Figure 5 This is a cross-sectional view of a portion of a split-gate memory cell array according to an embodiment. Three-dimensional memory arrays are typically fabricated by forming alternating layers of conductors and dielectrics, forming vias in these layers, forming additional material on the sidewalls of the vias to define gate stacks for memory cells and other gates (e.g., select gates), and subsequently filling the vias with a semiconductor material to define pillar segments to act as channels for the memory cells and gates. To improve the conductivity of the pillar segments and adjacent semiconductor material (e.g., on which the pillar segments are formed), conductive (e.g., conductively doped) portions are typically formed at the interfaces between the pillar segments and the adjacent semiconductor material. These conductive portions are typically formed of a different conductivity type than that of the pillar segments and the adjacent semiconductor material. For example, if the pillar segments are formed of a P-type semiconductor material, then the conductive portions may have N-type conductivity.

[0071] Due to the nature of removal processes commonly used in the semiconductor industry, forming vias through multiple layers typically results in vias with diameters decreasing towards the bottom. To avoid the vias becoming too narrow, reference vias can be formed in segments. Figures 2A to 2C An array of the type described in section 4 allows for the formation of a layer for forming a first portion of a NAND string, followed by the removal of portions to define holes, within which the remaining structure can be formed. After forming the first portion of the NAND string, a second portion of the NAND string can be formed on top of the first portion in a similar manner. Figure 5 Describe a structure of this type according to an embodiment.

[0072] exist Figure 5 The diagram depicts two series-connected split-gate memory cell strings in a cross-sectional view. Note that the spaces between the various elements in the diagram typically represent dielectric material.

[0073] refer to Figure 5 The first NAND string may contain the first column segment 554. 00 Second column section 554 10 First column section 554 00 Second column section 554 10 Each portion can be formed from a semiconductor material of a first conductivity type (e.g., P-type polysilicon). Conductive portion 558 00 and 558 10 It can be formed in column section 554 respectively. 00 and 554 10 At the bottom, where the conductive part 558 00 Electrically connected to source 216 and conductive portion 558 10 Electrical connection to column section 554 00 Conductive part 558 00 and 558 10 It can be formed from a semiconductor material of a second conductivity type, different from the first conductivity type. For the first pillar segment 554... 00 Second column section 554 10 Examples of P-type polycrystalline silicon that can be formed individually, with conductive portion 558. 00 and 558 10 It can be formed from an N-type semiconductor material, such as N-type polycrystalline silicon. Additionally, the conductive portion 558... 00 and 558 10 It can have a higher elevation than the column section 554 00 and 554 10 The conductivity level. For example, the conductive part 558 00 and 558 10 It can have N+ conductivity. Alternatively, the conductive portion 558 00 and 558 10 It can be formed from conductors such as metals or metal silicides.

[0074] Column section 554 10 The conductive plug 5600 can be electrically connected to the data line 204. In this example, the conductive plug 5600 can also be formed of a semiconductor material of a second conductivity type, and can similarly have a higher diameter than the pillar section 554. 00 and 554 10 The conductivity level. Alternatively, the conductive plug 5600 may be formed of a conductor such as a metal or a metal silicide. The first NAND string may be further included between the source select line 214 and the pillar segment 554. 00The source selects the gate at the intersection point, and at the drain select line 215 and the pillar section 554 10 The drain selects the gate at the intersection point. The first NAND string may be further contained in the pillar segment 554. 00 and 554 10 Each of the split-gate memory cells is located at the intersection point of the main access lines 2020 to 2027 and the secondary access lines 2030 to 2037. These split-gate memory cells may further include data storage structures 350. 00 Up to 350 70 .Although Figure 5 The structure is depicted as containing only eight main access lines 202 and eight auxiliary access lines 203 for each NAND string in an effort to improve the readability of the diagram, but the NAND structure according to the embodiment may have significantly more main access lines 202 and auxiliary access lines 203.

[0075] Although not all are numbered, this is for clarity. Figure 5 The data storage structure 350 is depicted on both sides of the column segment 554. Individual data storage structures 350 may completely surround their respective column segments 554, for example... Figure 3B As depicted in the example. Alternatively, the first portion of the data storage structure 350 between its respective column segment 554 and its respective primary access line 202 may be isolated from the second portion of the data storage structure 350 between its respective column segment 554 and its respective secondary access line 203, for example... Figure 3C As depicted in the examples.

[0076] To improve the crossing of the conductive section 558 10 The conductivity of the first NAND string may further include select line 217 and column segment 554. 10 The intermediate gate at the intersection point. This divides the split-gate memory cells of the first NAND string into a first stack 5560 of split-gate memory cells and a second stack 5561 of split-gate memory cells. Although depicted as a conventional field-effect transistor, it is formed in the pillar segment 554. 10 The intermediate gate at the intersection with select line 217 can utilize data storage structure 350, as well as gate dielectric structure and charge blocking structure, similar to those formed on main access line 202 and auxiliary access line 203 and pillar segment 554. 10 The memory cell at the intersection point.

[0077] A stack 556 of split-gate memory cells can generally be considered as a group of split-gate memory cells sharing a common pillar segment 554 (i.e., a single pillar segment 554 that serves as the channel region of the split-gate memory cell group), and can be extended to include multiple split-gate memory cell groups, wherein each such split-gate memory cell group shares a common pillar segment 554, and the respective common pillar segments 554 are formed at the same level (e.g., intersected by the same main access line 202), the level of which may include all such split-gate memory cell groups sharing a common (e.g., one or more) main access lines 202. For example, a stack 5560 of split-gate memory cells may include main access lines 2020 to 2023 and secondary access lines 2030 to 2033 and pillar segment 554. 00 The split-gate memory cells formed at the intersection points. The stack 5560 of the split-gate memory cells may further include the main access lines 2020 to 2023 and the auxiliary access lines 2030 to 2033 and their corresponding cylinder segments 554. 00 and 554 01 Those split-gate memory cells formed at the intersection points, and may be further included in the main access lines 2020 to 2023 and the auxiliary access lines 2030 to 2033 and the pillar segment 554. 00 and 554 01 And all split-gate memory cells formed at the intersection with any other pillar segment 554 formed at the same level.

[0078] The channel region of the main memory cell portion of a split-gate memory cell in a split-gate memory cell group is connected to the channel region of the auxiliary memory cell portion of the split-gate memory cell in the same memory cell group. That is, if at least one of the memory cell portions of each split-gate memory cell is activated, a continuous conductive path can be established. For example, by biasing auxiliary access lines 2030, 2031, and 2033 to activate the corresponding auxiliary memory cell portion and by biasing the main access line 2032 to activate its corresponding main memory cell portion, a path through pillar segment 554 can be established. 00 The conductive path.

[0079] Further reference Figure 5 The second NAND string may contain the first column segment 554. 01 Second column section 554 11 First column section 554 01 Second column section 554 11 Each portion can be formed from a semiconductor material of a first conductivity type (e.g., P-type polysilicon). Conductive portion 558 01 and 558 11 It can be formed in column section 554 respectively.01 and 554 11 At the bottom, where the conductive part 558 01 Electrically connected to source 216 and conductive portion 558 11 Electrical connection to column section 554 01 Conductive part 558 01 and conductive part 558 11 It can be formed from a semiconductor material of the second conductivity type. For the first pillar segment 554... 01 Second column section 554 11 Examples of P-type polycrystalline silicon that can be formed individually, with conductive portion 558. 01 and 558 11 It can be formed from an N-type semiconductor material, such as N-type polycrystalline silicon. Additionally, the conductive portion 558... 01 and 558 11 It can have a higher elevation than the column section 554 01 and 554 11 The conductivity level. For example, the conductive part 558 01 and 558 11 It can have N+ conductivity.

[0080] Column section 554 11 The conductive plug 5601 can be electrically connected to the data line 204. In this example, the conductive plug 5601 can also be formed of a semiconductor material of a second conductivity type, and can similarly have a higher diameter than the pillar section 554. 01 and 554 11 The conductivity level. Alternatively, the conductive plug 5601 may be formed of a conductor such as a metal or a metal silicide. A second NAND string may be further included between the source select line 214 and the pillar segment 554. 01 The source selects the gate at the intersection point, and at the drain select line 215 and the pillar section 554 11 The drain selects the gate at the intersection point. The second NAND string can be further included in the pillar segment 554. 01 and 554 11 Each of the split-gate memory cells is located at the intersection point of the main access lines 2020 to 2027 and the secondary access lines 2030 to 2037. These split-gate memory cells may further include data storage structures 350. 01 Up to 350 71 It can have a reference data storage structure such as 350. 00 Up to 350 70 The structure described.

[0081] To improve the crossing of the conductive section 558 11 The conductivity of the second NAND string can be further enhanced by including select line 217 and column segment 554.11 The intermediate gate at the intersection point. This divides the split-gate memory cells of the second NAND string into a first stack 5560 of split-gate memory cells and a second stack 5561 of split-gate memory cells. Although Figure 5 Only two stacks 556 of split-gate memory cells are depicted, but according to embodiments, fewer or more stacks 556 of split-gate memory cells may be used in a NAND string. Additionally, although depicted as conventional field-effect transistors, they are formed in pillar segments 554. 11 The intermediate gate at the intersection with select line 217 can utilize data storage structure 350, as well as gate dielectric structure and charge blocking structure, similar to those formed on main access line 202 and auxiliary access line 203 and pillar segment 554. 11 The memory cell at the intersection point.

[0082] Figure 6 This is a schematic diagram of a portion of a memory cell array and a string driver, which can be found in the reference. Figure 1 The memory device of the described type is used to depict a many-to-one relationship between local main access lines (e.g., local main word lines) 202 and global main access lines (e.g., global main word lines) 602, and a many-to-one relationship between local auxiliary access lines (e.g., local auxiliary word lines) 203 and global auxiliary access lines (e.g., global auxiliary word lines) 603.

[0083] like Figure 6 As depicted, local main access lines (e.g., local main word lines) 202 of a plurality of memory cell blocks 250 may be selectively connected to a plurality of global main access lines (e.g., global main word lines) 602, and local auxiliary access lines (e.g., local auxiliary word lines) 203 of the plurality of memory cell blocks 250 may be selectively connected to a plurality of global auxiliary access lines (e.g., global auxiliary word lines) 603. Although Figure 6 Only memory cell blocks 2500 and 250 are depicted. L (Block 0 and Block L), but the local main access line 202 of the additional memory cell block 250 can be connected to the global main access line 602 in a similar manner, and the local auxiliary access line 203 of the additional memory cell block 250 can be connected to the global auxiliary access line 603 in a similar manner. Similarly, although Figure 6 Only four local primary access lines 202 and four local secondary access lines 203 are depicted, but memory cell block 250 may contain fewer or more local primary access lines 202 and local secondary access lines 203. Memory cell blocks 2500 to 250 L It can belong to a single memory cell plane 242.

[0084] To facilitate memory access operations on a specific memory cell block 250 that is co-coupled to a given set of global primary access lines 602 and a given set of global secondary access lines 603, each memory cell block 250 may have a corresponding set of block select transistors 662 and a corresponding set of block select transistors 664 that are one-to-one with its local primary access line 202 and its local secondary access line 203, respectively. The control gates of the set of block select transistors 662 and the set of block select transistors 664 of a given memory cell block 250 may be commonly connected to a corresponding block select line 668. For example, for memory cell block 2500, when block select transistor 662... 00 up to 662 30 Block select transistor 664 00 Up to 664 30 Local main access line 202 responds to the control signal received on block select line 6680. 00 Transistor 662 can be selected via block. 00 Selectively connected to global primary access line 6020 and local secondary access line 203. 00 Transistor 664 can be selected via block. 00 Selectively connected to global secondary access line 6030 and local primary access line 202. 10 Transistor 662 can be selected via block. 10 Selectively connected to global primary access line 6021 and local secondary access line 203. 10 Transistor 664 can be selected via block. 10 Selectively connected to global secondary access line 6031 and local primary access line 202 20 Transistor 662 can be selected via block. 20 Selectively connected to global primary access line 6022 and local secondary access line 203. 20 Transistor 664 can be selected via block. 20 Selectively connected to global secondary access line 6032 and local primary access line 202 30 Transistor 662 can be selected via block. 30 Selectively connected to global primary access line 6023, and local secondary access line 203 30 Transistor 664 can be selected via block. 30 Selectively connected to global auxiliary access line 6033. Block select transistors 662 and 664 of memory cell block 250 can be collectively referred to as a serial driver, or simply as a driver circuit system.

[0085] Figures 7A to 7B This is a conceptual depiction of the threshold voltage distribution of multiple memory cells used in the embodiments. Figure 7AThis describes an example of the threshold voltage range and threshold voltage distribution 770 of those memory cells after an erase operation. For example, charge can be removed from the data storage structure of those memory cells to place the memory cells in an initial data state, such as an erased data state. Figure 7B Examples illustrating the threshold voltage range and distribution of a memory cell that may be referred to as a single-level memory cell (SLC). A memory cell programmed as an SLC can store one of two data states, such as a logic 1 or a logic 0 data state. For example, threshold voltage distribution 772 may represent a logic 1 data state, and threshold voltage distribution 774 may represent a logic 0 data state.

[0086] During the programming process of the SLC memory, memory cells with a predetermined threshold voltage distribution 772 can be prevented from being programmed, allowing the memory cells to maintain their state. Figure 7A The threshold voltage is present in the threshold voltage distribution 770. Programming of memory cells with predetermined threshold voltages within the threshold voltage distribution 774 can be enabled to shift (e.g., increase) the threshold voltage of the memory cell. Typically, such programming involves applying a programming pulse to the control gate of the memory cell, followed by a verification operation to determine whether the memory cell has reached the desired threshold voltage. A typical programming operation uses a number of programming pulses in an incremental step-pulse programming scheme, where each programming pulse is a single pulse that shifts the threshold voltage of the memory cell by a certain amount, and each subsequent programming pulse is higher than the previous programming pulse. For the verification operation, a verification voltage Vvfy can be applied to the control gate of the memory cell to determine whether the memory cell remains deactivated. If the memory cell remains deactivated in response to the verification voltage Vvfy, then programming of the memory cell can be considered complete. If the memory cell is activated in response to the verification voltage Vvfy, then an additional higher programming pulse can be applied to the control gate of the memory cell when programming of the memory cell is enabled. This procedure / verification process can be repeated until each memory cell selected for programming has reached its desired data state.

[0087] To sense the data state of memory cells (e.g., selected memory cells) in a series-connected memory cell string, the memory cell may receive a verification voltage Vvfy at its control gate for verification operations or a read voltage Vread at its control gate for read operations. The verification voltage Vvfy is typically higher than the read voltage Vread to improve the reliability of subsequent read operations. During either verification or read operations, the remaining memory cells in the series-connected memory cell string (e.g., non-selected memory cells) may receive a pass voltage Vpass applied to their control gate to activate those memory cells, regardless of their data state. In this way, the ability of the series-connected memory cell string to conduct current can be used to indicate whether a selected memory cell is activated or deactivated.

[0088] During a programming operation, some memory cells may become overprogrammed, which can be indicated by the threshold voltage distribution 776. This can happen if the voltage level difference between a programming pulse and an immediately following programming pulse is too high for the programming speed of the memory cell. For example, due to anomalous manufacturing processes or materials, the programming speed of a memory cell may be unexpectedly fast. While smaller incremental steps between programming pulses can reduce the risk of overprogramming, this typically increases the time and power requirements for completing the programming operation.

[0089] Memory cells with threshold voltages higher than the pass voltage Vpass in threshold voltage distribution 776 will remain deactivated in response to the pass voltage Vpass applied to their control gate. Therefore, during sensing operations (e.g., verification operations or read operations), a string of serially connected memory cells containing non-selected memory cells with threshold voltages higher than the pass voltage Vpass will indicate that the selected memory cell is deactivated, regardless of whether it is activated in response to the read voltage Vread applied to its control gate. This can lead to data errors. Various embodiments provide array structures and mechanisms to mitigate such errors. Various embodiments can further facilitate reduced programming time and reduced power requirements for completing programming operations.

[0090] For example, auxiliary memory cell portions connected in series with a string of split-gate memory cells can each be programmed to a controlled threshold voltage range. This programming can be performed before the memory is installed into the electronic system. It is anticipated that such programming of the auxiliary memory cell portions will be performed only infrequently, and possibly only once during the expected lifetime of the memory. With the auxiliary memory cell portions having controlled threshold voltage ranges, overprogramming of the main memory cell portions may become meaningless. Specifically, because only one memory cell portion activating a split-gate memory cell provides a current path through the split-gate memory cell, the main memory cell portion of a non-selected split-gate memory cell deactivated by voltage during a read operation of the selected split-gate memory cell will not affect the sensed data state of the selected split-gate memory cell, provided that the auxiliary memory cell portions of the non-selected split-gate memory cells are activated. Therefore, programming of the main memory cell portions can be performed using a single programming pulse with a voltage level sufficient to increase the threshold voltage of the main memory cell portion to a level exceeding the verification voltage. Such voltage levels can be determined during memory characterization during manufacturing and testing. This voltage level can represent the minimum voltage level determined to be the threshold voltage for each memory cell that sufficiently increases the memory. Alternatively, a corresponding voltage level can be determined for smaller groups of memory cells (e.g., memory cell blocks or memory cell pages).

[0091] To prepare the memory according to the embodiment, both the main memory cell portion and the auxiliary memory cell portion of the split-gate memory cell can be erased. Table 1 provides examples of voltage levels that can be applied to the series-connected string of split-gate memory cells during the erase operation of both the main memory cell portion and the auxiliary memory cell portion.

[0092] Table 1

[0093] node voltage level Data cable 204 20V Main access line 202 0V Auxiliary access line 203 0V Source 216 20V

[0094] Other voltage levels can be used to erase split-gate memory cells. Generally, a voltage differential is applied between the control gate of the split-gate memory cell and the channel region of the split-gate memory cell, the voltage differential being configured to remove charge from the data storage nodes in the main memory cell section and the auxiliary memory cell section. Although not listed in Table 1, select gates, such as select gates 210 and 212, can be activated during the erase operation. It should be noted that the erase operation can be iterative, with the erase voltage applied to the data lines and the source increasing. An erase verification operation can be performed between erase voltages.

[0095] After erasing a split-gate memory cell, an auxiliary memory cell portion can be programmed to a controlled threshold voltage range. Programming an auxiliary memory cell portion may involve an iterative process of applying a programming pulse to the auxiliary memory cell portion and verifying, in response to the programming pulse, whether the auxiliary memory cell portion has reached its target threshold voltage, and repeating the iterative process until the auxiliary memory cell portion passes verification. Once an auxiliary memory cell portion passes verification, it can be prevented from further programming, but programming of other auxiliary memory cell portions can still be enabled for subsequent programming pulses. The iterative process can be repeated using varying (e.g., increasing) voltage levels of the programming pulses until each auxiliary memory cell portion selected for programming operation has reached its target threshold voltage or until some failure is declared, for example, the maximum number of allowed programming pulses is reached during programming operation. Table 2 provides examples of voltage levels that can be applied to a string of serially connected split-gate memory cells during programming operations of auxiliary memory cell portions of selected split-gate memory cells.

[0096] Table 2

[0097]

[0098] Other voltage levels can be used to program the auxiliary memory cell portion of a split-gate memory cell. Although not listed in Table 2, the active source select gate, such as select gate 210, can be deactivated during programming operations, while the active drain select gate, such as select gate 212, can be activated for enabled split-gate memory cells and deactivated for disabled split-gate memory cells. Generally, a voltage differential is applied between the control gate of the auxiliary memory cell portion of the selected split-gate memory cell and the channel region of the selected split-gate memory cell, the voltage differential being configured to add charge to the data storage node of the auxiliary memory cell portion of the selected split-gate memory cell. The main memory cell portion and non-selected auxiliary memory cell portions can receive voltage levels at their control gates configured to activate those memory cell portions and disable programming of those memory cell portions. Programming operations can be performed simultaneously for the auxiliary memory cell portions of each split-gate memory cell connected to a selected auxiliary access line and selectively connected to the corresponding data line in response to a control signal on the same select line 215. In response to the auxiliary memory cell portion reaching a target threshold voltage, the corresponding data lines selectively connected to the auxiliary memory cell portion can be increased to, for example, a disable voltage level, configured to deactivate the corresponding drain-select gate 212 activating the data line, causing the channel region of the disabled series-connected memory cell string to become electrically floating. The resulting threshold voltage distribution of the auxiliary memory cell portion can correspond to... Figure 7BThe threshold voltage distribution 774. The selection of the voltage difference between adjacent programming pulses can be used to control the width of the threshold voltage distribution in a manner understood in the art. In this way, the controlled threshold voltage range of the auxiliary memory cell portion can be higher than the verification voltage level and lower than the pass voltage of the memory read operation.

[0099] As previously mentioned, verification operations can be performed between programming pulses. Table 3 provides examples of voltage levels that can be applied to the series-connected string of split-gate memory cells during verification operations in the auxiliary memory cell portion of a selected split-gate memory cell.

[0100] Table 3

[0101] node voltage level Data cable 204 Vcc Main access line 202 -3V Select auxiliary access line 203 0.5V Non-selected auxiliary access line 203 5V Source 216 0V

[0102] Other voltage levels can be used to verify the auxiliary memory cell portions of a split-gate memory cell. Generally, a verification voltage level (e.g., 0.5V in this example) can be applied to the control gate of the auxiliary memory cell portion of a selected split-gate memory cell. For the remaining non-selected split-gate memory cells, the control gate of their auxiliary memory cell portions can receive a voltage level sufficient to activate those auxiliary memory cell portions, such as a pass voltage, if the auxiliary memory cell portions have a threshold voltage within a controlled threshold voltage range. It should be noted that if the non-selected split-gate memory cells have not yet been programmed, some of the auxiliary memory cell portions of these non-selected split-gate memory cells may still be in an erased state. However, such auxiliary memory cell portions will still be activated in response to the pass voltage. During the verification operation, the control gate of the main memory cell portion of each split-gate memory cell in the series-connected split-gate memory cell string can receive a voltage level sufficient to deactivate those main memory cell portions having a threshold voltage corresponding to an erased state. If, for example, current flow is detected through a voltage drop on the data line through the auxiliary memory cell portion of the selected split-gate memory cell, then the auxiliary memory cell portion can be considered to have failed the verification operation and is enabled for programming during a subsequent programming pulse. If no current flow is detected through the auxiliary memory cell portion of the selected split-gate memory cell, then the auxiliary memory cell portion can be considered to have passed the verification operation and is disabled for programming during a subsequent programming pulse.

[0103] Programming of auxiliary memory cell portions can be performed by the memory manufacturer. For example, in response to the number of program / erase cycles of the main memory cell portion of a split-gate memory cell, or in response to an event such as the number of bit errors exceeding a threshold, the memory can autonomously assess the need to reprogram the auxiliary memory cell portions. For instance, a background verification operation can be performed to determine whether any of the auxiliary memory cell portions has experienced charge loss, causing the threshold voltage of said auxiliary memory cell portion to fall below the verification voltage level. Such auxiliary memory cell portions can then be reprogrammed as discussed with reference to Table 2. This can be done when the memory is idle, making the operation invisible to the user of the memory. It should be noted that an erase operation is not required before reprogramming, as the goal is simply to increase the threshold voltage from its current level back to the controlled threshold voltage range.

[0104] User data can be programmed into the main memory cell portion of a split-gate memory cell when the auxiliary memory cell portion is programmed to have a threshold voltage level within its desired controlled threshold voltage range. While programming the main memory cell portion may involve an iterative process similar to that of the auxiliary memory cell portion, various embodiments have been disclosed to mitigate errors caused by overprogramming. Thus, programming the main memory cell portion as an SLC memory may involve applying a single programming pulse to the main memory cell portion having a voltage level considered sufficient to increase the threshold voltage of the main memory cell portion to a level higher than the read voltage of a read operation of the memory. Such voltage levels can be determined during memory characterization. Verification operations may not be performed. Although such advantages may not be available where data needs to be stored in the main memory cell portion at higher memory densities (e.g., MLC, TLC, QLC, etc.), various embodiments can still mitigate errors caused by overprogramming of the main memory cell portion. Table 4 provides examples of voltage levels that can be applied to a string of split-gate memory cells connected in series during programming operations of the main memory cell portion of a selected split-gate memory cell.

[0105] Table 4

[0106]

[0107] Other voltage levels can be used to program the main memory cell portion of a split-gate memory cell. Although not listed in Table 4, the active source select gate, such as select gate 210, can be deactivated during programming, while the active drain select gate, such as select gate 212, can be activated for enabled split-gate memory cells and deactivated for disabled split-gate memory cells. Generally, a voltage differential is applied between the control gate of the main memory cell portion of the selected split-gate memory cell and the channel region of the selected split-gate memory cell, the voltage differential being configured to add charge to the data storage node of the main memory cell portion of the selected split-gate memory cell. Auxiliary memory cell portions and non-selected main memory cell portions can receive voltage levels at their control gates configured to activate those memory cell portions and disable programming of those memory cell portions. Programming operations can be performed simultaneously for the main memory cell portions of each split-gate memory cell connected to a selected main access line and selectively connected to the corresponding data line in response to a control signal on the same select line 215. The resulting threshold voltage distribution of the main memory cell portions can correspond to... Figure 7B The threshold voltage distribution is 776.

[0108] After the main memory cell portion is programmed, a read operation can be performed. Table 5 provides examples of voltage levels that can be applied to the series-connected string of split-gate memory cells during a read operation of the main memory cell portion of a selected split-gate memory cell.

[0109] Table 5

[0110] node voltage level Data cable 204 Vcc Select main access line 202 0V Non-selected main access line 202 5V Select auxiliary access line 203 0V Non-selected auxiliary access line 203 5V Source 216 0V

[0111] Other voltage levels can be used to verify the auxiliary memory cell portions of a split-gate memory cell. Although not listed in Table 5, select gates, such as select gates 210 and 212, can be activated during read operations. Generally, a read voltage level (e.g., 0V in this example) can be applied to the control gate of the main memory cell portion of the selected split-gate memory cell to selectively activate the main memory cell portion depending on the data state of that main memory cell portion. The control gate of the auxiliary memory cell portion of the selected split-gate memory cell can receive a voltage level configured to deactivate the auxiliary memory cell portion. For the remaining non-selected split-gate memory cells, the control gate of their auxiliary memory cell portions can receive a voltage level sufficient to activate those auxiliary memory cell portions, such as a pass voltage, if the auxiliary memory cell portions have a threshold voltage within a controlled threshold voltage range. Although not strictly necessary, the control gate of the main memory cell portion of the non-selected split-gate memory cells can also receive a pass voltage intended to activate those main memory cell portions, regardless of the data state of the memory cell. In some embodiments, the non-selected main access line 202 can receive 0V, which reduces energy requirements during read operations.

[0112] The data state of a selected split-gate memory cell can be determined by a sensed current flowing through the main memory cell portion of the selected split-gate memory cell. If, for example, current flow through the main memory cell portion of the selected split-gate memory cell is detected via a voltage drop on the data line, then the selected split-gate memory cell can be considered to have a first data state, such as an erased data state or logic 1. If no current flow through the main memory cell portion of the selected split-gate memory cell is detected, then the selected split-gate memory cell can be considered to have a second data state, such as a programmed data state or logic 0.

[0113] Erasing the main memory cell portion can be performed without erasing the auxiliary memory cell portion. Table 6 provides examples of voltage levels that can be applied to the series-connected split-gate memory cell string during the erase operation of the main memory cell portion.

[0114] Table 6

[0115] node voltage level Data cable 204 20V Main access line 202 0V Auxiliary access line 203 float Source 216 20V

[0116] Other voltage levels can be used to erase the main memory cell portion of a split-gate memory cell. Generally, a voltage differential is applied between the control gate of the main memory cell portion of the split-gate memory cell and the channel region of the split-gate memory cell, the voltage differential being configured to remove charge from the data storage node of the main memory cell portion. Floating the secondary access line allows it to follow the voltage level of the channel region via capacitive coupling, thus preventing the erasure of the secondary memory cell portion. Although not listed in Table 6, select gates, such as select gates 210 and 212, can be activated during the erase operation. It should be noted that the erase operation can be iterative, with the erase voltage applied to the data line and source increasing. An erase verification operation can be performed between erase voltages.

[0117] Figure 8 A flowchart depicts a method for operating a memory during an erase operation according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in an instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., associated components of the memory) to perform the method.

[0118] At 801, each of the plurality of main access lines can be actively biased when an erase voltage is applied to each of the plurality of serially connected split-gate memory cell strings. The bias level of a particular main access line among the plurality of main access lines can be a voltage level configured to remove charge from the data storage structure connected to each main memory cell portion of the particular main access line. Different voltage levels can be applied to different main access lines among the plurality of main access lines. For example, in a configuration similar to... Figure 5 In array structures, but in array structures with more than two stacks, different channel voltages can produce different pillar sections, so that the main access lines for different stacks can receive different voltage levels to provide similar (e.g., the same) voltage differential.

[0119] At 803, each of the plurality of auxiliary access lines can be electrically floated when an erase voltage is applied to each of the plurality of series-connected split-gate memory cell strings. The auxiliary memory cell portions of the plurality of series-connected split-gate memory cell strings can each have a positive threshold voltage. The main memory cell portions of the plurality of series-connected split-gate memory cell strings can have either a positive or negative threshold voltage.

[0120] Figure 9A flowchart depicts a method for operating a memory during a read operation according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., an associated component of the memory) to perform the method.

[0121] At 911, a first voltage level can be applied to a selected main access line among a plurality of main access lines that is connected to the control gate of a main memory cell portion of a selected split-gate memory cell, wherein the first voltage level is configured to selectively activate the main memory cell portion depending on the data state of the main memory cell portion of the selected split-gate memory cell.

[0122] At 913, a second voltage level can be applied to a selected auxiliary access line of a plurality of auxiliary access lines connected to the control gate of an auxiliary memory cell portion of a selected split-gate memory cell, wherein the second voltage level is configured to deactivate the auxiliary memory cell portion of the selected split-gate memory cell.

[0123] At 915, a third voltage level can be applied to a non-selected auxiliary access line of a plurality of auxiliary access lines connected to the control gate of the auxiliary memory cell portion of a non-selected split-gate memory cell in a read operation, wherein the third voltage level is configured to activate the auxiliary memory cell portion of the non-selected split-gate memory cell. The third voltage level can be applied to each of the plurality of auxiliary access lines other than the selected auxiliary access line. The third voltage level can further be applied to a non-selected main access line of a plurality of main access lines connected to the control gate of the main memory cell portion of a non-selected split-gate memory cell, wherein the third voltage level is configured to activate the main memory cell portion of the non-selected split-gate memory cell. The third voltage level can further be applied to each of the plurality of main access lines other than the selected main access line.

[0124] in conclusion

[0125] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory comprising: A memory cell array comprising a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings comprises a main memory cell portion and an auxiliary memory cell portion, and wherein, For each of the plurality of serially connected split-gate memory cells, the main memory cell portion of the split-gate memory cell is configured to store data states that can be accessed by a read operation during normal operation of the memory, and the data states of the auxiliary memory cell portion of the split-gate memory cell are configured not to be accessed by the read operation during normal operation of the memory. Multiple main access lines, wherein each of the multiple main access lines is connected to the control gate of the main memory cell portion of the corresponding split gate memory cell in each of the multiple series-connected split gate memory cell strings. as well as A plurality of auxiliary access lines, wherein each of the plurality of auxiliary access lines is connected to the control gate of the auxiliary memory cell portion of the respective split gate memory cell in each of the plurality of serially connected split gate memory cell strings.

2. The memory according to claim 1, wherein, For each of the plurality of serially connected split-gate memory cells, the main memory cell portion of the split-gate memory cell is configured to output data using a read operation of the memory, and the data state of the auxiliary memory cell portion of the split-gate memory cell is configured to be inaccessible using the read operation.

3. The memory according to claim 1, further comprising: Multiple data lines, wherein each of the multiple data lines is selectively connected to a corresponding serially connected split-gate memory cell string in the multiple serially connected split-gate memory cell strings; as well as A common source, wherein each of the plurality of serially connected split-gate memory cell strings is selectively connected to the common source.

4. The memory according to claim 3, wherein the plurality of serially connected split-gate memory cell strings are a first plurality of serially connected split-gate memory cell strings, and wherein the memory cell array further comprises: The second plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the second plurality of serially connected split-gate memory cell strings includes a main memory cell portion and an auxiliary memory cell portion; Each of the plurality of data lines is further selectively connected to a corresponding serially connected split-gate memory cell string in the second plurality of serially connected split-gate memory cell strings; and Each of the second plurality of serially connected split-gate memory cell strings is selectively connected to the common source.

5. The memory of claim 4, wherein each of the plurality of main access lines is further connected to the control gate of the main memory cell portion of the corresponding split gate memory cell in each of the second plurality of serially connected split gate memory cell strings, and wherein each of the plurality of auxiliary access lines is connected to the control gate of the auxiliary memory cell portion of the corresponding split gate memory cell in each of the second plurality of serially connected split gate memory cell strings.

6. The memory according to claim 1, wherein, For each of the plurality of serially connected split-gate memory cells, the main memory cell portion of the split-gate memory cell includes a data storage structure, and the auxiliary memory cell portion of the split-gate memory cell includes a data storage structure.

7. The memory according to claim 6, wherein, For each of the plurality of serially connected split-gate memory cells, the data storage structure of the main memory cell portion of the split-gate memory cell and the data storage structure of the auxiliary memory cell portion of the split-gate memory cell include a continuous dielectric structure.

8. The memory according to claim 6, wherein, For each of the plurality of serially connected split-gate memory cells, the data storage structure of the main memory cell portion of the split-gate memory cell is isolated from the data storage structure of the auxiliary memory cell portion of the split-gate memory cell.

9. The memory according to claim 8, wherein, For each of the plurality of serially connected split-gate memory cells, the data storage structure of the main memory cell portion of the split-gate memory cell includes a first conductive structure, and the data storage structure of the auxiliary memory cell portion of the split-gate memory cell includes a second conductive structure.

10. The memory according to claim 1, wherein, For each of the plurality of serially connected split-gate memory cells, the channel region of the main memory cell portion of the split-gate memory cell is connected to the channel region of the auxiliary memory cell portion of the split-gate memory cell.

11. A memory comprising: A memory cell array comprising a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings comprises a main memory cell portion and an auxiliary memory cell portion; Multiple main access lines, wherein each of the multiple main access lines is connected to the control gate of the main memory cell portion of the corresponding split gate memory cell in each of the multiple series-connected split gate memory cell strings. Multiple auxiliary access lines, wherein each of the multiple auxiliary access lines is connected to the control gate of the auxiliary memory cell portion of the corresponding split gate memory cell in each of the multiple series-connected split gate memory cell strings. as well as A controller for accessing the memory cell array; During the erase operation on the plurality of serially connected split-gate memory cell strings, the controller is configured such that the memory: When an erase voltage is applied to each of the plurality of serially connected split-gate memory cell strings, each of the plurality of main access lines is actively biased; and When the erase voltage is applied to each of the plurality of series-connected split-gate memory cell strings, each of the plurality of auxiliary access lines is electrically floated.

12. The memory of claim 11, wherein the controller is configured such that the memory actively biases each of the plurality of main access lines when the erase voltage is applied, the controller is configured such that the memory actively biases a particular of the plurality of main access lines with a voltage level configured to remove charge from a data storage structure connected to each main memory cell portion of the particular main access line.

13. The memory of claim 11, wherein the controller is configured such that the memory actively biases each of the plurality of main access lines when the erase voltage is applied, the controller is configured such that the memory actively biases each of the plurality of main access lines with a corresponding voltage level, the voltage level being configured to remove charge from the data storage structure of each main memory cell portion connected to the main access line.

14. The memory according to claim 11, wherein, For each of the plurality of serially connected split-gate memory cells, the auxiliary memory cell portion of the split-gate memory cell has a positive threshold voltage.

15. The memory according to claim 14, wherein, For at least one of the plurality of serially connected split-gate memory cell strings, the main memory cell portion of the split-gate memory cell has a negative threshold voltage.

16. A memory comprising: A memory cell array comprising a plurality of serially connected split-gate memory cell strings, wherein each split-gate memory cell in the plurality of serially connected split-gate memory cell strings comprises a main memory cell portion and an auxiliary memory cell portion; Multiple main access lines, wherein each of the multiple main access lines is connected to the control gate of the main memory cell portion of the corresponding split gate memory cell in each of the multiple series-connected split gate memory cell strings. Multiple auxiliary access lines, wherein each of the multiple auxiliary access lines is connected to the control gate of the auxiliary memory cell portion of the corresponding split gate memory cell in each of the multiple series-connected split gate memory cell strings. as well as A controller for accessing the memory cell array; During a read operation on a selected split-gate memory cell in a specific serially connected split-gate memory cell string of the plurality of serially connected split-gate memory cell strings, the controller is configured such that the memory: A first voltage level is applied to a selected main access line of the plurality of main access lines connected to the control gate of the main memory cell portion of the selected split-gate memory cell, wherein the first voltage level is configured to selectively activate the main memory cell portion depending on the data state of the main memory cell portion of the selected split-gate memory cell. A second voltage level is applied to a selected auxiliary access line among the plurality of auxiliary access lines connected to the control gate of the auxiliary memory cell portion of the selected split-gate memory cell, wherein the second voltage level is configured to deactivate the auxiliary memory cell portion of the selected split-gate memory cell; and A third voltage level is applied to the non-selected auxiliary access line of the plurality of auxiliary access lines that is connected to the control gate of the auxiliary memory cell portion of the non-selected split-gate memory cell of the read operation, wherein the third voltage level is configured to activate the auxiliary memory cell portion of the non-selected split-gate memory cell.

17. The memory of claim 16, wherein the controller is configured such that the memory applies the third voltage level to the non-selected secondary access line, the controller is configured such that the memory applies the third voltage level to each of the plurality of secondary access lines other than the selected secondary access line.

18. The memory of claim 16, wherein the controller is further configured such that the memory applies the third voltage level to a non-selected main access line of the plurality of main access lines connected to the control gate of the main memory cell portion of the non-selected split-gate memory cell, wherein the third voltage level is configured to activate the main memory cell portion of the non-selected split-gate memory cell.

19. The memory of claim 18, wherein the controller is configured such that the memory applies the third voltage level to the non-selected main access line, the controller being configured such that the memory applies the third voltage level to each of the plurality of main access lines other than the selected main access line.

20. The memory according to claim 16, wherein, For each of the plurality of serially connected split-gate memory cells, the auxiliary memory cell portion of the split-gate memory cell has a positive threshold voltage.

21. The memory according to claim 20, wherein, For at least one of the plurality of serially connected split-gate memory cell strings, the main memory cell portion of the split-gate memory cell has a negative threshold voltage.

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