Flash memory controller and encoding circuit therein

Abstract

An encoding circuit applied in a flash memory controller includes an auxiliary data generating circuit and an encoder. In operation of the encoding circuit, the auxiliary data generating circuit receives a plurality of data blocks to generate auxiliary data of the plurality of data blocks, and the encoder encodes the plurality of data blocks according to a check code check matrix to generate a check code, and replaces a part of the check code with the auxiliary data to generate an adjusted check code, wherein the plurality of data blocks and the adjusted check code are written into a flash memory. The present application replaces dependent bits in the check code originally generated by the encoding circuit with auxiliary data having actual functions, so as to make full use of memory space to avoid waste of space, and further adds auxiliary data in the check code, so that the accuracy of the correctness / integrity check in the decoding process is higher.

Description

[0001] This application is a divisional application of the China Invention Application No. 201910039611.X, with the application date of January 16, 2019, and the title of “Flash Memory Controller and Coding Circuit and Decoding Circuit Therein”. TECHNICAL FIELD

[0002] The present application relates to a flash memory, and in particular, to a coding circuit and a decoding circuit applied in a flash memory controller. BACKGROUND

[0003] In the current Low-Density Parity Check code (LDPC code) encoder, if the parity check matrix used is a non-full rank parity check matrix, the parity code generated will include a plurality of bits (usually referred to as dependent bits) that do not have error correction effect, thus causing waste of memory space. SUMMARY

[0004] Therefore, one of the purposes of the present application is to provide a coding circuit that can use the addresses of the original dependent bits to store other auxiliary data to solve the problems in the prior art.

[0005] In one embodiment of the present application, a coding circuit applied in a flash memory controller is disclosed, which includes an auxiliary data generation circuit and an encoder. In the operation of the coding circuit, the auxiliary data generation circuit is used to receive a plurality of data blocks to generate an auxiliary data of the plurality of data blocks, and the encoder is used to encode the plurality of data blocks according to a parity check matrix to generate a parity code, and replace a part of the parity code with the auxiliary data to generate an adjusted parity code, wherein the plurality of data blocks and the adjusted parity code are written into a flash memory.

[0006] In another embodiment of the present application, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises a memory, a microprocessor and an encoding circuit. The memory is used to store a program code, and the microprocessor is used to execute the program code to control access to the flash memory module, and the encoding circuit comprises an auxiliary data generating circuit and an encoder. In operation of the encoding circuit, the auxiliary data generating circuit is used to receive a plurality of data chunks to generate an auxiliary data for the plurality of data chunks, and the encoder is used to encode the plurality of data chunks according to a check matrix of a check code to generate a check code, and replace a portion of the check code with the auxiliary data to generate a modified check code, wherein the plurality of data chunks and the modified check code are written into a flash memory.

[0007] In another embodiment of the present application, a decoding circuit used in a flash memory controller is disclosed, which comprises a decoder and a check circuit. In operation of the decoding circuit, the decoder is used to decode a data from a flash memory to generate a decoded data and a decoded check code; and the check circuit is used to obtain an auxiliary data from the decoded check code, and determine integrity or correctness of the decoded data according to the auxiliary data to generate a check result; wherein when the check result indicates that the integrity or correctness of the decoded data is normal, the decoded data is transmitted to a host device coupled to the flash memory controller.

[0008] In another embodiment of the present application, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises a memory, a microprocessor and a decoding circuit. The memory is used to store a program code, and the microprocessor is used to execute the program code to control access to the flash memory module, and the decoding circuit comprises a decoder and a check circuit. In operation of the decoding circuit, the decoder is used to decode a data from a flash memory to generate a decoded data and a decoded check code; and the check circuit is used to obtain an auxiliary data from the decoded check code, and determine integrity or correctness of the decoded data according to the auxiliary data to generate a check result; wherein when the check result indicates that the integrity or correctness of the decoded data is normal, the decoded data is transmitted to a host device coupled to the flash memory controller. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a memory device according to an embodiment of the present application.

[0010] Figure 2 A schematic diagram of a check matrix and a check matrix generator.

[0011] Figure 3 A schematic diagram of an encoding circuit according to an embodiment of the application.

[0012] Figure 4 A schematic diagram illustrating a data block, a cyclic redundancy check code and an adjusted check code written into a flash memory module.

[0013] Figure 5 A flowchart of an encoding method according to an embodiment of the application.

[0014] Figure 6 A schematic diagram of a decoding circuit according to an embodiment of the application.

[0015] Figure 7 A flowchart of a decoding method according to an embodiment of the application.

[0016] Wherein the reference numerals are explained as follows:

[0017] 100 memory device

[0018] 110 flash controller

[0019] 112 microprocessor

[0020] 112C program code

[0021] 112M read only memory

[0022] 114 control logic

[0023] 116 buffer memory

[0024] 118 interface logic

[0025] 120 flash memory module

[0026] 130 host device

[0027] 132 encoding circuit

[0028] 134 decoding circuit

[0029] 310 cyclic redundancy check encoder

[0030] 320 low density parity check encoder

[0031] 322 local check code calculation circuit

[0032] 324 cyclic convolution calculation circuit

[0033] 326 compensation circuit

[0034] 330 auxiliary data generation circuit

[0035] 500-510, 700-708 steps

[0036] 610 low density parity check code decoder

[0037] 620 checking circuit DETAILED DESCRIPTION

[0038] Figure 1 A schematic diagram of a memory device 100 according to an embodiment of the present application is shown in FIG. 1. The memory device 100 includes a flash memory module 120 and a flash memory controller 110 for accessing the flash memory module 120. According to the embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M stores a program code 112C, and the microprocessor 112 executes the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoding circuit 132 and a decoding circuit 134. The encoding circuit 132 encodes data to be written into the flash memory module 120 to generate corresponding check codes (or error correction codes, ECC), and the decoding circuit 134 decodes data read from the flash memory module 120.

[0039] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each of the flash memory chips includes a plurality of blocks. The controller (e.g., the flash memory controller 110 executing the program code 112C by the microprocessor 112) performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a certain number of data pages. The controller (e.g., the flash memory controller 110 executing the program code 112C by the microprocessor 112) performs an operation of writing data on the flash memory module 120 in units of data pages.

[0040] In practice, the flash controller 110, by executing the program code 112C via the microprocessor 112, can utilize its own internal components to perform various control operations, such as utilizing the control logic 114 to control access operations to the flash memory module 120 (e.g., access operations to at least one block or at least one page of data), utilizing the buffer memory 116 to perform required buffering operations, and utilizing the interface logic 118 to communicate with a host device 130.

[0041] In one embodiment, the memory device 100 can be a portable memory device (e.g., a memory card complying with the SD / MMC, CF, MS, XD standards), and the host device 130 can be an electronic device (e.g., a mobile phone, a notebook computer, a desktop computer, etc.) that can be connected to the memory device. In another embodiment, the memory device 100 can be disposed in an electronic device (e.g., a mobile phone, a notebook computer, a desktop computer, etc.), and the host device 130 can be a processor of the electronic device.

[0042] In the present embodiment, the encoding circuit 132 includes at least a Low-Density Parity Check code (LDPC code) encoder, and can generate a corresponding parity code from data received from the host device 130, wherein the generated parity code complies with a parity check matrix. Specifically, referring to Figure 2 , assume that the parity check matrix is a matrix of size c*t (e.g., c = 5, t = 48, or any other suitable values), and the parity check matrix can be divided into a left matrix M (of size c*(t-c)) and a right matrix K (of size c*c). To find a parity generation matrix corresponding to the parity check matrix, the inverse matrix K -1 of the matrix K can be found first, and then the inverse matrix K -1 is multiplied by the matrix M to obtain a matrix P, and the transpose matrix of the matrix P can be used as the parity generation matrix. In other words, after finding the transpose matrix of the matrix P, the encoding circuit 132 can multiply data received from the host device 130 by the transpose matrix of the matrix P to obtain a parity code corresponding to the data, and the encoder can then multiply the data and the parity code by the parity check matrix to determine whether the parity code is correct. For example, if the multiplication result is equal to "0", it is determined that the encoding is correct; otherwise, it is determined that the encoding is incorrect. After determining that the encoding is correct, the data and the corresponding parity code can be written into a page of data in the flash memory module 120.

[0043] It is noted that each cell of the check code check matrix is actually a block, and the block can be a square matrix (e.g., a 64*64 matrix or a 192*192 matrix), that is, the check code check matrix includes c*t blocks.

[0044] However, when the check code check matrix is a non-full rank check code check matrix, the rank of the inverse matrix K -1 is lower than the number of rows / columns of the inverse matrix K -1 , for example, the rank of the inverse matrix K -1 may be (c-x), where x is a positive integer that can be different according to different check code check matrices, for example, x=3, x=5, and the like. However, since the rank of the inverse matrix K -1 is lower than the number of rows / columns of the inverse matrix K -1 , the check code generated by the encoding circuit 132 includes some dependent bits, that is, bits that cannot be used for error correction. The encoding circuit 132 of the embodiment can store other auxiliary data using the addresses of the original dependent bits to avoid wasting memory space.

[0045] Referring to Figure 3 , which is a schematic diagram of the encoding circuit 132 according to an embodiment of the present application. As shown in Figure 3 , the encoding circuit 132 includes a cyclic redundancy check (CRC) encoder 310, a low-density parity-check code encoder 320, and an auxiliary data generation circuit 330, wherein the low-density parity-check code encoder 320 includes a local check code calculation circuit 322, a circulant convolution calculation circuit 324, and a compensation circuit 326. In the embodiment, the local check code calculation circuit 322 can be compared to the matrix M shown in Figure 2 , and the circulant convolution calculation circuit 324 is used to generate a content similar to the inverse matrix K -1 shown in Figure 2 . Since the local check code calculation circuit 322 and the circulant convolution calculation circuit 324 involve many complex circuit architectures and mathematical operations, the specific circuit architecture can refer to the Taiwan patent application (application number: 106141115) proposed by the same inventor, and in addition, the focus of the present application is not on the circuit design of the low-density parity-check code encoder 320, so the details of the local check code calculation circuit 322 and the circulant convolution calculation circuit 324 are not described here.

[0046] In Figure 3In the operation of the encoding circuit 132, first, the cyclic redundancy check encoder 310 performs cyclic redundancy check encoding on the data blocks to generate a cyclic redundancy check code; then, the local parity calculation circuit 322 and the cyclic convolution calculation circuit 324 in the low-density parity-check code encoder 320 sequentially perform encoding calculation on the data blocks and the cyclic redundancy check code to generate a parity code, wherein the parity code includes at least one dependent bit; at the same time, the auxiliary data generation circuit 330 generates auxiliary data according to the data blocks and / or the cyclic redundancy check code; then, the compensation circuit 326 uses the auxiliary data to replace at least one dependent bit of the parity code to generate an adjusted parity code; finally, the encoding circuit 132 writes the data blocks, the cyclic redundancy check code, and the adjusted parity code into a data page of a block in the flash memory module 120.

[0047] In an embodiment, the auxiliary data generated by the auxiliary data generation circuit 330 is an identification information (ID) of the data blocks, hash data, quality of service (QoS) information, a time stamp, or a logical / physical address; in another embodiment, the cyclic redundancy check code generated by the cyclic redundancy check encoder 310 includes a first part and a second part, wherein the first part is followed by the data blocks, and the second part is used as the auxiliary data to replace the dependent bit in the parity code; in another embodiment, the auxiliary data can also be the remainder obtained by dividing the number of bits with a value of "1" (or a value of "0") in the data blocks by a reference value, but the present application is not limited thereto.

[0048] Figure 4 A schematic diagram of the data blocks, the cyclic redundancy check code, and the adjusted parity code written into the flash memory module 120 is shown. As shown, the cyclic redundancy check code is followed by the data blocks, and the adjusted parity code is followed by the cyclic redundancy check code. The address of the dependent bit in the original parity code is shown in the diagonal line part, and the auxiliary data is used to replace the dependent bit in the original parity code to generate the adjusted parity code. Figure 4

[0049] In the embodiment shown in FIG. 1, the dependent bit in the parity code that does not have a correction effect is replaced by the auxiliary data that has an actual effect, so that more useful information can be added in the limited memory space to avoid waste of memory space. Figure 3 4

[0050] Figure 5 ​​​A flowchart of an encoding method according to an embodiment of the present invention. (See reference) Figures 1 to 4 Based on the relevant content disclosed in the instruction manual, the coding method process is as follows.

[0051] Step 500: Process begins.

[0052] Step 502: Perform Cyclic Redundancy Check (CRC) coding on multiple data blocks to generate a CRC code.

[0053] Step 504: Encode and calculate the multiple data blocks and the cyclic redundancy check code to generate a check code.

[0054] Step 506: Generate auxiliary data based on the plurality of data blocks and / or the cyclic redundancy check code.

[0055] Step 508: Use the auxiliary data to replace at least one dependent bit of the check code to generate an adjusted check code.

[0056] Step 510: Write the data block, the cyclic redundancy check code, and the adjusted check code together into a data page of a block in the flash memory module.

[0057] Figure 6 The diagram shown is a schematic representation of a decoding circuit 134 according to an embodiment of the present invention. Figure 6 As shown, the decoding circuit 134 includes a low-density parity check decoder 610 and a checking circuit 620. In the operation of the decoding circuit 134, firstly, in response to a read request from the master device 130, the low-density parity check decoder 610 reads data from a data page of a block in the flash memory module 120 and decodes the data to generate decoded data and a decoded checksum. The decoded data may be the data block shown in Figure 4 and a cyclic redundancy check (CRC) code, while the decoded checksum may be... Figure 4 The adjusted checksum. Next, the check circuit 620 obtains auxiliary data (such as...) from the decoded checksum. Figure 4 The shaded portion shown represents known information about the encoding circuit 132 and the decoding circuit 134, and auxiliary data is used to determine the integrity / correctness of the decoded data to generate a check result. In one embodiment, when the check result indicates that the integrity or correctness of the decoded data is normal, the microprocessor 112 transmits the decoded data to the main device 130.

[0058] In one embodiment, the checking circuit 620 can be a cyclic redundancy check decoder, wherein the checking circuit 620 obtains a first portion of the cyclic redundancy check code from the decoded data, the checking circuit 620 obtains a second portion of the cyclic redundancy check code (i.e. the auxiliary data) from the decoded check code, and the checking circuit 620 uses the first portion of the cyclic redundancy check code and the second portion of the cyclic redundancy check code to determine the integrity or correctness of the decoded data to generate the checking result. As mentioned above, since the decoded check code also includes a portion of the cyclic redundancy check code, the embodiment can have higher accuracy of the integrity / correctness checking when the number of bits of the cyclic redundancy check code is large.

[0059] Figure 7 A flowchart of the decoding method according to one embodiment of the present application. Refer to the related content disclosed in the Figure 4 , 6 and the specification, the flow of the decoding method is as follows.

[0060] Step 700: the flow starts.

[0061] Step 702: a data is read from a data page of a block in a flash memory module.

[0062] Step 704: the data is decoded to generate a decoded data and a decoded check code.

[0063] Step 706: an auxiliary data is obtained from the decoded check code.

[0064] Step 708: the correctness / integrity of the decoded data is determined according to the auxiliary data.

[0065] Briefly summarized, in the flash memory controller and the related encoding circuit and decoding circuit of the present application, the dependent bits in the check code originally generated by the encoding circuit are replaced by the auxiliary data having actual functions, so as to fully utilize the memory space to avoid wasting space. On the other hand, by adding the auxiliary data in the check code, the correctness / integrity checking in the decoding process can have higher accuracy.

[0066] The above descriptions are only the preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An encoding circuit used in a flash memory controller, characterized in that, Including: An auxiliary data generation circuit is used to receive multiple data blocks to generate auxiliary data for the multiple data blocks; as well as An encoder, coupled to the auxiliary data generation circuit, is used to encode the plurality of data blocks according to a check code check matrix to generate a check code, and to use the auxiliary data to replace a portion of the check code to generate an adjusted check code. The plurality of data blocks and the adjusted checksum are written into a flash memory; The check matrix is ​​a non-full-rank check matrix, and the portion of the check matrix consists of multiple bits that do not have error correction effect.

2. The encoding circuit as described in claim 1, characterized in that, The encoder is a low-density parity check encoder in the flash memory controller.

3. The encoding circuit as described in claim 1, characterized in that, It also includes: A cyclic redundancy check encoder is used to encode the plurality of data blocks to generate a cyclic redundancy check code; The auxiliary data generation circuit generates the auxiliary data based on a portion of the cyclic redundancy check code.

4. The encoding circuit as described in claim 3, characterized in that, The encoder encodes the plurality of data blocks together with the cyclic redundancy check (CRC) code to generate the check code, wherein a portion of the CRC code is used to replace the portion of the check code to generate the adjusted check code.

5. A flash memory controller, the flash memory controller being used to access a flash memory module, and the flash memory controller being characterized in that it comprises: A memory used to store program code; A microprocessor is used to execute the program code to control access to the flash memory module; as well as An encoding circuit includes: An auxiliary data generation circuit is used to receive multiple data blocks to generate auxiliary data for the multiple data blocks; as well as An encoder, coupled to the auxiliary data generation circuit, is used to encode the plurality of data blocks according to a check code check matrix to generate a check code, and to use the auxiliary data to replace a portion of the check code to generate an adjusted check code. The plurality of data blocks and the adjusted checksum are written to the flash memory module; The check matrix is ​​a non-full-rank check matrix, and the portion of the check matrix consists of multiple bits that do not have error correction effect.

6. The flash memory controller as described in claim 5, characterized in that, The encoder is a low-density parity check encoder in the flash memory controller.

7. The flash memory controller as claimed in claim 5, characterized in that, It also includes: A cyclic redundancy check encoder is used to encode the plurality of data blocks to generate a cyclic redundancy check code; The auxiliary data generation circuit generates the auxiliary data based on a portion of the cyclic redundancy check code.

8. The flash memory controller as claimed in claim 7, characterized in that, The encoder encodes the plurality of data blocks together with the cyclic redundancy check (CRC) code to generate the check code, wherein a portion of the CRC code is used to replace the portion of the check code to generate the adjusted check code.

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