Hard mask structure and manufacturing method thereof, and semiconductor device

Abstract

The present invention provides a hard mask structure, a manufacturing method thereof, and a semiconductor device; the hard mask structure comprises an etching stopper layer (100), a metal hard mask layer (200) covering the etching stopper layer (100), and at least one buffer layer (300) covering the metal hard mask layer (200); the buffer layer (300) is made of at least one of Si, SiC, SiCN, SiOC, SiOCN, and SiN. The hard mask structure, the manufacturing method thereof, and the semiconductor device of the present invention form a buffer layer by covering the metal hard mask layer, thereby preventing the metal hard mask layer from being damaged, thereby solving the problem of first groove mismatch.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a hard mask structure and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] TiN hard mask is often used in multiple lithography technology. Figure 1 As shown, the hard mask structure includes an etch stop layer 100, a metal hard mask layer 200, and a cap layer 210. First, a photoresist 900 is applied over the cap layer. A predetermined pattern is formed on the left side of the cap layer through photolithography, etching, and photoresist stripping. The above steps are then repeated to obtain a multi-lithography hard mask structure.

[0003] In addition, the hard mask can also be used in self-aligned double patterning (SADP) technology. Figure 2 As shown, the hard mask structure includes an etch stop layer 100, a metal hard mask layer 200, and a cap layer 210. First, a core structure 230 is formed on the cap layer 210, and then spacers 220 are formed by deposition and etching. After removing the core structure 230, a mask pattern is obtained and etched, and finally the cap layer 210 is formed into a predetermined pattern.

[0004] However, in multiple photolithography, when etching the cap layer 210, grooves 240 are formed in the metal hard mask layer 200, resulting in a significant mismatch between the designed dimensions of the grooves 240. Furthermore, the subsequent ashing step after etching can cause oxidation damage to the metal hard mask layer 200. In particular, ashing in subsequent steps can cause even more severe oxidation damage to the grooves 240 formed in the previous step. Similarly, in self-aligned double patterning, etching the cap layer also forms grooves 240 in the metal hard mask layer 200, resulting in a mismatch between the designed dimensions of the pattern. Summary of the Invention

[0005] The purpose of the present invention is to address the above technical problems and to provide a hard mask structure, a manufacturing method thereof, and a semiconductor device.

[0006] The technical solution of the present invention to solve the technical problem is:

[0007] The present invention provides a hard mask structure, which includes an etch stop layer, a metal hard mask layer covering the etch stop layer, and at least one buffer layer covering the metal hard mask layer;

[0008] The buffer layer is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN.

[0009] In the hard mask structure of the present invention, the thickness of the buffer layer is greater than

[0010] In the above-mentioned hard mask structure of the present invention, the hard mask structure further includes a cap layer covering the buffer layer, and the etching selectivity between the cap layer and the buffer layer is greater than 3.

[0011] In the above-mentioned hard mask structure of the present invention, the hard mask structure further includes a cap layer covering the buffer layer, and the hard mask structure satisfies the following characteristics:

[0012] D c / D b ≤S

[0013] Among them, D c The thickness of the cap layer etched during over-etching; D b is the thickness of the buffer layer; S is the etching selectivity ratio of the cap layer and the buffer layer.

[0014] The present invention also proposes a use of a hard mask structure, which includes an etch stop layer, a metal hard mask layer covering the etch stop layer, and at least one buffer layer covering the metal hard mask layer; the use of the hard mask structure is to use the buffer layer to prevent the metal hard mask layer from being etched, so as to control the etching operation to stop at the buffer layer.

[0015] The present invention also provides a method for manufacturing the hard mask structure as described above, comprising the following steps:

[0016] Step S1, providing a semiconductor substrate having an etch stop layer, a metal hard mask layer, a buffer layer and a cap layer formed thereon;

[0017] Step S2, forming a preset mask pattern layer above the cap layer of the semiconductor substrate;

[0018] Step S3, removing excess material of the cap layer by etching according to a preset mask pattern layer to form a cap layer pattern, and controlling the etching to stop at the buffer layer;

[0019] Step S4: removing the preset mask pattern layer.

[0020] In the method for manufacturing the hard mask structure of the present invention, step S2 is: covering the cap layer with a photoresist and removing excess photoresist material by photolithography to form a preset mask pattern layer on the cap layer;

[0021] The step S3 is: according to the preset mask pattern layer, a first groove is opened on the hard mask structure by etching, which penetrates the cap layer and stops at the buffer layer, to form a cap layer pattern;

[0022] The method for manufacturing a hard mask structure further includes step S5: repeating steps S2, S3 and S4 at least once.

[0023] In the manufacturing method of the hard mask structure of the present invention, an oxide layer is formed on the exposed area of the buffer layer, and the thickness of the oxide layer is The thickness of the oxide layer is smaller than the thickness of the metal hard mask layer.

[0024] In the method for manufacturing the hard mask structure of the present invention, step S2 specifically comprises: first forming a mandrel structure above the cap layer, wherein the mandrel structure includes a core structure and a spacer layer formed overlying the core structure; then etching the spacer layer to retain only a portion of the spacer layer disposed on the sidewalls of the core structure, removing the core structure to form a predetermined mask pattern layer on the cap layer;

[0025] The step S3 is: according to the preset mask pattern layer, a second groove is opened on the hard mask structure by etching, which penetrates the cap layer and stops at the buffer layer, so as to form a cap layer pattern.

[0026] In the above-mentioned method for manufacturing the hard mask structure of the present invention, the etching in step S3 is dry etching, and the etching gas is at least one of C4F6 and O2.

[0027] The present invention also provides a semiconductor device, which is manufactured using the hard mask structure described above, or using the manufacturing method described above.

[0028] The hard mask structure, manufacturing method, and semiconductor device of the present invention employ a buffer layer formed over the metal hard mask layer to protect the metal hard mask layer from damage, thereby resolving the problem of mismatched first grooves. The hard mask structure, manufacturing method, and semiconductor device of the present invention are novel in design and highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0030] Figure 1 A schematic diagram of a process state of an existing double lithography technology is shown;

[0031] Figure 2 A schematic diagram of the process state of an existing self-aligned dual imaging technology is shown;

[0032] Figure 3 FIG2 shows a schematic structural diagram of a hard mask structure according to a preferred embodiment of the present invention;

[0033] Figure 4 This is the final structure diagram obtained using the LELE scheme;

[0034] Figure 5 Shown Figure 4 A flow chart of a method for manufacturing a hard mask structure is shown;

[0035] Figure 6 FIG. 4 shows a final hard mask structure obtained by SADP;

[0036] Figure 7 Shown Figure 6 Flowchart of a method for manufacturing a hard mask structure is shown. DETAILED DESCRIPTION

[0037] In order to make the technical objectives, technical solutions and technical effects of the present invention clearer and to facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 3 As shown, Figure 3 FIG2 is a schematic diagram of a hard mask structure according to a preferred embodiment of the present invention. The hard mask structure includes an etch stop layer 100, a metal hard mask layer 200 covering the etch stop layer 100, and at least one buffer layer 300 covering the metal hard mask layer 200.

[0039] Here, multiple layers of buffer layer 300 may be provided as required, such as two layers, three layers, four layers, etc.

[0040] The metal hard mask layer 200 is a TiN layer. The buffer layer 300 is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN.

[0041] Furthermore, the thickness of the buffer layer 300 is greater than

[0042] Furthermore, if Figure 4 As shown, Figure 4 The final structure obtained using the LELE scheme is shown in FIG. This hard mask structure is used in photolithography and includes an etch stop layer 100, a metal hard mask layer 200 covering the etch stop layer 100, at least one buffer layer 300 covering the metal hard mask layer 200, and a cap layer covering the buffer layer 300.

[0043] exist Figure 4 In the embodiment, the etching selectivity of the cap layer and the buffer layer 300 is greater than 3. By selecting appropriate cap layer and buffer layer and combining etching process means, the etching selectivity of the cap layer and the buffer layer is ensured to be greater than 3, thereby ensuring etching quality.

[0044] The cap layer material is a nitrogen-free material, and can be selected from Si, SiC, SiOC, SiO 2 , tetraethoxysilane (TEOS), etc. The cap layer can also be a dielectric anti-reflective coating (DARC) 400 .

[0045] In another embodiment, the hard mask structure further includes a cap layer covering the buffer layer 300 , and the hard mask structure satisfies the following characteristics:

[0046] D c / D b ≤S

[0047] Among them, D c The thickness of the cap layer etched during over-etching; D b is the thickness of the buffer layer; S is the etching selectivity ratio of the cap layer and the buffer layer 300.

[0048] During the fabrication of hardmask structures, overetching is typically used to prevent gaps in the cap layer's through-holes. However, overetching must also ensure that the buffer layer is fully penetrated, which could damage the metal hardmask layer. Therefore, by defining the buffer layer thickness and the relationship between Dc and Db, we ensure that even if a partial cavity forms in the buffer layer, oxidation of the metal hardmask layer will not occur.

[0049] The buffer layer 300 is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN.

[0050] Furthermore, the thickness of the buffer layer 300 is greater than The thickness of the dielectric anti-reflective coating 400 is The etching selectivity of the dielectric anti-reflective coating 400 / buffer layer 300 is greater than 3.

[0051] Furthermore, the dielectric anti-reflective coating 400 is covered with a multilayer photoresist 900. The multilayer photoresist 900 is developed to address some shortcomings of the single-layer photoresist lithography process. Using the multilayer photoresist 900 process for lithography can obtain better resolution and the side of the photoresist after lithography is steep and the cross-sectional shape is approximately rectangular.

[0052] Furthermore, the present invention also provides a method for manufacturing a hard mask structure, comprising the following steps:

[0053] Step S1, providing a semiconductor substrate having an etch stop layer 100, a buffer layer 300 and a cap layer formed thereon;

[0054] Step S2, forming a preset mask pattern layer above the cap layer of the semiconductor substrate;

[0055] Step S3, removing excess material of the cap layer by etching according to a preset mask pattern layer to form a cap layer pattern, and controlling the etching to stop at the buffer layer 300;

[0056] Step S4: removing the preset mask pattern layer.

[0057] Specifically, if Figure 5 As shown, Figure 5 Shown Figure 4 The flowchart of the method for manufacturing a hard mask structure is shown. The method for manufacturing a hard mask structure includes the following steps:

[0058] Step S1, providing a semiconductor substrate having an etch stop layer 100, a metal hard mask layer 200, a buffer layer 300 and a cap layer formed thereon;

[0059] In this embodiment, the cap layer is a dielectric anti-reflective coating 400;

[0060] Step S2: covering the cap layer with a photoresist 900 and removing excess material of the photoresist 900 by photolithography technology to form a preset mask pattern layer on the cap layer;

[0061] Step S3: A first groove 800 is opened on the hard mask structure by etching according to a preset mask pattern layer, penetrating the cap layer and stopping at the buffer layer 300, to form a cap layer pattern;

[0062] Step S4, removing the preset mask pattern layer;

[0063] Step S5: Repeat steps S2, S3 and S4 once.

[0064] Furthermore, after step S5, the method for manufacturing the hard mask structure further comprises: forming an oxide layer on the exposed area of the buffer layer 300, wherein the thickness of the oxide layer is The thickness of the oxide layer is smaller than that of the metal hard mask layer 200 .

[0065] The buffer layer 300 is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN.

[0066] Furthermore, the thickness of the buffer layer 300 is greater than The thickness of the dielectric anti-reflective coating 400 is The etching selectivity of the dielectric anti-reflective coating 400 / buffer layer 300 is greater than 3.

[0067] Furthermore, the oxide layer is formed when the exposed area of the buffer layer is oxidized during the manufacturing process.

[0068] Furthermore, if Figure 6 As shown, Figure 6 The final hard mask structure produced by SADP is shown. This hard mask structure is used in the self-aligned double patterning technique and includes an etch stop layer 100, a metal hard mask layer 200 covering the etch stop layer 100, a buffer layer 300 covering the metal hard mask layer 200, and a cap layer 410 covering the buffer layer 300.

[0069] The buffer layer 300 is made of at least one of Si, SiC, SiCN, SiOC, SiOCN, and SiN. The cap layer is a nitrogen-free material selected from Si, SiC, SiOC, SiO2, tetraethoxysilane (TEOS), and the like. The cap layer can also be a dielectric anti-reflective coating (DARC) 400.

[0070] Furthermore, the thickness of the buffer layer 300 is greater than

[0071] Furthermore, a core structure 420 is provided on the cap layer 410. The etching selectivity of the cap layer 410 / buffer layer 300 is greater than 3.

[0072] like Figure 7 As shown, Figure 7 Shown Figure 6 The flowchart of the method for manufacturing a hard mask structure is shown. The method for manufacturing a hard mask structure includes the following steps:

[0073] Step S1, providing a semiconductor substrate having an etch stop layer 100, a metal hard mask layer 200, a buffer layer 300 and a cap layer 410 formed thereon;

[0074] Step S2: forming a mandrel structure on the cap layer 410, wherein the mandrel structure includes a core structure 420 and a spacer layer 910 formed overlying the core structure 420; then etching the spacer layer 910 to retain only the portion of the spacer layer 910 disposed on the sidewalls of the core structure 420, removing the core structure 420 to form a predetermined mask pattern layer on the cap layer 410;

[0075] Step S3 : A second groove 920 penetrating the cap layer 410 and stopping at the buffer layer 300 is opened on the hard mask structure by etching according to the preset mask pattern layer to form a cap layer pattern.

[0076] In this step, the etching is dry etching, and the etching gas is at least one of C4F6 or O2.

[0077] Step S4: removing the preset mask pattern layer.

[0078] The buffer layer 300 is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN. Further, the thickness of the buffer layer 300 is greater than The etching selectivity of the cap layer 410 / buffer layer 300 is greater than 3.

[0079] The buffer layer 300 prevents the metal hard mask layer 200 from being damaged, thereby solving the mismatch problem of the first groove 800 .

[0080] In the present invention, because the cap layer is typically made of a silicon-rich material, it is difficult to achieve a high etch selectivity between the cap layer and the buffer layer 300. However, through extensive experiments, the inventors found that the selectivity of the cap layer / buffer layer 300 reached 5.67 after the gas was tuned to C4F6 / O2, fully meeting all requirements of the hard mask structure manufacturing process.

[0081] In the embodiment of the present invention, comparative groups 1 and 2 were set up. The comparative groups used the above-mentioned multiple photolithography technology. Step S5 was a repetition of steps S2, S3, and S4. The etching in step S3 was dry etching. Different comparative groups used different etching gases, as shown in Table 1.

[0082] Table 1

[0083]

[0084] The selectivity of CF4 / CHF3 / O2 is lower than that of C4F6 / O2, mainly because a high F / C ratio increases the etching rate (nm / min) of silicon-containing materials, especially when both the upper and lower layers contain silicon, which is more detrimental to improving the selectivity. Therefore, C4F6 is preferred. On the one hand, it can reduce the F / C ratio. On the other hand, the C4F6 structure has a long carbon chain, which can effectively reduce the etching rate. At the same time, by adding O2, the etching rate may drop too much when the F / C ratio is reduced, which may lead to incomplete etching. Therefore, appropriate O2 can help dissociate F and facilitate etching.

[0085] Furthermore, the present invention also proposes a use of a hard mask structure, which includes an etching stop layer 100, a metal hard mask layer 200 covering the etching stop layer 100, and at least one buffer layer 300 covering the metal hard mask layer 200; the use of the hard mask structure is to use the buffer layer 300 to prevent the metal hard mask layer 200 from being etched, so as to control the etching operation to stop at the buffer layer 300.

[0086] The present invention also provides a semiconductor device, which is manufactured using the hard mask structure described above, or using the manufacturing method described above.

[0087] The hard mask structure, manufacturing method, and semiconductor device of the present invention employ a buffer layer formed over the metal hard mask layer to protect the metal hard mask layer from damage, thereby resolving the problem of mismatched first grooves. The hard mask structure, manufacturing method, and semiconductor device of the present invention are novel in design and highly practical.

[0088] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A hard mask structure, characterized in that: The hard mask structure comprises an etch stop layer (100), a metal hard mask layer (200) covering the etch stop layer (100), and at least one buffer layer (300) covering the metal hard mask layer (200); The buffer layer (300) is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN; The metal hard mask layer (200) is a TiN layer; The thickness of the buffer layer (300) is greater than The hard mask structure further comprises a cap layer covering the buffer layer (300), wherein an etching selectivity ratio between the cap layer and the buffer layer (300) is greater than 3; The hard mask structure meets the following characteristics: D c / D b ≤S Among them, D c The thickness of the cap layer etched during over-etching; D b is the thickness of the buffer layer; S is the etching selectivity ratio of the cap layer and the buffer layer (300).

2. A method for manufacturing a hard mask structure according to claim 1, characterized in that: The following steps are involved: Step S1, providing a semiconductor substrate formed with an etching stop layer (100), a metal hard mask layer (200), a buffer layer (300) and a cap layer; Step S2, forming a preset mask pattern layer above the cap layer of the semiconductor substrate; Step S3, removing excess material of the cap layer by etching according to a preset mask pattern layer to form a cap layer pattern, and controlling the etching to stop at the buffer layer (300); Step S4, removing the preset mask pattern layer; The buffer layer (300) is made of at least one of Si, SiC, SiCN, SiOC, SiOCN and SiN; The metal hard mask layer (200) is a TiN layer; The thickness of the buffer layer (300) is greater than The hard mask structure further comprises a cap layer covering the buffer layer (300), wherein an etching selectivity ratio between the cap layer and the buffer layer (300) is greater than 3; The hard mask structure meets the following characteristics: D c / D b ≤S Among them, D c The thickness of the cap layer etched during over-etching; D b is the thickness of the buffer layer; S is the etching selectivity ratio of the cap layer and the buffer layer (300); The etching in step S3 is dry etching, and the etching gas is a mixture of C4F6 and O2; The method further comprises: An oxide layer is formed on the exposed area of the buffer layer (300), wherein the thickness of the oxide layer is The thickness of the oxide layer is smaller than the thickness of the metal hard mask layer (200).

3. A method for manufacturing a hard mask structure according to claim 2, characterized in that: The step S2 comprises: covering the cap layer with a photoresist (900), and removing excess material of the photoresist (900) by photolithography technology to form a preset mask pattern layer on the cap layer; The step S3 is: according to the preset mask pattern layer, a first groove (800) is opened on the hard mask structure by etching, which penetrates the cap layer and stops at the buffer layer (300), so as to form a cap layer pattern; The method for manufacturing a hard mask structure further includes step S5: repeating steps S2, S3 and S4 at least once.

4. A method for manufacturing a hard mask structure according to claim 2, characterized in that: The step S2 specifically comprises: first forming a mandrel structure above the cap layer, wherein the mandrel structure includes a core structure (420) and a spacer layer (910) formed and covered on the core structure (420); then etching the spacer layer (910) to retain only a portion of the spacer layer (910) disposed on the sidewall of the core structure (420), and removing the core structure (420) to form a preset mask pattern layer on the cap layer; The step S3 is: according to the preset mask pattern layer, a second groove (920) is opened on the hard mask structure by etching, which penetrates the cap layer and stops at the buffer layer (300), so as to form a cap layer pattern.

5. A semiconductor device, characterized in that: The hard mask structure according to claim 1 is used, or the manufacturing method according to any one of claims 2 to 4 is used for manufacturing.

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