Method for forming semiconductor device

Abstract

The present invention discloses a method for forming a semiconductor device, comprising providing a substrate having a first region and a second region surrounding the first region, wherein the first region includes a first active region and a first gate on the first active region; disposing a dummy pattern on the substrate in the second region surrounding the first region; disposing a photoresist pattern on the substrate, covering the second region and including an opening exposing the first region; performing an ion implantation process to implant dopants through the opening into the first active region in the first region that is not covered by the first gate, thereby forming a doped region in the first active region; performing a photoresist stripping process to remove the photoresist pattern by using an SPM solution at a temperature greater than or equal to 0.5 degrees Celsius; and cleaning the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor element. Background Art

[0002] As is known, in semiconductor manufacturing processes, when performing an ion implantation process, such as a lightly doped drain (LDD) ion implantation step, it is usually necessary to cover areas of the semiconductor substrate where ion implantation is not desired with a photoresist pattern.

[0003] When the photoresist pattern is thick, the high-dose LDD ion implantation step described above can form a crust on the surface of the photoresist pattern. This crust is prone to cracking and causing defects. In particular, the crust formed on the sidewalls of the photoresist pattern is most likely to cause defects such as pattern collapse during the subsequent photoresist pattern removal process, affecting production yield. Summary of the Invention

[0004] The main object of the present invention is to provide an improved method for forming a semiconductor device to solve the above-mentioned deficiencies and shortcomings of the prior art.

[0005] One aspect of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having a first region and a second region surrounding the first region, wherein the first region comprises at least one first active region and a first gate on the first active region; providing a dummy pattern on the substrate in the second region surrounding the first region; providing a photoresist pattern on the substrate, wherein the photoresist pattern covers the second region and comprises an opening exposing the first region; performing an ion implantation process to implant dopants into the first active region not covered by the first gate in the first region through the opening, thereby forming a doped region in the first active region; performing a photoresist stripping process at a temperature greater than or equal to 0.5°C. The photoresist pattern is removed by using a sulfuric acid and hydrogen peroxide mixture (SPM) solution at a temperature of 1000 nm; and a cleaning process is performed on the substrate.

[0006] According to an embodiment of the present invention, the second region includes at least one second active region and a second gate on the at least one second active region.

[0007] According to an embodiment of the present invention, the photoresist pattern covers the dummy pattern, the second region, the at least one second active region and the second gate.

[0008] According to an embodiment of the present invention, the dummy pattern is disposed between the at least one first active region and the at least one second active region.

[0009] According to an embodiment of the present invention, a hard crust is generated on the photoresist pattern during the ion implantation process, and the dummy pattern prevents the hard crust from adhering to the second gate during the photoresist stripping process.

[0010] According to an embodiment of the present invention, the SPM solution comprises a mixture ratio between of H2SO4 and H2O2.

[0011] According to an embodiment of the present invention, the width of the dummy pattern is greater than 120 nm.

[0012] According to an embodiment of the present invention, the width of the dummy pattern is greater than 150 nm.

[0013] According to an embodiment of the present invention, a distance between the first gate and a sidewall of the photoresist pattern surrounding the opening is greater than 1000 angstroms.

[0014] According to an embodiment of the present invention, a sidewall of the photoresist pattern surrounding the opening includes an inclined upper sidewall portion.

[0015] According to an embodiment of the present invention, the ion implantation process is performed at a rate greater than 1E14 / cm 2 A lightly doped drain (LDD) implantation process is performed with a dose of , wherein the doped region is an LDD region.

[0016] According to an embodiment of the present invention, the cleaning process is performed by using a wet cleaning solution comprising a mixture of ammonium hydroxide, hydrogen peroxide and water.

[0017] According to an embodiment of the present invention, the volume ratio of ammonium hydroxide, hydrogen peroxide and water is about

[0018] According to an embodiment of the present invention, the dummy pattern is a strip-shaped polysilicon pattern.

[0019] According to an embodiment of the present invention, the dummy pattern is disposed on a trench isolation region.

[0020] According to an embodiment of the present invention, the substrate is a semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 4 A schematic diagram illustrating a method of forming a semiconductor device; wherein,

[0022] Figure 1 A top view illustrating the arrangement of a dummy pattern and a photoresist pattern on a semiconductor substrate;

[0023] Figure 2 for Figure 1 A sectional view along the tangent line II';

[0024] Figure 3 A schematic diagram illustrating an LDD ion implantation process;

[0025] Figure 4 Schematic diagram illustrating a photoresist stripping process.

[0026] Description of main component symbols

[0027] 100 base

[0028] 102 trench isolation area

[0029] 106 doping region

[0030] 120 bottom anti-reflective layer

[0031] 200 Ion Implantation Process

[0032] 230 Hard Shell

[0033] AA1 first active area

[0034] AA2 Second active area

[0035] d1, d2, d3 distances

[0036] DG dummy gate

[0037] DP1 dummy pattern

[0038] DP2 dummy pattern

[0039] OP Opening

[0040] PG1 first gate

[0041] PG2 Second Gate

[0042] PR photoresist pattern

[0043] R1 First Area

[0044] R2 Second Area

[0045] S sidewall

[0046] S1 sidewall

[0047] S2 vertical sidewall

[0048] S3 inclined upper side wall section

[0049] W1, W2 width

[0050] θ angle DETAILED DESCRIPTION

[0051] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them.

[0052] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0053] See also Figures 1 to 4 , which illustrates a method of forming a semiconductor device, wherein Figure 1 FIG. 1 is a top view schematically illustrating a process of providing a dummy pattern on a semiconductor substrate for performing an ion implantation process according to an embodiment of the present invention. Figure 2 for Figure 1 The cross-sectional view along the tangent line II' is shown in FIG. Figure 3 The LDD ion implantation process is illustrated. Figure 4 A photoresist stripping process is illustrated.

[0054] like Figure 1 and Figure 2 As shown, a substrate 100 is first provided, for example, a semiconductor substrate, having a first region R1 and a second region R2 surrounding the first region R1. According to one embodiment of the present invention, for example, the first region R1 can be an input / output (IO) circuit area, but is not limited thereto. According to one embodiment of the present invention, for example, the second region R2 can be a logic core circuit area, but is not limited thereto. According to an embodiment of the present invention, the first region R1 includes at least one first active region AA1 and a first gate PG1 on the first active region AA1. It should be understood that, for simplicity of description, Figure 1 The first active area AA1 shown in the figure is merely an example, and the number and layout of the first active area AA1 are not intended to limit the present invention.

[0055] According to an embodiment of the present invention, for example, the first active area AA1 may be a fin-type structure extending along the reference X-axis direction, but is not limited thereto. According to an embodiment of the present invention, for example, the first gate PG1 may be a polysilicon fine line pattern extending across the first active area AA1 and along the reference Y-axis direction. According to an embodiment of the present invention, for example, a dummy gate DG may be provided at the end of the first active area AA1, but is not limited thereto.

[0056] According to an embodiment of the present invention, the second region R2 may include at least one second active region AA2 and a second gate PG2 on the at least one second active region AA2. Figure 1 The second active area AA2 shown is for illustrative purposes only, and its number and layout are not intended to limit the present invention. According to an embodiment of the present invention, for example, the second active area AA2 may be a fin-shaped structure extending along the reference X-axis, but is not limited thereto. According to an embodiment of the present invention, for example, the second gate PG2 may be a polysilicon fine line pattern extending across the second active area AA2 and along the reference Y-axis. According to an embodiment of the present invention, the polysilicon fine line pattern may be replaced by a metal gate in subsequent fabrication processes.

[0057] According to an embodiment of the present invention, a dummy pattern DP1 and a dummy pattern DP2 may be provided on the substrate 100 within the second region R2 surrounding the first region R1. According to an embodiment of the present invention, the dummy patterns DP1 and DP2 are provided between the first active region AA1 and the second active region AA2. According to an embodiment of the present invention, the dummy pattern DP1 may be a strip pattern extending along the reference X-axis direction, and the dummy pattern DP2 may be a strip pattern extending along the reference Y-axis direction. According to an embodiment of the present invention, the strip pattern may be a strip polysilicon pattern, but is not limited thereto. According to an embodiment of the present invention, the dummy pattern DP1 and the dummy pattern DP2 may be connected to each other and form a ring-shaped or square-shaped pattern that continuously surrounds the first region R1.

[0058] According to an embodiment of the present invention, the width W1 of the dummy pattern DP1 is greater than 120 nm, preferably greater than 150 nm. According to an embodiment of the present invention, the width W2 of the dummy pattern DP2 is greater than 120 nm, preferably greater than 150 nm. According to an embodiment of the present invention, the width W1 of the dummy pattern DP1 may be equal to the width W2 of the dummy pattern DP2. In other embodiments, the width W1 of the dummy pattern DP1 may not be equal to the width W2 of the dummy pattern DP2. According to an embodiment of the present invention, for example, the distance d1 between the dummy pattern DP1 and the first gate PG1 may be greater than 1500 angstroms. According to an embodiment of the present invention, for example, the distance d2 between the dummy pattern DP2 and the first gate PG1 may be greater than 1500 angstroms.

[0059] According to an embodiment of the present invention, Figure 2 As shown, for example, the dummy patterns DP1 and DP2 may be disposed on a trench isolation region 102. For example, the trench isolation region 102 may be a shallow trench isolation (STI) region.

[0060] According to an embodiment of the present invention, in order to facilitate the subsequent ion implantation process, for example, a lightly doped drain (LDD) implantation process, to implant a predetermined dopant into the first active region AA1 within the first region R1, it is necessary to provide a photoresist pattern PR on the substrate 100, wherein the photoresist pattern PR substantially covers the second region R2 and includes an opening OP exposing the first region R1. The steps for forming the photoresist pattern PR are well known in the art, so the details thereof are not described separately. For example, the steps for forming the photoresist pattern PR typically include, but are not limited to, processes such as photoresist spin coating, baking, exposure, development, and cleaning. According to an embodiment of the present invention, the photoresist pattern PR covers the dummy patterns DP1 and DP2, the second region R2, the second active region AA2, and the second gate PG2.

[0061] like Figure 2 As shown, typically, there is a bottom anti-reflective layer 120 below the photoresist pattern PR. For example, the thickness of the bottom anti-reflective layer 120 can be between 3600 angstroms and 3700 angstroms. According to an embodiment of the present invention, the bottom anti-reflective layer 120 typically has a sidewall S1 that is approximately perpendicular to the surface of the substrate 100 and extends upward to the sidewall S of the photoresist pattern PR, and includes a vertical sidewall S2 and an inclined upper sidewall portion S3. According to an embodiment of the present invention, an angle θ is formed between the inclined upper sidewall portion S3 and the sidewall S1, wherein the angle θ can be greater than 30 degrees, for example, greater than 35 degrees. According to an embodiment of the present invention, the distance d3 between the first gate PG1 and the sidewall S of the photoresist pattern PR is preferably greater than 1000 angstroms.

[0062] like Figure 3 As shown, the method of forming a semiconductor device of the present invention includes: performing an ion implantation process 200 to implant dopants into the first active region AA1 in the first region R1 that is not covered by the first gate PG1 through the opening OP of the photoresist pattern PR, thereby forming a doped region 106 in the first active region AA1. According to an embodiment of the present invention, for example, the ion implantation process 200 is performed at a rate greater than 1E14 / cm 2 The oblique-angle LDD implantation process is performed with a dose of 100, wherein the doped region 106 is an LDD region. According to an embodiment of the present invention, when the ion implantation process 200 is performed, a hard crust 230 is generated on the photoresist pattern PR.

[0063] As previously mentioned, the hard crust formed on the photoresist pattern PR is prone to cracking, resulting in defects. In particular, the hard crust 230 formed on the sidewalls S2 and S3 of the photoresist pattern PR is most likely to cause defects such as pattern collapse during the subsequent removal of the photoresist pattern PR, affecting production yield. The present invention specifically addresses this problem. By providing dummy patterns DP1 and DP2 on the substrate 100, the present invention prevents the hard crust 230 from adhering to the second gate PG2 during the photoresist stripping process.

[0064] like Figure 4 As shown, a photoresist stripping process is then performed to remove the photoresist pattern PR and the underlying bottom anti-reflective layer 120. According to an embodiment of the present invention, the photoresist stripping process is a fully wet process, that is, no dry step, such as oxygen plasma, is used in the photoresist removal process to avoid dopant loss in the LDD region.

[0065] According to an embodiment of the present invention, for example, the photoresist stripping process can be performed at a temperature greater than or equal to Celsius. According to an embodiment of the present invention, for example, the SPM solution comprises a mixture ratio between Finally, the substrate 100 may be subjected to a cleaning process. According to an embodiment of the present invention, for example, the cleaning process is performed by using a wet cleaning solution containing a mixture of ammonium hydroxide, hydrogen peroxide, and water. According to an embodiment of the present invention, for example, the volume ratio of ammonium hydroxide, hydrogen peroxide, and water is about

[0066] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: Providing a substrate having a first region and a second region surrounding the first region, wherein the first region includes at least one first active region and a first gate on the first active region, and the second region includes at least one second active region and a second gate on the at least one second active region; providing a dummy pattern on the substrate in the second region around the first region, wherein the dummy pattern is provided between the at least one first active region and the at least one second active region; providing a photoresist pattern on the substrate, wherein the photoresist pattern covers the second region and includes an opening exposing the first region; Performing an ion implantation process to implant dopants into the first active region in the first region that is not covered by the first gate through the opening, thereby forming a doped region in the first active region; Perform photoresist stripping process at a temperature higher than or equal to 120 degrees Celsius removing the photoresist pattern by using a mixed solution of sulfuric acid and hydrogen peroxide at 190 degrees; as well as The substrate is cleaned.

2. The method according to claim 1, wherein The photoresist pattern covers the dummy pattern, the second region, the at least one second active region, and the second gate.

3. The method according to claim 1, wherein a hard crust is generated on the photoresist pattern when the ion implantation process is performed, and wherein the dummy pattern prevents the hard crust from being attached to the second gate when the photoresist stripping process is performed.

4. The method according to claim 1, wherein The sulfuric acid and hydrogen peroxide mixed solution comprises a mixing ratio of 2:1 9:1 ​​H2SO4 and H2O2.

5. The method according to claim 1, wherein The width of the dummy pattern is greater than 120 nm.

6. The method according to claim 1, wherein The width of the dummy pattern is greater than 150 nm.

7. The method according to claim 1, wherein A distance between the first gate and a sidewall of the photoresist pattern surrounding the opening is greater than 1000 angstroms.

8. The method according to claim 1, wherein A sidewall of the photoresist pattern surrounding the opening includes an inclined upper sidewall portion.

9. The method according to claim 1, wherein: The ion implantation process is greater than 1E14 / cm 2 A lightly doped drain implantation process is performed with a dose of , wherein the doped region is a lightly doped drain region.

10. The method according to claim 1, wherein The cleaning process is performed by using a wet cleaning solution including a mixture of ammonium hydroxide, hydrogen peroxide, and water.

11. The method according to claim 10, wherein: The volume ratio of ammonium hydroxide, hydrogen peroxide and water is 1:1 10:10 100.

12. The method according to claim 1, wherein The dummy pattern is a stripe-shaped polysilicon pattern.

13. The method according to claim 1, wherein The dummy pattern is disposed on the trench isolation region.

14. The method according to claim 1, wherein The substrate is a semiconductor substrate.

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