A method for manufacturing a semiconductor device

Abstract

The present invention discloses a manufacturing method of a semiconductor device, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a groove; depositing a shielding dielectric layer on the bottom and sidewalls of the groove; forming a shielding gate layer in the groove; etching to remove a part of the shielding gate layer, the upper surface of the shielding gate layer being lower than the upper surface of the shielding dielectric layer; etching the shielding dielectric layer, the upper surface of the shielding dielectric layer being lower than the upper surface of the shielding gate layer; performing topography treatment on the shielding gate layer by dry etching so that both ends of the shielding gate layer are not higher than the shielding dielectric layer; forming a gate dielectric layer in the groove; filling the groove with a gate material to form a gate material layer, the upper surface of the gate material layer being higher than the upper surface of the semiconductor substrate; planarizing the gate material layer so that the upper surface of the gate material layer is flush with the upper surface of the semiconductor substrate. According to the manufacturing method provided by the present invention, the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a method for manufacturing a semiconductor device. Background Art

[0002] Shield Gate Trench (SGT) devices can achieve both low on-resistance (Rdson) and low reverse recovery capacitance (Crss), thereby reducing both the conduction loss and switching loss of the system and improving the system efficiency.

[0003] The SGT power device structure usually isolates with polysilicon gate - dielectric layer - polysilicon gate in a longitudinal trench. Among them, the polysilicon gate morphology has a great influence on the device. For example, when defects such as "V" shape or "small void" are formed in or around the polysilicon gate, it will affect the gate leakage and short - circuit, and further affect the device gate leakage (IGSS failure).

[0004] Therefore, it is necessary to propose a new method for manufacturing a semiconductor device to solve the above problems. Summary of the Invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0006] The present invention provides a method for manufacturing a semiconductor device, including:

[0007] Providing a semiconductor substrate;

[0008] Etching the semiconductor substrate to form a groove;

[0009] Depositing a shielding dielectric layer on the bottom and side walls of the groove;

[0010] Forming a shielding gate layer in the groove;

[0011] Etching away a part of the shielding gate layer, the upper surface of the shielding gate layer being lower than the upper surface of the shielding dielectric layer;

[0012] Etching the shielding dielectric layer, the upper surface of the shielding dielectric layer being lower than the upper surface of the shielding gate layer;

[0013] Performing morphology treatment on the shielding gate layer by dry etching so that both ends of the shielding gate layer are not higher than the shielding dielectric layer;

[0014] Form a gate dielectric layer in the groove;

[0015] Fill the groove with a gate material to form a gate material layer, the upper surface of the gate material layer being higher than the upper surface of the semiconductor substrate;

[0016] Planarize the gate material layer so that the upper surface of the gate material layer is flush with the upper surface of the semiconductor substrate.

[0017] Furthermore, the topography treatment of the shielding gate layer by dry etching includes:

[0018] Introduce a first gas combination to smooth the step corner at the junction of the shielding gate layer and the shielding dielectric layer;

[0019] Introduce a second gas combination with a high selectivity ratio for the shielding gate layer and the shielding dielectric layer to reduce the step at the junction of the shielding gate layer and the shielding dielectric layer, making the two ends of the shielding gate layer flush with the two ends of the shielding dielectric layer;

[0020] Introduce a third gas combination to adjust the topography of the central region of the shielding gate layer.

[0021] Furthermore, after the topography treatment of the shielding gate layer by dry etching, the central region of the shielding gate layer bulges upward.

[0022] Furthermore, after the topography treatment of the shielding gate layer by dry etching, the central region of the shielding gate layer sinks downward.

[0023] Furthermore, the first gas combination includes an inert gas and / or oxygen; the second gas combination includes a chlorine-based gas and / or a bromine-based gas; the third gas combination includes a fluorine-based gas.

[0024] Furthermore, the central region of the shielding gate layer bulges upward in an arc shape, and the height exceeding the shielding dielectric layer is less than The radian angle range is 10° - 20°.

[0025] Furthermore, the central region of the shielding gate layer sinks downward in an arc shape, and the height lower than the shielding dielectric layer The radian angle range is 30° - 45°.

[0026] Furthermore, forming a gate dielectric layer in the groove includes: filling the groove with a gate dielectric layer by chemical vapor deposition.

[0027] Furthermore, forming a gate dielectric layer in the groove includes: forming a gate dielectric layer in the groove by heat treatment.

[0028] Furthermore, the shielding gate layer includes a polysilicon layer, the gate material layer includes a polysilicon layer, the shielding dielectric layer includes an oxide layer, and the gate dielectric layer includes an oxide layer.

[0029] According to the manufacturing method of the semiconductor device provided by the present invention, by performing chemical mechanical polishing after overfilling polysilicon, the formation of a "V"-shaped polysilicon gate is avoided, and the shielding gate layer is subjected to topography treatment by dry etching, so that the two ends of the shielding gate layer are not higher than the shielding dielectric layer, and there is no "step" between the two, avoiding the occurrence of "small cavity" defects in the subsequent process and improving the device performance. Description of the Drawings

[0030] The following drawings of the present invention are hereby incorporated as part of the present invention for understanding the present invention. The embodiments of the present invention shown in the drawings and their descriptions are used to explain the principles of the present invention.

[0031] In the drawings:

[0032] By describing the embodiments of the present invention in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present invention will become more obvious. The drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings, the same reference numerals generally represent the same components or steps.

[0033] In the drawings:

[0034] Figure 1 is a schematic diagram of the defects of a semiconductor device manufactured according to the prior art;

[0035] Figures 2A - 2H is a schematic cross-sectional view of the device respectively obtained by the steps sequentially implemented according to the method of the exemplary embodiment of the present invention;

[0036] Figures 3A - 3E is a schematic cross-sectional view of the device respectively obtained by the steps sequentially implemented for topography treatment of the shielding gate layer according to the method of the exemplary embodiment of the present invention;

[0037] Figure 4 is a schematic flow chart of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention. Detailed Embodiments

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

[0039] It should be understood that the present invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the figures denote like elements.

[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0041] Spatial relationship terms such as "below", "beneath", "lower", "under", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] To thoroughly understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may also have other embodiments.

[0044] Referring to Figure 1 , in an SGT device prepared by the prior art, in the groove of the silicon substrate 100 (or silicon epitaxial layer), after dry etching the polysilicon shielding gate 104 and wet etching the shielding oxide 103, the height of the polysilicon shielding gate 104 is higher than that of the shielding oxide 103, forming a step. When subsequently filling the gate oxide layer 105, "small void" defects are likely to form at the step. Continuing to fill the groove to form the polysilicon gate 106, the center of the polysilicon gate 106 presents a "V" shape, and it will become more serious as the critical dimension (CD) of the groove shrinks. In addition, the wet etching process will also cause the upper sidewall of the silicon substrate 100 (or silicon epitaxial layer) to be "concave inward". When subsequently filling the polysilicon gate 106, "small void" defects are likely to form at the "concave inward" part under the silicon nitride mask layer 101. Defects such as the above-mentioned "V" shape or "small voids" will affect the leakage and short-circuit of the gate, and further affect the gate leakage current (IGSS failure) of the device.

[0045] To address the above problems, the present invention provides a method for manufacturing a semiconductor device, as Figure 4 shown. The main steps of this manufacturing method include:

[0046] Step S401: Provide a semiconductor substrate;

[0047] Step S402: Etch the semiconductor substrate to form a groove;

[0048] Step S403: Deposit a shielding dielectric layer on the bottom and sidewalls of the groove;

[0049] Step S404: Form a shielding gate layer in the groove

[0050] Step S405: Etch away a part of the shielding gate layer, with the upper surface of the shielding gate layer being lower than the upper surface of the shielding dielectric layer;

[0051] Step S406: Etch the shielding dielectric layer, with the upper surface of the shielding dielectric layer being lower than the upper surface of the shielding gate layer;

[0052] Step S407: Perform topography treatment on the shielding gate layer by dry etching so that both ends of the shielding gate layer are not higher than the shielding dielectric layer;

[0053] Step S408: Form a gate dielectric layer in the groove;

[0054] Step S409: Fill the groove with gate material to form a gate material layer, with the upper surface of the gate material layer being higher than the upper surface of the semiconductor substrate;

[0055] Step S410: Planarize the gate material layer so that the upper surface of the gate material layer is flush with the upper surface of the semiconductor substrate.

[0056] According to an embodiment of the present invention, the manufacturing method of the semiconductor device of the present invention specifically includes the following steps:

[0057] First, execute step S401 to obtain the device structure as Figure 2A shown. Provide a semiconductor substrate 200.

[0058] Exemplarily, the semiconductor device includes an SGT device.

[0059] Exemplarily, the semiconductor substrate 200 can be at least one of the materials mentioned below: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by the present invention. The semiconductor substrate 200 can be formed by epitaxial growth or can be a wafer substrate.

[0060] Exemplarily, a mask layer 201 is formed on the semiconductor substrate 200.

[0061] Exemplarily, the mask layer 201 includes a hard mask layer, and the hard mask layer includes an oxide layer, a nitride layer, or a stacked structure of the two to protect the upper surface of the semiconductor substrate 200 during the manufacturing process of the SGT device. In the embodiment of the present invention, the mask layer 201 includes a silicon nitride layer and a silicon oxide layer formed in sequence from bottom to top.

[0062] Next, perform step S402 to obtain a device structure as shown in Figure 2A Etch the semiconductor substrate 200 to form a groove.

[0063] In this embodiment, first, a photoresist layer (not shown) is formed on the mask layer 201, and then an opening pattern is formed in the photoresist through exposure and development processes; then, the mask layer 201 is etched using the patterned photoresist layer as a mask to transfer the opening pattern into the mask layer 201.

[0064] Exemplarily, dry etching can be used to etch the mask layer 201. Dry etching processes include but are not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can also be used.

[0065] Next, the semiconductor substrate 200 is etched using the patterned mask layer 201 as a mask.

[0066] Exemplarily, deep reactive ion etching (DRIE) can be used as the method to etch the semiconductor substrate 200 to form a groove. Specifically, the gas silicon hexafluoride (SF6 / C4F8) is selected as the process gas, and a radio frequency power supply is applied to make the silicon hexafluoride reaction intake form high ionization. In the etching step, the pressure is controlled at 15 mT to 45 mT, the source power is controlled at 400 W to 600 W, the bias power is controlled at -180 V to -240 V, the etching gas SF6 is controlled at 50 sccm - 70 sccm, O2 is controlled at 60 sccm - 85 sccm, and He is controlled at 100 sccm - 400 sccm to ensure the need for anisotropic etching. The deep reactive ion etching system can select commonly used equipment in the art and is not limited to a certain model.

[0067] In an exemplary embodiment of the present invention, the size range of the formed groove is 0.4 μm - 0.45 μm.

[0068] Next, perform step S403 to obtain a device structure as shown in Figure 2B Deposit a shielding dielectric layer 202 on the bottom and sidewalls of the groove.

[0069] Exemplarily, the material of the shielding dielectric layer 202 includes but is not limited to silicon oxide.

[0070] Exemplarily, a shielding dielectric layer 202 is formed in the groove by heat treatment or chemical vapor deposition. The method for forming the shielding dielectric layer 202 can adopt any existing technology familiar to those skilled in the art, including physical vapor deposition (PVD) and chemical vapor deposition (CVD), preferably chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0071] In an exemplary embodiment of the present invention, the thickness range of the formed shielding dielectric layer 202 is

[0072] Next, step S404 is executed to obtain a device structure as Figure 2B shown. A shielding gate layer 203 is formed in the groove.

[0073] Exemplarily, forming the shielding gate layer 203 in the groove includes:[[]]

[0074] Filling the groove with a shielding gate material to form a shielding gate layer 203, and the upper surface of the shielding gate layer 203 is higher than the upper surface of the mask layer 201;

[0075] The shielding gate layer 203 is planarized so that the upper surface of the shielding gate layer 203 is flush with the upper surface of the mask layer 201.

[0076] Exemplarily, the shielding gate material includes polysilicon. The method for forming polysilicon can select the low-pressure chemical vapor deposition (LPCVD) process. The process conditions for forming the polysilicon include: the reaction gas is silane (SiH4), and the flow rate range of the silane can be 350 - 450 cubic centimeters per minute (sccm), such as 400 sccm; the temperature range in the reaction chamber can be 500 - 600 degrees Celsius; the pressure in the reaction chamber can be 300 - 400 millitorr (mTorr), such as 350 mTorr; the reaction gas may further include a buffer gas, and the buffer gas can be helium or nitrogen, and the flow rate range of the helium and nitrogen can be 5 - 20 liters per minute (slm), such as 8 slm, 10 slm, or 15 slm.

[0077] By making the upper surface of the shielding gate layer 203 higher than the upper surface of the mask layer 201, and then using chemical mechanical polishing (CMP) to make the upper surface of the shielding gate layer 203 flush with the upper surface of the mask layer 201, it is possible to avoid a "V" - shaped morphology at the center of the shielding gate layer 203, and further avoid a "V" - shaped morphology at the center of the subsequently formed gate material layer.

[0078] Next, perform step S405 to obtain a device structure as shown in Figure 2D Etch away a part of the shielding gate layer 203, and the upper surface of the shielding gate layer 203 is lower than the upper surface of the shielding dielectric layer 202.

[0079] In an exemplary embodiment of the present invention, etching is only performed on a part of the grooves, while the other grooves are masked with a photoresist 204.

[0080] Exemplarily, a part of the shielding gate layer 203 is removed by dry etching. Specifically, the upper half of the polysilicon is removed by dry etching. Dry etching includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, or laser cutting. Dry etching is preferably performed through one or more RIE steps. As an example, plasma etching is used, and the etching gas can be a nitrogen-based gas. Specifically, a lower radio frequency energy is used to generate a low-pressure and high-density plasma gas to achieve dry etching of polysilicon. The etching gas used is a nitrogen-based gas, and the flow rate of the etching gas is: 100 - 200 cubic centimeters per minute (sccm); the pressure in the reaction chamber can be 30 - 50 mTorr, the etching time is 10 - 15 seconds, the power is 30 - 80 W, and the bias power is 0 W.

[0081] Next, perform step S406 to obtain a device structure as shown in Figure 2E Etch the shielding dielectric layer 202, and the upper surface of the shielding dielectric layer 202 is lower than the upper surface of the shielding gate layer 203.

[0082] Exemplarily, a part of the shielding dielectric layer 202 is removed by wet etching. Specifically, the upper half of the silicon oxide is removed by wet etching. The etching solution for the wet etching is a hydrofluoric acid solution. Specifically, ammonium fluoride and hydrofluoric acid are mixed at a volume ratio of 6:1, and the etching rate is about 100 nm / min.

[0083] Generally, after wet etching, the upper surface of the shielding dielectric layer 202 is lower than the upper surface of the shielding gate layer 203, forming a step, as shown in Figure 2E and 3A shown.

[0084] Next, perform step S407 to obtain a device structure as shown in Figure 2F Perform topography processing on the shielding gate layer 203 using dry etching so that both ends of the shielding gate layer 203 are not higher than the shielding dielectric layer 202.

[0085] Referring to Figures 3A - 3E , performing topography processing on the shielding gate layer 203 using dry etching includes:

[0086] Introduce a first gas combination to smooth the step corner at the junction of the shielding gate layer 203 and the shielding dielectric layer 202;

[0087] Introduce a second gas combination that has a high selectivity ratio for the shielding gate layer 203 and the shielding dielectric layer 202 to reduce the step at the junction of the shielding gate layer 203 and the shielding dielectric layer 202, making the two ends of the shielding gate layer 203 flush with the two ends of the shielding dielectric layer 202;

[0088] Introduce a third gas combination to adjust the topography of the central region of the shielding gate layer 203.

[0089] Exemplarily, after the topography of the shielding gate layer is processed by dry etching, the central region of the shielding gate layer bulges upward, or the central region of the shielding gate layer sinks downward.

[0090] In an exemplary embodiment of the present invention, the first gas combination includes an inert gas and / or oxygen, and the inert gas includes but is not limited to helium, argon, etc. Preferably, the first gas combination includes argon, helium, and oxygen: the flow rate range of argon can be 100 - 250 cubic centimeters per minute (sccm), the flow rate range of helium can be 100 - 150 cubic centimeters per minute (sccm), and the flow rate range of oxygen can be 5 - 15 cubic centimeters per minute (sccm); the temperature range in the reaction chamber can be 30 - 50 degrees Celsius; the pressure in the reaction chamber can be 5 - 50 millitorr (mTorr); the source power can be 500 - 800 W; the bias power can be 100 - 200 W. Introducing the first gas combination uses the pure physical bombardment of particles to cut the step, so as to smooth the step corner at the junction of the shielding gate layer 203 and the shielding dielectric layer 202, as Figure 3B shown, and the greater the particle mass, the more obvious the cutting effect.

[0091] Furthermore, the second gas combination includes chlorine-based gas and / or bromine-based gas. The chlorine-based gas and / or bromine-based gas has a high selectivity ratio for silicon oxide and polysilicon. The chlorine-based gas includes but is not limited to Cl2 and BCl3, and the bromine-based gas includes but is not limited to Br2 and HBr. Preferably, the second gas combination includes Cl2, HBr, oxygen, and CF4. Among them, Cl2 is mainly used for etching Poly-Si, HBr mainly plays a passivation role to protect SiO2 at the sidewalls, O2 is used to improve the selectivity ratio of Si to SiO2, and CF4 mainly balances the step difference at the junction of SiO2 and polysilicon at the sidewalls. Generally speaking, HBr, Cl2, and O2 in the second gas combination play the main roles, and CF4 plays an auxiliary role. Specifically, the flow rate range of Cl2 can be 60 to 150 cubic centimeters per minute (sccm), the flow rate range of HBr can be 100 to 200 cubic centimeters per minute (sccm), the flow rate range of oxygen can be 4 to 10 cubic centimeters per minute (sccm); the flow rate range of CF4 can be 10 to 20 cubic centimeters per minute (sccm), the temperature range in the reaction chamber can be 40 to 65 degrees Celsius; the pressure in the reaction chamber can be 5 to 60 millitorr (mTorr); the source power can be 600 to 1000 W; the bias power can be 30 to 200 W. Since the second gas combination has a high selectivity ratio for polysilicon and silicon oxide, the height of the shielding gate layer 203 can be reduced, making the two ends of the shielding gate layer 203 flush with the two ends of the shielding dielectric layer 202, and the central region bulges upward in an arc shape, as Figure 3C shown.

[0092] Further, the third gas combination includes fluorine-based gases, which include but are not limited to SF6, CH3F, and CF4. The fluorine-based gases have a high etching rate for polysilicon. Preferably, the third gas combination includes SF6, CH3F, helium, and oxygen. Among them, SF6 has a high polysilicon etching rate, a high selectivity ratio for SiO2, and isotropic etching. Hydrogen-containing fluorocarbon gases mainly provide more polymers for passivation protection, and He and oxygen are used to assist in modifying the morphological differences. Generally speaking, SF6 / CH3F in the third gas plays a major role. Specifically, the flow rate range of SF6 can be 10 to 85 cubic centimeters per minute (sccm), the flow rate range of CH3F can be 40 to 100 cubic centimeters per minute (sccm), the flow rate range of helium can be 80 to 150 cubic centimeters per minute (sccm), and the flow rate range of oxygen can be 5 to 15 cubic centimeters per minute (sccm); the temperature range in the reaction chamber can be 45 to 60 degrees Celsius; the pressure in the reaction chamber can be 5 to 45 millitorr (mTorr); the source power can be 600 to 1000 W; the bias power can be 50 to 200 W. Since the third gas combination has a high selectivity ratio for polysilicon and silicon oxide, and at the same time forms a thick polymer environmental protection shielding dielectric layer 202, the height of the circular arc "small dome" protruding upward in the central region of the shielding gate layer 203 can be further reduced, so that the height of the shielding gate layer 203 exceeding the shielding dielectric layer 202 is less than The radian angle range of the "small dome" is 10° - 20°, as Figure 3D shown.

[0093] Further, continue to introduce the third gas combination to further reduce the height of the central region of the shielding gate layer 203, making it concave downward in a circular arc shape, so that the height range of the shielding gate layer 203 below the shielding dielectric layer 202 is The radian angle range of the "concave trapezoid" is 30° - 45°, as Figure 3E shown.

[0094] Next, perform step S408: Form a gate dielectric layer 205 in the groove.

[0095] When the central region of the shielding gate layer 203 protrudes upward, a gate dielectric layer is filled in the groove by chemical vapor deposition.

[0096] Exemplarily, the material of the gate dielectric layer 205 includes, but is not limited to, silicon oxide. The method for forming the gate dielectric layer 205 can adopt any existing technology familiar to those skilled in the art. Preferably, chemical vapor deposition (CVD) methods such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD) can be used.

[0097] In an exemplary embodiment of the present invention, the height of the formed gate dielectric layer 205 is higher than the upper surface of the mask layer 201. Then, chemical mechanical polishing (CMP) is used to remove the part of the gate dielectric layer 205 that is higher than the upper surface of the semiconductor substrate 200 and the mask layer 201, so that the upper surface of the gate dielectric layer 205 is flush with the upper surface of the semiconductor substrate 200. Then, a part of the gate dielectric layer 205 in the groove is etched back, as Figure 2G shown.

[0098] When the central region of the shield gate layer 203 is recessed downward, a gate dielectric layer 205 is formed in the groove by heat treatment.

[0099] Exemplarily, a gate dielectric layer 205 is formed on the shield gate layer 203 and the inner wall of the groove by performing thermal oxidation. The gate dielectric layer 205 is a silicon oxide layer. In this embodiment, a layer of silicon oxide is grown on the shield gate layer 203 and the inner wall of the groove by using a furnace tube process as the gate dielectric layer 205. Specifically, by introducing water vapor into the furnace tube for wet oxidation, compared with dry oxidation without introducing water vapor into the furnace tube, the oxidation rate of the wet oxidation method is faster, which is beneficial to forming a thicker silicon oxide layer.

[0100] Next, step S409 is performed: filling the groove with a gate material to form a gate material layer 206, and the upper surface of the gate material layer 206 is higher than the upper surface of the semiconductor substrate 200.

[0101] Exemplarily, the gate material includes polysilicon. The method for filling polysilicon in the groove can adopt any existing technology familiar to those skilled in the art, and will not be elaborated here.

[0102] Next, step S410 is performed: planarizing the gate material layer 206 so that the upper surface of the gate material layer 206 is flush with the upper surface of the semiconductor substrate 200.

[0103] In an exemplary embodiment of the present invention, the upper surface of the formed gate material layer 206 is higher than the upper surface of the semiconductor substrate 200, and then chemical mechanical polishing (CMP) is used to make the upper surface of the gate material layer 206 flush with the upper surface of the semiconductor substrate 200, which can avoid the "V" - shaped morphology at the center of the gate material layer 206.

[0104] According to the manufacturing method of the semiconductor device provided by the present invention, by over - filling polysilicon and then performing chemical mechanical polishing, the formation of a "V" - shaped polysilicon gate is avoided, and dry etching is used to process the morphology of the shielding gate layer so that the two ends of the shielding gate layer are not higher than the shielding dielectric layer, and there is no "step" between them, avoiding the occurrence of "small void" defects in the subsequent process and improving the device performance.

[0105] The present invention has been described through the above - mentioned embodiments. However, it should be understood that the above - mentioned embodiments are only for the purpose of exemplification and illustration, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above - mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a semiconductor substrate; Etching the semiconductor substrate to form a groove; Depositing a shielding dielectric layer on the bottom and sidewalls of the groove; Forming a shielding gate layer in the groove; Etching to remove a part of the shielding gate layer, and the upper surface of the shielding gate layer is lower than the upper surface of the shielding dielectric layer; Etching the shielding dielectric layer, and the upper surface of the shielding dielectric layer is lower than the upper surface of the shielding gate layer; Performing topography treatment on the shielding gate layer by dry etching so that both ends of the shielding gate layer are not higher than the shielding dielectric layer; Forming a gate dielectric layer in the groove; Filling the groove with a gate material to form a gate material layer, and the upper surface of the gate material layer is higher than the upper surface of the semiconductor substrate; Planarizing the gate material layer so that the upper surface of the gate material layer is flush with the upper surface of the semiconductor substrate; Wherein, performing topography treatment on the shielding gate layer by dry etching includes: Introducing a first gas combination to smooth the step corner at the junction of the shielding gate layer and the shielding dielectric layer; Introducing a second gas combination having a high selectivity ratio for the shielding gate layer and the shielding dielectric layer to reduce the step at the junction of the shielding gate layer and the shielding dielectric layer so that both ends of the shielding gate layer are flush with both ends of the shielding dielectric layer.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Performing topography treatment on the shielding gate layer by dry etching further includes: Introducing a third gas combination to adjust the topography of the central region of the shielding gate layer.

3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, After performing topography treatment on the shielding gate layer by dry etching, the central region of the shielding gate layer bulges upward.

4. The manufacturing method of the semiconductor device according to claim 2, characterized in that, After performing topography treatment on the shielding gate layer by dry etching, the central region of the shielding gate layer sinks downward.

5. The manufacturing method of the semiconductor device according to claim 2, characterized in that, The first gas combination includes an inert gas and / or oxygen; the second gas combination includes a chlorine-based gas and / or a bromine-based gas; the third gas combination includes a fluorine-based gas.

6. The manufacturing method of the semiconductor device according to claim 3, characterized in that, The central region of the shielding gate layer bulges upward in an arc shape, and the height by which it exceeds the shielding dielectric layer is less than The range of its radian angle is 10°-20°.

7. The manufacturing method of the semiconductor device according to claim 4, characterized in that, The central region of the shielding gate layer is recessed downward in an arc shape, and its height is lower than that of the shielding dielectric layer. The range of its radian angle is 30°-45°.

8. The manufacturing method of the semiconductor device according to claim 3, characterized in that, Forming a gate dielectric layer in the groove includes: Filling the groove with a gate dielectric layer by chemical vapor deposition.

9. The manufacturing method of the semiconductor device according to claim 4, characterized in that, Forming a gate dielectric layer in the groove includes: Forming a gate dielectric layer in the groove by heat treatment.

10. The method for manufacturing a semiconductor device according to claim 8 or 9, characterized in that, The shielding gate layer includes a polysilicon layer, the gate material layer includes a polysilicon layer, the shielding dielectric layer includes an oxide layer, and the gate dielectric layer includes an oxide layer.

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