Semi-wafer-level packaging method

Abstract

A semi-wafer-level packaging method, comprising the following steps: preparing a wafer; grinding the back surface of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a cutting process; bonding a second tape; removing the first tape; bonding a support structure; bonding a third tape; removing the second tape; and applying a separation process. A semi-wafer-level packaging method, comprising the following steps: preparing a wafer; connecting a carrier wafer to the wafer; grinding the back surface of the wafer; forming a metallization layer; applying a cutting process; bonding a support structure; removing the carrier wafer; bonding a tape; and applying a separation process.

Description

Technical Field

[0001] The present invention generally relates to a semi-wafer-level packaging method. More specifically, the present invention relates to a semiconductor packaging manufacturing method, which includes a dicing process for separating a device layer and a separation process for separating a metal support structure before connecting the metal support structure. Background Art

[0002] Traditional packaging methods employ a single dicing process before packaging. The wafer-level chip-scale packaging (WLCSP) process of Yilmaz et al., U.S. Patent No. 9,087,828, applies a packaging process before a single dicing process. When manufacturing a double-diffused metal oxide semiconductor field effect transistor (DMOSFET) package using the WLCSP process, a thinner device wafer needs to be attached to a thicker back metal to reduce resistance. Due to the mismatch in the coefficient of thermal expansion between the thinner device wafer and the thicker back metal, the thinner device wafer may warp. Warping of the thinner device wafer may cause cracking and lead to device failure.

[0003] It is advantageous to introduce the semi-wafer-level packaging method of the present invention to reduce wafer warping, lower resistance, and improve device reliability performance. The semi-wafer-level packaging method includes a dicing process before connecting the metal support structure and a separation process for separating the device layer and the metal support structure. Summary of the Invention

[0004] A semi-wafer-level packaging method includes the following steps: providing a wafer; grinding the back of the wafer; forming a metallization layer; removing the peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a support structure; bonding a third tape; removing the second tape; and applying a separation process.

[0005] A semi-wafer-level packaging method includes the following steps: providing a wafer; connecting a carrier wafer to the wafer; grinding the back of the wafer; forming a metallization layer; applying a dicing process; bonding a support structure; removing the carrier wafer; bonding a tape; and applying a separation process. Brief Description of the Drawings

[0006] Figure 1 Represents a process flow diagram for preparing multiple semiconductor packages in an example of the present invention.

[0007] Figures 2A - 2K Represents an example of the present invention Figure 1 Cross-sectional views of corresponding steps in the illustrated process.

[0008] Figure 3 Represents a process flow diagram for preparing a support structure in an example of the present invention.

[0009] Figures 4A - 4C In an example of the present invention, Figure 3 a cross-sectional view of a corresponding step in the process shown.

[0010] Figure 5 In an example of the present invention, another flowchart of a process for fabricating a plurality of semiconductor packages is shown.

[0011] Figures 6A - 6I In an example of the present invention, Figure 5 a cross-sectional view of a corresponding step in the process shown.

[0012] Figure 7 In an example of the present invention, a cross-sectional view of a semiconductor package is shown. Detailed Description of the Invention

[0013] Figure 1 In an example of the present invention, a flowchart of Process 100 for fabricating a plurality of semiconductor packages is shown. FIGS. 2A-2K show cross-sectional views of corresponding steps. Process 100 may start at block 102.

[0014] In block 102, now referring to Figure 2A , which has a wafer 202. In one example, the upper surface of the wafer 202 is completed with a plurality of semiconductor devices formed thereon. The wafer 202 includes a front side 204 and a back side 206 opposite the front side 204. Each semiconductor device includes a plurality of metal electrodes [not shown in the figure, the metal electrodes are conventional features described in 37 CFR 1.83(a)]. In one example, the wafer 202 is a silicon wafer. The wafer 202 may be a wafer having a diameter of 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. After block 102 may be block 104.

[0015] In block 104, now referring to Figure 2B , a grinding process is applied to the back side 206 of the wafer 202 to thin the wafer 202 from its back side. In one example, the grinding process is applied only to the central portion of the back side 206 of the wafer 202 to form a groove 212 and a peripheral ring 214. The groove 212 is cylindrical. The peripheral ring 214 is circular. The peripheral ring 214 may be a Taiko ring. After block 104 may be block 106.

[0016] In block 106, now referring to Figure 2C , a metallization layer 218 is formed in the groove 212. The metallization layer 218 is deposited on the back side of the wafer. In one example, the metallization layer 218 is made of copper. After block 106 may be block 108.

[0017] In block 108, now referring to Figure 2D, the peripheral ring 214 (in one example, the Taiko ring) is removed to form a flat, circular back surface 222. The metallization layer 218 covers the entire back surface of the thinned device layer 224. Block 108 may be followed by block 110.

[0018] In block 110, now referring to Figure 2E , the back side of the wafer is bonded to the first tape 232 by bonding the metallization layer 218 to the first tape 232. The diameter of the first tape 232 is larger than the diameter of the thinned device layer 224. Block 110 may be followed by block 112.

[0019] In block 112, now referring to Figure 2F , a dicing process is applied. A plurality of diced device portions 234 and a plurality of diced metallization portions 238 are formed. In one example, the cutting process from the front side stops at the top surface of the first tape 232. In another example, the incision of the cutting process cuts the first tape 232 to a depth of 5% to 15% of the thickness of the first tape 232. The first tape 232 holds the separated devices in place to maintain the wafer shape. Block 112 may be followed by block 114.

[0020] In block 114, now referring to Figure 2G , a plurality of diced device portions 234 are connected to the second tape 242. The top surface of the diced wafer is connected to the second tape 242. The diameter of the second tape 242 is larger than the diameter of the thinned device layer 224. Block 114 may be followed by block 116.

[0021] In block 116, now referring to Figure 2H , the first tape 232 is removed. The second tape 242 holds the separated devices in place to maintain the wafer shape. Block 116 may be followed by block 118.

[0022] In block 118, now referring to Figure 2I, the support structure 252 is connected to a plurality of cut metallization portions 238. In an example of the present invention, the support structure 252 is also referred to as a thick metal structure including a thick metal layer of a predetermined thickness. In one example, the support structure 252 includes a thin film laminate 254 and a metal layer 256. In another example, the support structure 252 includes a thin film laminate 254, a metal layer 256, and a marker film coating 258. The metal layer 256 includes a first surface 257 and a second surface 255 opposite the first surface 257. The thin film laminate 254 includes a first surface 253 and a second surface 251 opposite the first surface 253. The first surface 253 of the thin film laminate 254 is connected to the second surface 255 of the metal layer 256. The second surface 251 of the thin film laminate 254 is connected to a plurality of cut metallization portions 238. In one example, the thin film laminate 254 is a sintered silver film. In another example, the thin film laminate is a conductive die attach film (CDAF).

[0023] Figure 3 Indicates that in an example of the present invention, the preparation Figure 2I A flowchart of process 300 for the support structure 252 shown. Process 300 can start from block 302.

[0024] In block 302, now referring to Figure 4A , a metal layer 456 is provided. In an example of the present invention, the metal layer 456 is also referred to as a thick metal layer. In one example, the metal layer 456 is made of copper. The thickness of the metal layer 456 is in the range of 10 micrometers to 100 micrometers. After block 302, it can be block 304 or block 306.

[0025] In optional block 304 (shown as a dashed line because it is optional), now referring to Figure 4B , a marker film coating 458 is attached to the first side of the metal layer 456. After block 304, it can be block 306.

[0026] In block 306, now referring to Figure 4C , a thin film laminate 454 is attached to the second side of the metal layer opposite the first side of the metal layer 456 to form Figure 2I the support structure 252 shown.

[0027] After block 118, it can be block 120.

[0028] In block 120, now referring to Figure 2J, the third tape 272 is connected to the support structure 252. In one example, the third tape 272 is directly connected to the marker film coating 258 of the support structure 252. In another example, the third tape 272 is directly connected to the metal layer 256 (without the marker film coating 258) of the support structure 252. Block 120 may be followed by block 122.

[0029] In block 122, still referring now to Figure 2J , the second tape 242 (shown in dashed lines) is removed. The support structure 252 holds the separated devices in place to maintain the wafer shape. Block 122 may be followed by block 124.

[0030] In block 124, now referring to Figure 2K , a separation process is applied. The separation process that is spatially aligned with the diced device portion 234 and the diced metallization portion 238 passes through the support structure 252, forming a plurality of cut support structure portions 292. In one example, the separation process starts with a front cut and stops at the top surface of the third tape 272. In another example, the separation process cuts to a depth of 5% to 15% of the thickness of the third tape 272 into the third tape 272. A plurality of semiconductor packages 299 are formed. Each of the plurality of semiconductor packages 299 can be separated from the third tape 272 at a later time.

[0031] Now referring to Figure 7 , in the example of the present invention, the radius of the first saw for performing the cutting process is greater than the radius of the second saw for performing the separation process, such that the first width 712 of each of the cut support structure portions 792 is greater than the second width 714 of each of the plurality of diced device portions 731. Thus, due to the narrower second width 714, each of the plurality of diced device portions 731 is protected by reducing the chance of being touched. The semiconductor package 700 includes a marker film coating 741 that covers the surface of the thick metal layer 742 device semiconductor layer 745 that is connected to the backside metallization layer 744 through the thin film laminate layer 743. As Figure 7 shown, the sides of the device backside metallization layer 744 are substantially coplanar with the corresponding sides of the device semiconductor layer 745 on all sides. The side surfaces of the thick metal layer 742 are substantially coplanar with the corresponding side surfaces of the film stack 743 and the corresponding side surfaces of the marker film coating 741 on all sides. Each edge of the device backside metallization layer 744 is recessed from the corresponding edge of the thick metal layer 742 on all sides. The device semiconductor layer 745 may include one or more field effect transistors (FETs).

[0032] Figure 5 represents a flowchart of a process 500 for fabricating a plurality of semiconductor packages in the example of the present invention. Figures 6A - 6IRepresents a cross-section of the corresponding step. The process 500 can start from block 502.

[0033] In block 502, now referring to Figure 6A , there is a wafer 602. In one example, the upper surface of the wafer 602 is completed by a plurality of semiconductor devices formed thereon. The wafer 602 includes a front side 604 and a back side 606 opposite to the front side 604. Each semiconductor device includes a plurality of metal electrodes [not shown in the figure, the metal electrodes are conventional features described in 37 CFR 1.83(a)], placed on the front side 204. In one example, the wafer 602 is a silicon wafer. The wafer 602 can be a wafer with a diameter of 4 inches, 6 inches, 8 inches, 12 inches or 18 inches. After block 502 can be block 504.

[0034] In block 504, now referring to Figure 6B , a carrier wafer 612 is connected to the front side 604 of the wafer 602 through an adhesive 614. In one example, the adhesive 614 is a non-conductive adhesive. In another example, the adhesive 614 is a conductive adhesive. After block 504 can be block 506.

[0035] In block 506, now referring to Figure 6C , a grinding process is applied to the back side 606 of the wafer 602 to form a thinned device layer 616. After block 506 can be block 508.

[0036] In block 508, now referring to Figure 6D , a metallization layer 618 is formed. The metallization layer 618 is deposited on the back side of the wafer. In one example, the metallization layer 618 is directly connected to the thinned device layer 616. The metallization layer 618 is made of copper. After block 508 can be block 510.

[0037] In block 510, now referring to Figure 6E , a dicing process is applied. A plurality of diced device portions 634 and a plurality of diced metallization portions 638 are formed. In one example, the cut of the dicing process stops at the upper surface of the adhesive 614. In another example, the cut of the dicing process cuts through the adhesive 614 to a depth of 5% to 15% of the thickness of the adhesive 614. The adhesive 614 fixes the separated device positions on the carrier wafer 612 to maintain the wafer shape. After block 510 can be block 512.

[0038] In block 512, now referring to Figure 6F, the support structure 652 is connected to a plurality of cut metallization portions 638. In an example of the present invention, the support structure 652 is also referred to as a thick metal structure including a thick metal layer of a predetermined thickness. In one example, the support structure 652 includes a thin film laminate 654 and a metal layer 656. In another example, the support structure 652 includes a thin film laminate 654, a metal layer 656, and a marker film coating 658. The metal layer 656 includes a first surface 657 and a second surface 655 opposite the first surface 657. The thin film laminate 654 includes a first surface 653 and a second surface 651 opposite the first surface 653. The first surface 653 of the thin film laminate 654 is attached to the second surface 655 of the metal layer 656. The second surface 651 of the thin film laminate 654 is connected to a plurality of cut metallization portions 638. Block 512 may be followed by block 514.

[0039] In block 514, now referring to Figure 6G , the carrier wafer 612 and the adhesive 614 are removed. The support structure 652 holds the separated devices in place to maintain the wafer shape. Block 514 may be followed by block 516.

[0040] In block 516, now referring to Figure 6H , a tape 672 is connected to the support structure 652. In one example, the tape 672 is directly connected to the marker film coating 658 of the support structure 652. In another example, the tape 672 is directly connected to the metal layer 656 of the support structure 652 (without the marker film coating 658). Block 516 may be followed by block 518.

[0041] In block 518, now referring to Figure 6I , a separation process is applied. The separation process that is spatially aligned with the cut device portions 634 and the cut metallization portions 638 passes through the support structure 652, forming a plurality of cut support structure portions 692. In one example, the separation process stops at the top surface of the tape 672. In another example, the separation process cuts the tape 672 to a depth of 5% to 15% of the thickness of the tape 672. A plurality of semiconductor packages 699 are formed. Each of the plurality of semiconductor packages 699 can then be separated from the third tape 672.

[0042] In the example described in the present invention, the radius of the first saw for performing the cutting process is greater than the radius of the second saw for performing the separation process, such that the Figure 7 first width 712 of each is greater than the second width 714 of each of the plurality of cut device portions 731. The area of the thick metal layer 742 is greater than the area of the backside metallization layer 744 and extends beyond all the edges of the device semiconductor layer 745.

[0043] Those of ordinary skill in the art will recognize that there is a possibility of modifying the embodiments disclosed in the present invention. For example, the number of multiple semiconductor packages made from one wafer can vary. Those of ordinary skill in the art can make other modifications, and all such modifications are considered to fall within the scope of the present invention as defined by the claims.

Claims

1. A method for manufacturing a plurality of wafer - level chip - scale semiconductor packages, the method comprising the following steps: Provide a wafer, the wafer including a front side and a back side opposite to the front side; Grind the back side of the wafer to form a peripheral ring; Deposit a metallization layer onto the ground surface; Remove the peripheral ring; Bond the metallization layer to a first tape; Apply a cutting process to the wafer to form a plurality of cut device portions and a plurality of cut metallization portions; Bond the plurality of cut device portions to a second tape; Remove the first tape; Bond a support structure to the plurality of cut metallization portions; Bond a third tape to the support structure; Remove the second tape; and apply a cutting process to the support structure; Wherein the step of bonding the support structure includes the following sub-steps: Provide a metal layer, the metal layer including a first surface and a second surface opposite to the first surface; Provide a thin film laminate, the thin film laminate including a first surface and a second surface opposite to the first surface; Attach the first surface of the thin film laminate to the second surface of the metal layer to form a support structure; And Connect the support structure to the plurality of cut metallization portions by connecting the second surface of the thin film laminate to the plurality of cut metallization portions.

2. The method according to claim 1, wherein the step of bonding the support structure further comprises: Before the sub-step of attaching the first surface of the thin film laminate to the second surface of the metal layer, attach a marker film coating to the first surface of the metal layer.

3. The method according to claim 2, wherein the wafer is a silicon wafer, and wherein the metal layer contains copper.

4. The method according to claim 3, wherein the cutting process cuts the silicon wafer; wherein the cutting process cuts the metallization layer; and wherein the cutting process cuts the first tape to a depth of 5% to 15% of the thickness of the first tape.

5. The method according to claim 4, wherein the separating process passes through the support structure to form a plurality of cut - support - structure portions; And Wherein the depth of cutting the third tape in the separation process is 5% to 15% of the thickness of the third tape.

6. The method according to claim 5, wherein the first width of each cut - support - structure portion is greater than the second width of each cut - device portion among the plurality of cut - device portions.

7. The method according to claim 2, wherein the thickness of the metal layer ranges from ten micrometers to one hundred micrometers.

8. A method for manufacturing a plurality of wafer - level chip - scale semiconductor packages, the method comprising the following steps: Prepare a wafer, the wafer including a front side and a back side opposite to the front side; Connect a carrier wafer to the front side of the wafer; Grind the back side of the wafer to form a thinned wafer; Form a metallization layer on the ground surface; Apply a cutting process to the wafer to form a plurality of cut metallization portions and a plurality of cut device portions; Bond a support structure to the plurality of cut metallization portions; Remove the carrier wafer; Bond a tape to the support structure; And Apply a separation process to the support structure; Wherein the step of bonding the support structure includes the following sub-steps: Prepare a metal layer, the metal layer including a first surface and a second surface opposite to the first surface; Prepare a thin film laminate, the thin film laminate including a first surface and a second surface opposite to the first surface; Connect the first surface of the thin film laminate to the second surface of the metal layer to form a support structure, and connect the support structure to the plurality of cut metallization portions by connecting the second surface of the thin film laminate to the plurality of cut metallization portions.

9. The method according to claim 8, wherein the support structure further comprises Before the sub-step of connecting the first surface of the thin film laminate to the second surface of the metal layer, a marker film coating is attached to the first surface of the metal layer.

10. The method according to claim 9, wherein the wafer is a silicon wafer; and wherein the metal layer contains copper.

11. The method according to claim 10, wherein the cutting process cuts the silicon wafer; and wherein the cutting process passes through the metallization layer.

12. The method according to claim 11, wherein the separation process passes through the support structure to form a plurality of cut support structure portions; and wherein the depth of the separation process cutting the tape is 5% to 15% of the tape thickness.

13. The method according to claim 12, wherein the first width of each cut support structure portion is greater than the second width of the plurality of cut device portions.

14. The method according to claim 9, wherein the thickness range of the metal layer is from ten micrometers to one hundred micrometers.

15. A wafer-level chip-scale semiconductor package, prepared by the method according to any one of claims 1-14, comprising: A device semiconductor layer including a plurality of metal electrodes provided on a front surface of the device semiconductor layer; A backside metallization layer connected to a back side of the device semiconductor layer; And A metal layer attached to the backside metallization layer through a thin film laminate layer; Wherein each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer; Wherein each side surface of the metal layer is coplanar with a corresponding side surface of the thin film laminate layer; And Wherein the surface area of the back surface of the backside metallization layer is smaller than the surface area of the front surface of the metal layer.

16. The wafer-level chip-scale semiconductor package according to claim 15, further comprising: A marker film coating covering the metal layer.

17. The wafer-level chip-scale semiconductor package according to claim 16, wherein each side surface of the metal layer is coplanar with the corresponding side surface of the marking film coating.

18. The wafer-level chip-scale semiconductor package according to claim 17, wherein the surface area of the front surface of the metal layer extends beyond all edges of the device semiconductor layer.

Images