A FinFET basic structure and a manufacturing method thereof

Abstract

The present invention provides a FinFET basic structure and a manufacturing method thereof; the FinFET basic structure includes a substrate; further included is a filling member (520) inserted on the substrate; a protruding portion (521) is formed to protrude on the side wall at the bottom of the filling member (520); the protruding portion (521) protrudes above the top surface of the substrate; the FinFET basic structure further includes a metal gate covering the substrate and the portion of the side wall of the filling member (520) located above the substrate. The FinFET basic structure and the manufacturing method thereof of the present invention are novel in design and strong in practicability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a FinFET basic structure and a manufacturing method thereof. Background Art

[0002] As Figures 1 - 20 shown, Figure 1 FIG. shows a schematic flow state diagram of an interlayer dielectric planarization step in a manufacturing method of an existing FinFET basic structure; Figure 2 FIG. shows Figure 1 a cross-sectional view taken along line A-A of the state of the interlayer dielectric planarization step shown in FIG. Figure 3 FIG. shows Figure 1 a schematic flow state diagram of a grooving step in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 4 FIG. shows Figure 3 a cross-sectional view taken along line B-B of the state of the grooving step shown in FIG. Figure 5 FIG. shows Figure 1 a schematic flow state diagram of a step of filling SiN by ALD technology in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 6 FIG. shows Figure 5 a cross-sectional view taken along line C-C of the state of the step of filling SiN by ALD technology shown in FIG. Figure 7 FIG. shows Figure 1 a schematic flow state diagram of a step of removing a polysilicon layer in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 8 FIG. shows Figure 7 a cross-sectional view taken along line D-D of the state of the step of removing the polysilicon layer shown in FIG. Figure 9 FIG. shows Figure 1 a schematic flow state diagram of a step of removing a dummy layer in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 10 FIG. shows Figure 9 a cross-sectional view taken along line E-E of the state of the step of removing the dummy layer shown in FIG. Figure 11 FIG. shows Figure 1 a schematic flow state diagram of an oxide film growth step in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 12 FIG. shows Figure 11 a cross-sectional view taken along line F-F of the state of the oxide film growth step shown in FIG. Figure 13 FIG. shows Figure 1 a schematic flow state diagram of a step of depositing a high-k dielectric material / TiN in a manufacturing method of an existing FinFET basic structure shown in FIG. Figure 14 FIG. shows Figure 13 a cross-sectional view taken along line G-G of the state of the step of depositing the high-k dielectric material / TiN shown in FIG. Figure 15 FIG. showsFigure 1 Flow state schematic diagram of the capping layer formation step in the manufacturing method of the shown existing FinFET basic structure; Figure 16 Shows Figure 15 Cross-sectional schematic diagram in the H-H direction showing the state of the capping layer formation step; Figure 17 Shows Figure 1 Flow state schematic diagram of the capping layer removal step in the manufacturing method of the shown existing FinFET basic structure; Figure 18 Shows Figure 17 Cross-sectional schematic diagram in the I-I direction showing the state of the capping layer removal step; Figure 19 Shows Figure 1 Flow state schematic diagram of the metal gate formation step in the manufacturing method of the shown existing FinFET basic structure; Figure 20 Shows Figure 19 Cross-sectional schematic diagram in the J-J direction showing the state of the metal gate formation step; The manufacturing method of this FinFET basic structure includes the following steps: Step 1, prepare a substrate, which includes a STI layer 1, a plurality of fins 2 inserted in the STI layer 1, a dummy layer 3 attached to the fins 2, and a polysilicon layer 4 covering the STI layer 1 and the dummy layer 3; then, planarize the polysilicon layer 4; Step 2, open a groove 5 on the substrate, and the groove 5 penetrates the polysilicon layer 4 and stops inside the STI layer 1; Step 3, fill SiN in the groove 5 through ALD technology to form a filling member 6; Step 4, remove the polysilicon layer 4; Step 5, remove the dummy layer 3; Step 6, form an oxide film 7 on the outer wall of the fins 2; Step 7, successively form a high-k dielectric material layer 8 and a first TiN layer 9 through a deposition technique; Step 8, form a capping layer 10 on the first TiN layer 9, and perform post capping anneal (PCA); Step 9, remove the capping layer 10; Step 10, successively form a TaN layer 12 and a second TiN layer 13 through a deposition method, and then arrange a metal layer 14 on the second TiN layer 13 to form a metal gate. In this manufacturing method of the FinFET basic structure, when removing the capping layer, due to the trench with a high aspect ratio between the fins 2 and the filling member 6, there will be Si residue 11, which will cause poor electrical performance of the FinFET basic structure. Summary of the Invention

[0003] The object of the present invention is to address the above technical problems and propose a FinFET basic structure and its manufacturing method.

[0004] The technical solution for the present invention to solve its technical problems is: …

[0005] The present invention proposes a manufacturing method of a FinFET basic structure, including the following steps:

[0006] Step S: Provide a substrate, and then form a groove on the substrate by etching technology;

[0007] Step S: Oxidize a part of the inner wall of the groove near its opening to form a first oxide layer, and make the bottom of the groove protrude to form a convex groove;

[0008] Step S: Fill the groove and the convex groove with a filling material to form a filling member; wherein, the filling material filled in the convex groove forms a protruding portion of the filling member;

[0009] Step S: Remove a part of the substrate, so that the protruding portion of the filling member is exposed;

[0010] Step S: Form a capping layer to cover the protruding portion of the filling member; then anneal to remove the capping layer; and then arrange a metal layer at the position of the removed capping layer to form a metal gate.

[0011] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, in step S, the substrate includes a STI layer, a plurality of fins inserted on the STI layer, a dummy layer, and a polysilicon layer covering the STI layer and the dummy layer, and the dummy layer covers the outer walls of the fins located above the top surface of the STI layer; the groove penetrates through the polysilicon layer and extends into the STI layer.

[0012] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, step S further includes: removing the polysilicon layer; and then removing the dummy layer and the first oxide layer, so that the protruding portion of the filling member is exposed.

[0013] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, step S further includes: forming a second oxide layer on the outer walls of the fins located above the top surface of the STI layer; and then successively forming a high-k dielectric material layer and a first TiN layer by deposition technology; wherein, the high-k dielectric material layer covers the outer wall of the second oxide layer, the top surface of the STI layer, and the outer walls of the filling member located above the top surface of the STI layer; the first TiN layer covers the high-k dielectric material layer; and then, form a capping layer on the first TiN layer.

[0014] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, both the STI layer and the dummy layer are made of SiO; the thickness of the first oxide layer is less than the thickness of the dummy layer;

[0015] The filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or a metal oxide, wherein the metal oxide is AlO, TiO, an oxide of hafnium or an oxide of zirconium;

[0016] The high dielectric constant material layer is made of HfO, TiO, HfZrO, HfSiNO, TaO, ZrO, ZrSiO or AlO;

[0017] The metal layer is made of W.

[0018] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, in step S, exposing the protruding part of the filling piece includes: the step of making at least one contour turning point or contour turning line of the protruding part be located above the top surface of the STI layer.

[0019] In the manufacturing method of the above-mentioned FinFET basic structure of the present invention, in step S, after removing the capping layer, it further includes the steps of successively forming a TaN layer and a second TiN layer by a deposition method, and then arranging a metal layer on the second TiN layer to form a metal gate.

[0020] The present invention also proposes a FinFET basic structure, including a substrate, the substrate includes an STI layer; the FinFET basic structure further includes a filling piece inserted on the STI layer; a protruding part is formed protruding on the side wall at the bottom of the filling piece; the protruding part protrudes above the top surface of the STI layer;

[0021] The FinFET basic structure further includes a metal gate covering the STI layer and the part of the side wall of the filling piece located above the STI layer.

[0022] In the above-mentioned FinFET basic structure of the present invention, at least one contour turning point or contour turning line of the protruding part is located above the top surface of the STI layer.

[0023] In the above-mentioned FinFET basic structure of the present invention, the protruding part surrounds the filling piece and forms a bottom frustum contour structure with a gradually decreasing diameter from bottom to top.

[0024] The FinFET basic structure and its manufacturing method of the present invention avoid the problem of residual Si during the removal of the capping layer by adopting the protruding part. In particular, by forming the first oxide layer on the outer wall of the filling piece, the filling space of the filling piece is greatly reduced, so that the filling and removal space of the silicon material during the subsequent capping annealing process is increased, avoiding the problem of silicon residue. The FinFET basic structure and its manufacturing method of the present invention have novel designs and strong practicability. Description of the Drawings

[0025] The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0026] Figure 1 It shows a schematic flow state diagram of the interlayer dielectric planarization step of a manufacturing method of an existing FinFET basic structure;

[0027] Figure 2Shows Figure 1 A cross-sectional schematic view in the A-A direction showing the state of the interlayer dielectric planarization step shown;

[0028] Figure 3 Shows Figure 1 A process state schematic view of the grooving step in the manufacturing method of the existing FinFET infrastructure shown;

[0029] Figure 4 Shows Figure 3 A cross-sectional schematic view in the B-B direction showing the state of the grooving step shown;

[0030] Figure 5 Shows Figure 1 A process state schematic view of the step of filling SiN by ALD technology in the manufacturing method of the existing FinFET infrastructure shown;

[0031] Figure 6 Shows Figure 5 A cross-sectional schematic view in the C-C direction showing the state of the step of filling SiN by ALD technology shown;

[0032] Figure 7 Shows Figure 1 A process state schematic view of the step of removing the polysilicon layer in the manufacturing method of the existing FinFET infrastructure shown;

[0033] Figure 8 Shows Figure 7 A cross-sectional schematic view in the D-D direction showing the state of the step of removing the polysilicon layer shown;

[0034] Figure 9 Shows Figure 1 A process state schematic view of the step of removing the dummy layer in the manufacturing method of the existing FinFET infrastructure shown;

[0035] Figure 10 Shows Figure 9 A cross-sectional schematic view in the E-E direction showing the state of the step of removing the dummy layer shown;

[0036] Figure 11 Shows Figure 1 A process state schematic view of the oxide film growth step in the manufacturing method of the existing FinFET infrastructure shown;

[0037] Figure 12 Shows Figure 11 A cross-sectional schematic view in the F-F direction showing the state of the oxide film growth step shown;

[0038] Figure 13 Shows Figure 1Schematic diagram of the process state of the high-k dielectric material / TiN deposition step in the manufacturing method of the existing FinFET basic structure shown;

[0039] Figure 14 Shows Figure 13 Cross-sectional schematic diagram in the G-G direction showing the state of the high-k dielectric material / TiN deposition step shown;

[0040] Figure 15 Shows Figure 1 Schematic diagram of the process state of the capping layer formation step in the manufacturing method of the existing FinFET basic structure shown;

[0041] Figure 16 Shows Figure 15 Cross-sectional schematic diagram in the H-H direction showing the state of the capping layer formation step shown;

[0042] Figure 17 Shows Figure 1 Schematic diagram of the process state of the capping layer removal step in the manufacturing method of the existing FinFET basic structure shown;

[0043] Figure 18 Shows Figure 17 Cross-sectional schematic diagram in the I-I direction showing the state of the capping layer removal step shown;

[0044] Figure 19 Shows Figure 1 Schematic diagram of the process state of the metal gate formation step in the manufacturing method of the existing FinFET basic structure shown;

[0045] Figure 20 Shows Figure 19 Cross-sectional schematic diagram in the J-J direction showing the state of the metal gate formation step shown;

[0046] Figure 21 Schematic diagram of the state of the first step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;

[0047] Figure 22 Schematic diagram of the state of the second step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;

[0048] Figure 23 Schematic diagram of the state of the third step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;

[0049] Figure 24 Schematic diagram of the state of the fourth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;

[0050] Figure 25Schematic diagram showing the state of the fifth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;

[0051] Figure 26 Schematic diagram showing the state of the sixth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;

[0052] Figure 27 Schematic diagram showing the state of the seventh step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;

[0053] Figure 28 Schematic diagram showing the state of the eighth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;

[0054] Figure 29 Schematic diagram showing the state of the ninth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;

[0055] Figure 30 Schematic diagram showing the state of the tenth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention. Detailed implementation manners

[0056] In order to make the technical objectives, technical solutions and technical effects of the present invention clearer, so as to facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Refer to Figures 21 - 30 , Figure 21 Schematic diagram showing the state of the first step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 22 Schematic diagram showing the state of the second step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 23 Schematic diagram showing the state of the third step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 24 Schematic diagram showing the state of the fourth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 25 Schematic diagram showing the state of the fifth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 26 Schematic diagram showing the state of the sixth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 27 Schematic diagram showing the state of the seventh step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention; Figure 28 Schematic diagram showing the state of the eighth step of the manufacturing method of the FinFET basic structure according to a preferred embodiment of the present invention;Figure 29 The ninth step state diagram of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention is shown; Figure 30 The tenth step state diagram of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention is shown. Specifically, the manufacturing method of the FinFET basic structure includes the following steps:

[0058] Step 1: Provide a substrate, which includes a STI layer 100, a plurality of fins 200 inserted on the STI layer 100, a dummy layer 300, and a polysilicon layer 400 covering the STI layer 100 and the dummy layer 300, as Figure 21 shown; the dummy layer 300 is covered and disposed on the outer walls of the fins 200 above the top surface of the STI layer 100;

[0059] In this step, both the STI layer 100 and the dummy layer 300 are made of SiO2.

[0060] Step 2: Open a groove 500 on the substrate through an etching technique; the groove 500 penetrates through the polysilicon layer 400 and extends into the interior of the STI layer 100, as Figure 22 shown;

[0061] Step 3: Oxidize a part of the inner wall of the groove 500 near its opening to form a first oxide layer 510, and make the bottom of the groove 500 protrude to form a convex groove 530, as Figure 23 shown;

[0062] In this step, by controlling the process conditions, the thickness of the first oxide layer 510 is made less than the thickness of the dummy layer 300, so that in the subsequent process of removing the dummy layer, the first oxide layer is removed together and the complete removal of the first oxide layer is ensured.

[0063] In this step, by oxidizing the polysilicon layer 400 with an oxidant under heating conditions, the first oxide layer 510 can be formed on the inner wall of the groove 500, and at the same time, the bottom of the groove 500 can be made to protrude to form the convex groove 530.

[0064] Step 4: Fill the groove 500 and the convex groove 530 with a filling material to form a filling member 520; wherein, the filling material filled in the convex groove 530 forms a protruding portion 521 of the filling member 520, as Figure 24 shown;

[0065] In this step, the filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or a metal oxide, and the metal oxide is Al2O3, TiO2, an oxide of hafnium or an oxide of zirconium.

[0066] In this embodiment, the protruding portion 521 is disposed around the filling member 520 to form a bottom frustum contour structure with a gradually decreasing diameter from bottom to top.

[0067] Further, the filling member is used to isolate adjacent gates.

[0068] Step 5: Remove the polysilicon layer 400, as Figure 25 shown; then remove the dummy layer 300 and the first oxide layer 510 to expose the protruding portion 521 of the filling member 520, as Figure 26 shown; then form a second oxide layer 540 on the outer wall of the fin 200 above the top surface of the STI layer 100; then successively form a high-k dielectric material layer 600 and a first TiN layer 700 by deposition techniques; wherein, the high-k dielectric material layer 600 covers the outer wall of the second oxide layer 540, the top surface of the STI layer 100, and the outer wall of the filling member 520 above the top surface of the STI layer 100; the first TiN layer 700 covers the high-k dielectric material layer 600, as Figure 27 shown;

[0069] The high-k dielectric material layer 600 refers to a material with a dielectric constant higher than that of SiO2.

[0070] In this step, exposing the protruding portion 521 of the filling member 520 includes: the step of making at least one contour turning point or contour turning line of the protruding portion 521 located above the top surface of the STI layer 100.

[0071] Preferably, in this step, the high-k dielectric material layer 600 can be made of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, or Al2O3.

[0072] Step 6: Form a capping layer 800 on the first TiN layer 700 and perform capping annealing, as Figure 28 shown; then remove the capping layer 800, as Figure 29 shown, and then dispose a metal layer 910 at the position of the removed capping layer 800 to form a metal gate, as Figure 30 shown. The capping layer 800 is made of Si.

[0073] In this step, as Figure 30 shown, after removing the capping layer 800, it further includes successively forming a TaN layer 920 and a second TiN layer 930 by deposition methods, and then disposing a metal layer 910 on the second TiN layer 930 to form a metal gate. Preferably, the metal layer 910 is made of W.

[0074] Through the above manufacturing method of the FinFET basic structure, the problem of residual Si during the removal of the capping layer is avoided by using the protruding portion.

[0075] Specifically, the filling groove in the present invention includes an upper portion located in the polysilicon layer and a groove bottom extending deep into the STI layer. By utilizing the inconsistency of the materials of the polysilicon layer and the STI layer, the inner wall of the polysilicon layer in the groove is oxidized to form a first oxide layer, while the silicon oxide material of the STI layer is not affected, so that the groove bottom protrudes to form a convex groove.

[0076] Subsequently, during the process of removing the dummy layer and re-depositing the second oxide layer, firstly, the first oxide layer is completely removed while removing the dummy layer without adding an additional removal step; secondly, by removing the dummy layer, the raised portion is ensured to be higher than the surface of the STI layer, so that it is exposed.

[0077] Furthermore, if Figure 30 As shown, the present invention also proposes a FinFET basic structure, including a substrate; the substrate includes an STI layer 100 and a plurality of fins 200 inserted on the STI layer 100;

[0078] The FinFET basic structure further includes a filler 520 inserted on the STI layer 100; a protrusion 521 is formed on the sidewall of the bottom of the filler 520; the protrusion 521 protrudes from the top surface of the STI layer 100;

[0079] The FinFET basic structure also includes a high dielectric constant material layer 600 covering the substrate and the portion of the sidewall of the filler 520 located above the STI layer 100; a first TiN layer 700 is covered on the high dielectric constant material layer 600; a TaN layer 920 is covered on the first TiN layer 700, a second TiN layer 930 is covered on the TaN layer 920, and a metal layer 910 is covered on the second TiN layer 930.

[0080] In the above technical solution, at least one profile turning point or profile turning line of the protrusion 521 is located above the top surface of the STI layer 100; in this embodiment, the protrusion 521 is arranged around the filler 520 to form a bottom frustum profile structure with a gradually decreasing diameter from bottom to top.

[0081] In the above technical solution, the STI layer 100 is made of SiO 2 .

[0082] The filler 520 is made of SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide.

[0083] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A manufacturing method of a FinFET basic structure, characterized in that, It includes the following steps: Step S1: Provide a substrate, and then open a groove (500) on the substrate through an etching technique; Step S2: Oxidize a part of the inner wall of the groove (500) near its opening to form a first oxide layer (510), and make the bottom of the groove (500) protrude to form a protruding groove (530); Step S3: Fill the groove (500) and the protruding groove (530) with a filling material to form a filling member (520); wherein, the filling material filled in the protruding groove (530) forms a protruding portion (521) of the filling member (520); Step S4: Remove a part of the substrate, so that the protruding portion (521) of the filling member (520) is exposed; Step S5: Form a capping layer (800) to cover the protruding portion (521) of the filling member (520); then anneal to remove the capping layer (800); and then arrange a metal layer (910) at the position where the capping layer (800) has been removed to form a metal gate.

2. The manufacturing method of the FinFET basic structure according to claim 1, wherein In step S1, the substrate includes a STI layer (100), a plurality of fins (200) inserted on the STI layer (100), a dummy layer (300), and a polysilicon layer (400) covering the STI layer (100) and the dummy layer (300). The dummy layer (300) covers the outer walls of the fins (200) above the top surface of the STI layer (100). The groove (500) penetrates the polysilicon layer (400) and extends into the STI layer (100).

3. The manufacturing method of the FinFET basic structure according to claim 2, characterized in that Step S4 further includes: removing the polysilicon layer (400); and then removing the dummy layer (300) and the first oxide layer (510) to expose the protruding portion (521) of the filling member (520).

4. The manufacturing method of the FinFET basic structure according to claim 3, characterized in that, Step S5 further includes: forming a second oxide layer (540) on the outer walls of the fins (200) above the top surface of the STI layer (100); then successively forming a high-k dielectric material layer (600) and a first TiN layer (700) through a deposition technique; wherein, the high-k dielectric material layer (600) covers the outer walls of the second oxide layer (540), the top surface of the STI layer (100), and the outer walls of the filling member (520) above the top surface of the STI layer (100); the first TiN layer (700) covers the high-k dielectric material layer (600); and then, a capping layer (800) is formed on the first TiN layer (700).

5. The manufacturing method of the FinFET basic structure according to claim 4, characterized in that, Both the STI layer (100) and the dummy layer (300) are made of SiO2; the thickness of the first oxide layer (510) is less than the thickness of the dummy layer (300); The filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or a metal oxide. Among them, the metal oxide is Al2O3, TiO2, an oxide of hafnium or an oxide of zirconium; The high-k dielectric material layer (600) is made of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2 or Al2O3; The metal layer (910) is made of W.

6. The manufacturing method of the FinFET basic structure according to claim 1, characterized in that, In step S4, exposing the protrusion (521) of the filler (520) includes: the step of making at least one contour turning point or contour turning line of the protrusion (521) be above the top surface of the STI layer (100).

7. The manufacturing method of the FinFET basic structure according to claim 1, characterized in that, In step S5, after removing the capping layer (800), it further includes the steps of successively forming a TaN layer (920) and a second TiN layer (930) by a deposition method, and then disposing a metal layer (910) on the second TiN layer (930) to form a metal gate.

8. A FinFET basic structure manufactured by the method described in claim 1, characterized in that, It includes a substrate, and the substrate includes an STI layer (100); the FinFET basic structure further includes a filler (520) inserted on the STI layer (100); a protrusion (521) protrudes from the side wall at the bottom of the filler (520); the protrusion (521) protrudes above the top surface of the STI layer (100); The FinFET basic structure further includes a metal gate covering the STI layer (100) and the part of the side wall of the filler (520) above the STI layer (100); at least one contour turning point or contour turning line of the protrusion (521) is above the top surface of the STI layer (100).

9. The FinFET basic structure according to claim 8, wherein, The protrusion (521) is arranged around the filler (520) to form a bottom frustum contour structure with a gradually decreasing diameter from bottom to top.

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