Measuring method of hard mask layer etching deviation in self-aligned imaging process

Abstract

The present invention provides a method for measuring shear layer etching deviation in a self-aligned imaging process. A test pattern is designed. The main layout includes sacrificial layer patterns that are evenly spaced in the X direction and sequentially distributed with a fixed offset in the Y direction, and multiple rows of shear layer patterns that are evenly spaced in the X and Y directions. The period of two adjacent sacrificial layer patterns in each column in the Y direction is consistent with the period of the shear layer pattern. The test pattern is transferred to a photomask and, after a series of photolithography and etching processes, inspected using a large-field inspection tool. The position of the fin structure that has just been completely sheared off and the fin structure that has just been sheared in is used to determine the boundary of the etched pattern. The present invention accurately determines the boundary of the shear layer AEI CD, thereby determining the etching deviation, providing a reference for adjusting the optical proximity effect correction / photolithography / etching process, improving the accuracy of process correction and adjustment, and reducing the occurrence of defects.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for measuring etching deviation of a hard mask layer in a self-aligned imaging process. Background Art

[0002] In the FinFet (fin transistor) process, the SADP (self-aligned double patterning) process is first used to define the entire fin, and then the redundant fins are removed through shear layers parallel to the fin and perpendicular to the fin to define the active area. For the shear layer parallel to the fin, the ideal situation is to etch away the redundant entire fin without damaging the upper and lower fins. Figure 1 , respectively, are the overall fin and the active area defined by the shear layer. The dotted line area is the shear layer area parallel to the fin. The fin near the shear layer boundary has obvious fin damage.

[0003] From the layout file to the final active area, the process goes through OPC (optical proximity effect) correction, photolithography process, and etching process. Each step may cause fin damage. Among them, due to the three-dimensional structure of the underlying layer, for the shear layer parallel to the fin, the etching process does not leave an imprint on the underlying layer after the completion of the etching process. Therefore, it is impossible to directly measure the AEI CD (after-etch critical dimension measurement) and understand the etching deviation and its impact on fin damage. Figure 2 As shown, designing the mark on a large active area or STI (shallow trench isolation) cannot simulate the actual etching behavior in the chip. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention aims to provide a method for measuring the etching deviation of a hard mask layer in a self-aligned imaging process. This method is used to address the problem in the prior art that, due to the three-dimensional structure of the underlying layer, the etching process does not leave an imprint on the underlying layer for the shear layer parallel to the fin. Therefore, it is impossible to directly measure the critical dimensions after development, unable to obtain the etching deviation and its impact on fin damage, and unable to simulate the actual etching behavior in the chip.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for measuring the etching deviation of a hard mask layer in a self-aligned imaging process, comprising:

[0006] Step 1: Design a main layout, wherein the main layout includes sacrificial layer patterns that are evenly spaced in the X direction and sequentially distributed with a fixed offset in the Y direction, and multiple rows of shear layer patterns that are evenly spaced in the X and Y directions;

[0007] The X direction is parallel to the main layout, and the Y direction is perpendicular to the X direction and parallel to the main layout;

[0008] The plurality of sacrificial layer patterns in each row extend at least from being flush with the upper edge of the shearing layer pattern to being flush with the lower edge thereof along the Y direction;

[0009] The period of two adjacent sacrificial layer patterns in each column in the Y direction is consistent with the period of the shear layer patterns;

[0010] Step 2: Design a test key pattern, wherein the test key pattern includes at least 10 rows of the shear layer patterns and all the sacrificial layer patterns thereon;

[0011] Step 3: Providing a substrate on which a plurality of fin structures, a hard mask layer covering the plurality of fin structures, and a sacrificial layer covering the hard mask layer are formed; then forming a photoresist layer on the sacrificial layer; transferring the test key pattern to the photoresist layer by photolithography; and then measuring the photoresist layer after photolithography to obtain the ADI critical dimension;

[0012] Step 4: etching the substrate, and determining the boundary of the etched pattern by the positions of the fin structure that has just been completely sheared off and the fin structure that has just been sheared, thereby obtaining the AEI critical dimension;

[0013] Step 5: Obtain an etching deviation according to the ADI critical dimension and the AEI critical dimension.

[0014] Preferably, the length of the sacrificial layer pattern in step 1 is greater than or equal to five times its width.

[0015] Preferably, the fixed offset in step 1 is zero, and a plurality of sacrificial layer patterns in the same row are merged.

[0016] Preferably, the fixed offset in step 1 is an integer multiple of the minimum grid point in the layout design rules.

[0017] Preferably, the test key pattern in step 2 is set in the chip.

[0018] Preferably, the test key pattern in step three is arranged on the cutting path.

[0019] Preferably, the method is used to characterize any one-step shear layer process among SADP, SAQP and SAOP processes.

[0020] Preferably, in step three, the ADI critical dimension is obtained by SEM measurement or OCD measurement.

[0021] Preferably, in step 4, a large-field detection and analysis tool is used to obtain the AEI CD.

[0022] Preferably, the inspection of the substrate in step 4 includes critical dimension inspection and defect inspection of the fin structure.

[0023] Preferably, the method for etching the substrate in the SAOP process includes:

[0024] (1) etching the sacrificial layer using the photoresist layer after photolithography as a mask;

[0025] (2) removing the photoresist layer;

[0026] (3) forming sidewalls on the sidewalls of the etched sacrificial layer;

[0027] (4) removing the remaining sacrificial layer;

[0028] (5) Using the sidewall as a mask, the hard mask layer and the fin structure thereunder are etched.

[0029] Preferably, the material of the hard mask layer in step three is silicon dioxide or silicon nitride.

[0030] Preferably, the sacrificial layer material in step three is amorphous silicon.

[0031] Preferably, the material of the sidewall in step (3) is silicon dioxide or silicon nitride.

[0032] As described above, the method for measuring the etching deviation of the hard mask layer in the self-aligned imaging process of the present invention has the following beneficial effects: the present invention can accurately simulate the actual etching process of the fin structure layer through the design of the test key, so that the etching behavior of the test key is consistent with the main board. Figure 1 The test key design allows for the measurement of the critical AEI dimensions of the shear layer on the 3D fin structure. Large-field detection tools are used to measure the entire chip on the test key, reducing the impact of random factors and accurately determining the boundaries of the critical AEI dimensions of the shear layer. This, in turn, helps determine the etching deviation, providing a reference for adjustments to the optical proximity effect correction / lithography / etching processes. This improves the accuracy of process corrections and adjustments, and reduces the occurrence of defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a schematic diagram of damage to fins caused by etching in the prior art;

[0034] Figure 2 Shown is a schematic diagram of marking on a substrate in the prior art;

[0035] Figure 3 Shown is a schematic diagram of the overall design of the test key of the present invention;

[0036] Figure 4 Shown as the present invention Figure 3 A partial enlarged schematic diagram;

[0037] Figure 5 Shown as the present invention Figure 4 A partial enlarged schematic diagram;

[0038] Figure 6 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] See also Figure 6 The present invention provides a method for measuring the etching deviation of a hard mask layer in a self-aligned imaging process, comprising:

[0041] Step 1, see Figures 3 to 5 , design a main layout, which includes sacrificial layer patterns 20 (mandrel) distributed at equal intervals in the X direction and distributed sequentially with a fixed offset in the Y direction, and multiple rows of cut layer patterns 10 (cut layer) distributed at equal intervals in the X and Y directions; the cut layer patterns 10 (cut layer) are used to define the positions of the cut layers on the substrate parallel to and perpendicular to the fin structures, and to remove excess fins to define the active area. Multiple sacrificial layer patterns 20 (mandrel) are provided on each row of the cut layer patterns 10, and all the sacrificial layer patterns 20 are distributed at equal intervals in the X direction and distributed sequentially with a fixed offset in the Y direction;

[0042] The X direction is parallel to the main layout, and the Y direction is perpendicular to the X direction and parallel to the main layout;

[0043] The plurality of sacrificial layer patterns 20 in each row extend at least from being flush with the upper edge of the shear layer pattern 10 to being flush with the lower edge thereof along the Y direction;

[0044] The distance between two adjacent sacrificial layer patterns 20 in each column in the Y direction is consistent with the distance between the shear layer patterns 10;

[0045] In an optional embodiment, the length of the sacrificial layer pattern 20 in step 1 is greater than or equal to five times the width.

[0046] In an optional embodiment, the fixed offset in step 1 is zero, and multiple sacrificial layer patterns 20 in the same row are merged. That is, each row of shear layer patterns 10 has a whole sacrificial layer pattern 20 distributed in sequence in the Y direction with a fixed offset difference.

[0047] In an optional embodiment, the fixed offset in step 1 is an integer multiple of the minimum grid point in the layout design rules.

[0048] Step 2: Design a test key pattern. The test key pattern includes at least 10 lines of shear layer patterns 10 and all the sacrificial layer patterns 20 thereon. Then, place the test key pattern on the mask and print it. The design of the test key can accurately simulate the actual etching process of the fin structure layer, making the etching behavior of the test key consistent with the main board. Figure 1 To;

[0049] In an optional embodiment, the test key pattern in step 2 is set in the chip layout. After the chip is manufactured according to the main layout, the test key manufactured according to the test key pattern is located inside the chip.

[0050] In an optional implementation, the test key pattern in step three is set on the cutting path layout. After the chip is manufactured according to the main layout, the test key manufactured according to the test key pattern is located on the cutting path.

[0051] Step 3: Providing a substrate on which a plurality of fin structures, a hard mask layer covering the plurality of fin structures, and a sacrificial layer covering the hard mask layer are formed. The sacrificial layer is typically deposited by CVD, and then a photoresist layer is formed on the sacrificial layer. A test key pattern is transferred to the photoresist layer by photolithography to define the location where the sacrificial layer is etched. The photoresist layer after photolithography is then measured to obtain the ADI CD (critical dimension);

[0052] In an optional embodiment, in step three, SADP is used to etch the substrate.

[0053] In an optional embodiment, in step three, SEM measurement or OCD measurement is used to obtain the ADI critical dimension.

[0054] Preferably, the method is used to characterize any one-step shear layer process among SADP (self-aligned double patterning), SAQP (self-aligned quadruple patterning) and SAOP (self-aligned octuplet patterning) processes.

[0055] In an optional embodiment, the method for etching a substrate using a SAOP process includes:

[0056] (1) Etching the sacrificial layer using the photoresist layer after photolithography as a mask. The etched sacrificial layer pattern 20 is called "mandrel" or "core";

[0057] (2) removing the photoresist layer;

[0058] (3) forming sidewalls on the sidewalls of the etched sacrificial layer. Typically, ALD is used to deposit a thin film of relatively uniform thickness on the surface and side surfaces of the remaining sacrificial layer after etching, and then back-etching is used to form sidewalls on the sidewalls of the sacrificial layer.

[0059] (4) Use a highly selective etching solution to remove the remaining sacrificial layer;

[0060] (5) Using the sidewall as a mask, the hard mask layer and the fin structure underneath are etched.

[0061] In an optional embodiment, the material of the hard mask layer in step three is silicon dioxide or silicon nitride.

[0062] In an optional embodiment, the sacrificial layer material in step three is amorphous silicon.

[0063] In an optional embodiment, the material of the sidewall in step (3) is silicon dioxide or silicon nitride.

[0064] Step 4: Etching the substrate so that some of the multiple fin structures are completely etched and others are partially etched. The substrate is then inspected to determine the boundaries of the etched pattern based on the locations of the completely etched fin structures and the locations of the recently etched fin structures, thereby obtaining the AEI CD.

[0065] Preferably, in step 4, any one of the medium-large field detection and analysis tools among EP5, Provision and Anchor is used to obtain AEI CD.

[0066] Preferably, the substrate inspection in step 4 includes critical dimension inspection and defect inspection of the fin structure.

[0067] Step 5: Obtain etching bias based on ADI CD and AEI CD.

[0068] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0069] In summary, the present invention can accurately simulate the actual etching process of the fin structure layer through the design of the test key, so that the etching behavior of the test key is consistent with the main board. Figure 1 The design of the test key allows for measurement of the AEI CD of the shear layer located on the three-dimensional fin structure. Using a large-field inspection tool, the test key is used to measure the entire chip, reducing the influence of random factors and accurately determining the boundaries of the shear layer AEI CD. This, in turn, determines etching deviation, providing a reference for optical proximity correction, photolithography, and etching process adjustments. This improves the accuracy of process corrections and adjustments and reduces the occurrence of defects. Therefore, this invention effectively overcomes the shortcomings of the prior art and has high industrial application value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for measuring etching deviation of a hard mask layer in a self-aligned imaging process, characterized in that: At least: Step 1: Design a main layout, wherein the main layout includes sacrificial layer patterns that are evenly spaced in the X direction and sequentially distributed with a fixed offset in the Y direction, and multiple rows of shear layer patterns that are evenly spaced in the X and Y directions; The X direction is parallel to the main layout, and the Y direction is perpendicular to the X direction and parallel to the main layout; The plurality of sacrificial layer patterns in each row extend at least from being flush with the upper edge of the shearing layer pattern to being flush with the lower edge thereof along the Y direction; The period of two adjacent sacrificial layer patterns in each column in the Y direction is consistent with the period of the shear layer pattern; wherein the fixed offset is an integer multiple of the minimum grid point in the layout design rule; Step 2: Design a test key pattern, wherein the test key pattern includes at least 10 rows of the shear layer patterns and all the sacrificial layer patterns thereon; Step 3: Providing a substrate on which a plurality of fin structures, a hard mask layer covering the plurality of fin structures, and a sacrificial layer covering the hard mask layer are formed; then forming a photoresist layer on the sacrificial layer; transferring the test key pattern to the photoresist layer by photolithography; and then measuring the photoresist layer after photolithography to obtain the ADI critical dimension; Step 4: etching the substrate, and determining the boundary of the etched pattern by the positions of the fin structure that has just been completely sheared off and the fin structure that has just been sheared, thereby obtaining the AEI critical dimension; Step 5: Obtain an etching deviation according to the ADI critical dimension and the AEI critical dimension; the method is used to characterize any shear layer process in SADP, SAQP and SAOP processes.

2. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The length of the sacrificial layer pattern in step 1 is greater than or equal to five times its width.

3. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The fixed offset in step 1 is zero, and the multiple sacrificial layer patterns in the same row are merged.

4. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The test key pattern in step 2 is set in the chip layout.

5. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The test key pattern in step 2 is set on the cutting path layout.

6. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: In step three, the ADI critical dimensions are obtained by SEM measurement or OCD measurement.

7. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: In step 4, a large-field detection and analysis tool is used to obtain the AEI critical dimension.

8. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The inspection of the substrate in step 4 includes critical dimension inspection and defect inspection of the fin structure.

9. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The method for etching the substrate in the SAOP process includes: (1) etching the sacrificial layer using the photoresist layer after photolithography as a mask; (2) removing the photoresist layer; (3) forming sidewalls on the sidewalls of the etched sacrificial layer; (4) removing the remaining sacrificial layer; and (5) etching the hard mask layer and the fin structure thereunder using the sidewalls as a mask.

10. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The material of the hard mask layer in step three is silicon dioxide or silicon nitride.

11. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 1, wherein: The sacrificial layer material in step three is amorphous silicon.

12. The method for measuring etching deviation of a hard mask layer in a self-aligned imaging process according to claim 9, wherein: The material of the sidewall in step (3) is silicon dioxide or silicon nitride.

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