Split gate channel mos transistor with self-aligned gate region and body region

Abstract

Embodiments of this disclosure relate to a split-gate channel MOS transistor having a self-aligned gate region and a body region. A method for fabricating an integrated device having at least one MOS transistor integrated on a die of semiconductor material is proposed. The method includes forming one or more gate trenches having corresponding field plates and gate regions. The body region is formed by selectively implanting dopant along one or more implantation directions inclined relative to the front surface of the die. Furthermore, corresponding integrated devices and systems including such integrated devices are proposed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of integrated devices. More specifically, the present disclosure relates to MOS transistors. BACKGROUND

[0002] The background of the present disclosure is introduced below and discussed in the context of technology related to it. However, even if this discussion refers to a document, act, manufacture, or any other disclosure, it is not suggested or indicated that the discussed technology is part of the prior art or related to the common general knowledge in the field of the present disclosure.

[0003] Integrated devices based on MOS transistors are commonly used for a variety of applications. In particular, MOS transistors are one of the most common components in power applications, where large amounts of electrical energy are handled; in this case, MOS transistors are designed to work at relatively high voltages and / or currents.

[0004] A (power) MOS transistor typically has a cell-like structure. Each MOS transistor replicates the same structure in a plurality of cells, which are formed in the same semiconductor material die of the integrated MOS transistor; the cells include corresponding (basic) gate and source regions, which are connected in parallel, e.g. in the form of alternating strips (providing a high perimeter / area ratio of the source regions). Moreover, MOS transistors typically have a vertical structure. Each MOS transistor has a (common) source region at the front surface of the die, opposite to a drain region at the back surface of the die; in this way, a channel is formed between the source and drain regions, which extends through the die in operation. All this allows the MOS transistor to sustain high currents (due to its wide channel) and high voltages (due to its long channel) within a relatively small die area.

[0005] In particular, in trench-gate MOS transistors, the gate regions are formed in corresponding trenches, which extend from the front surface of the die; each trench is coated with an (relatively thin) insulating layer, and then filled with an electrically conductive material (e.g. doped polysilicon) forming the gate region. In this way, the channel of the MOS transistor is formed along the (vertical) walls of the trench.

[0006] MOS transistors can also be provided with field plates. Each field plate includes an (insulated) region of electrically conductive material, which is arranged between the corresponding gate and drain regions (close to the corresponding channel). In operation, the field plate is kept at a reference voltage (or ground). The field plate reduces the gate / drain capacitance Cdg of the MOS transistor; this correspondingly increases the switching frequency of the MOS transistor. Moreover, the field plate reduces the drain / source on-state or output resistance RDSon of the MOS transistor; this correspondingly increases the safe operating area (SOA) of the MOS transistor.

[0007] In particular, in split-gate (or shielded-gate) MOS transistors, the field plate is formed by a corresponding additional gate region (shielded gate) buried in its segment. The field plate is arranged below the corresponding actual gate region (upper gate), which controls the formation of the corresponding channel of the MOS transistor, as usual.

[0008] Accordingly, the body region of the MOS transistor (in which the source region is formed) should remain as much as possible at the same depth as the gate region in the die. To this end, after coating each trench with an insulating layer and filling it with doped polysilicon, the insulating layer is etched into the recessed trench until a level corresponding to the desired thickness of the field plate. The insulating material is then deposited over the entire die, and then etched to form the (relatively thick) insulating layer in the trench above the field plate. At this point, the trench is again filled with doped polysilicon to form the gate region.

[0009] However, due to the etching carried out to form the field plate and the gate region, the thickness of the corresponding insulating layer between the field plate and the gate region is affected by a (relatively large) spread. As a result, the body region and the gate region can be at different depths in the die. This misalignment (between the body region and the gate region) produces a corresponding variation (and increase) in the gate / drain capacitance Cdg of the MOS transistor. In addition, the same misalignment significantly increases the drain / source on-state resistance RDSon of the MOS transistor. Thus, the increased gate / drain capacitance Cdg reduces the switching frequency, while the increased on-state resistance RDSon correspondingly reduces the SOA of the MOS transistor. All of this has a detrimental effect on the performance of the MOS transistor (partially undermining the advantages offered by the split-gate structure). SUMMARY

[0010] In order to provide a basic understanding of the present disclosure, a simplified summary of the present disclosure is given here; however, the sole purpose of this summary is to introduce some concepts of the present disclosure in a simplified form, as a prelude to the more detailed description below, and it should not be interpreted as identifying key elements or describing the scope thereof.

[0011] In general, the present disclosure is based on the idea of self-alignment of the body region with the gate region.

[0012] In particular, one aspect provides a method for manufacturing an integrated device comprising at least one MOS transistor integrated on a die of a semiconductor material. The process comprises forming one or more gate trench regions having corresponding field plates and gate regions; a body region is formed by selectively implanting dopants along one or more implantation directions, said implantation directions being inclined with respect to the front surface of the die.

[0013] Another aspect provides a corresponding integrated device.

[0014] A system is provided in another aspect, comprising at least one integrated device as described above.

[0015] More specifically, one or more aspects of the present disclosure are set forth in the independent claims, which are advantageous per se, while advantageous features are set forth in the dependent claims, which are advantageous per se, all of which are hereby incorporated by reference in the detailed description (any advantageous feature provided in relation to any particular aspect being applicable mutatis mutandis to all other aspects). BRIEF DESCRIPTION OF DRAWINGS

[0016] The solution of the present disclosure, and its further features and advantages, will be best understood by reading the following detailed description, given purely by way of non- limiting indication, in conjunction with the accompanying drawings, which are provided purely by way of non-limiting indication, and in which: Figure One from the very beginning (where, for simplicity, corresponding elements are denoted with the same or similar references, whose explanation is not repeated, the name of each entity being typically used to indicate its type and properties, such as values, contents and representations) in this respect, it is expressly specified that the drawings are not necessarily to scale (certain details can be exaggerated and / or simplified) and unless otherwise specified, are merely intended to conceptually illustrate the structures and procedures described herein. In particular:

[0017] Figure 1 a partial view in a cross-sectional view of an integrated device according to an embodiment of the present disclosure is shown,

[0018] Figures 2A-2M main steps of a manufacturing process of an integrated device according to an embodiment of the present disclosure are shown, and

[0019] Figure 3 a schematic block diagram of a system comprising an integrated device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] With particular reference to Figure 1 a partial view in a cross-sectional view of an integrated device 100 according to an embodiment of the present disclosure is shown.

[0021] The integrated device 100 comprises a MOS transistor 105 (or more). The MOS transistor 105 has a vertical structure of split channel gate (STG) type. The MOS transistor 105 implements a power component, which is designed for handling relatively high electric power (e.g. of the order of magnitude of more than 10 w), e.g. operating at corresponding relatively high electric current and / or voltage (e.g. of the order of magnitude of more than 10 A and 10 V, respectively).

[0022] MOS transistor 105 is integrated on a semiconductor body, such as a die 110 of semiconductor material, for example, silicon (to define the corresponding chip). Typically, the concentration of N-type and P-type dopants (or impurities) in the semiconductor material is indicated by adding the symbols + or - to the letters N and P, respectively, to represent high or low concentrations of impurities, or by adding the symbols ++ or -- to represent extremely high or extremely low concentrations of impurities. Correspondingly, N and P without any + or - symbols represent intermediate concentrations. Die 110 includes an N++ type substrate 115 (actually thicker), on which an N-type (thin) epitaxial layer 120 is disposed. The free master surfaces of the epitaxial layer 120 define the front surface 125f of the epitaxial layer 120 of the die 110, while the free master surfaces of the substrate 115 define the rear surface 125b of the substrate 115 of the die 110 (opposite to each other).

[0023] The MOS transistor 105 includes the following components: A region N++ type drain region is defined by a substrate 115 (extending from the back surface 125b to the die 110). A region P type body region 130 extends from the front surface 125f into the epitaxial layer 120 to remain separate from the drain region 115. The MOS transistor 105 has a cell structure with the same structure replicated in multiple cells (e.g., 100-1,000). Specifically, each cell includes the following components: A region N+ type source region 135 extends from the front surface 125f to the body region 130. A gate trench 140 extends into the body region in the gate and then into the epitaxial layer 120 from the front surface 125f. The gate trench 140 is coated with an (electrically) insulating material (e.g., silicon oxide); specifically, a gate insulating layer 145 (relatively thin) covers the upper portion of the gate trench 140 (which may be referred to herein as the outer portion), extending substantially from the front surface 120f to the same depth as the body region 130 of the gate trench 140, while a (relatively thick) separating insulating layer 150 covers the (remaining) lower portion of the gate trench 140 (which may be referred to herein as the inner portion). The (coated) gate trench 140 is filled with an (electrically) conductive material, such as N+-doped polysilicon, which is split into an upper region defining a gate region 155 and a lower portion of a field plate (or shielding gate) 160 defined by a (relatively thick) split insulating layer 165 of (electrically) insulating material (e.g., silicon oxide); the split insulating layer 165 extends between the gate insulating layer 145 and the split insulating layer 150 such that the gate region 155 is substantially at the same depth as the body region 130 in the die 110.

[0024] The MOS transistor 105 has an interdigitated structure; specifically, in a plan view (on the front surface 125f), the source region 135 and the gate region 155 have elongated shapes (strips) and are arranged in parallel, alternating with each other (like crossed fingers). A drain contact 170 of conductive material (e.g., metal) contacts the drain region 115. A protective layer 175 of (electrically) insulating material (e.g., silicon dioxide) covers the front surface 125f (partially cut out in the figure for clarity). A source contact 180 of conductive material (e.g., metal) contacts all source regions 135 and the body region 130 through the protective layer 175. A gate contact 185 of conductive material (e.g., metal) contacts all gate regions 155 through the protective layer 175. Another contact (not shown) contacts all field plates 160 (in a portion of the gate trench 140 without the gate region 155 and the split insulating layer 165, wherein the field plates 160 extend upward to the front surface 125f).

[0025] Now for reference Figures 2A-2M The main steps of the manufacturing process of the integrated device according to embodiments of the present disclosure are shown.

[0026] In particular, the figure shows a (partial) cross-sectional view of the corresponding plane perpendicular to the front surface, which extends parallel (to the left) and laterally (to the right) relative to the longitudinal axis of the trench gate.

[0027] from Figure 2A Initially, the manufacturing process is typically performed at the level of semiconductor material wafer 305, where the same structure is simultaneously integrated in a large number of identical regions (for simplicity, only one will be mentioned below). Wafer 305 includes an N++ type substrate, which will form the substrate of the integrated device, and is denoted by the same reference numeral 115. An N-type epitaxial layer is thermally grown on substrate 115, which will form the epitaxial layer of the integrated device, and is denoted by the same reference numeral 120. A mask 310 for the gate trench is formed on the free master surface of epitaxial layer 120, which will form the front surface of the integrated device, and is denoted by the same reference numeral 125f; for example, mask 310 is obtained by growing a (relatively thick) silicon oxide layer using a thermal oxidation step, and then etching it using a photoresist layer that is appropriately patterned (and then stripped) using photolithography. Wafer 305 is etched through mask 310 (e.g., using a dry etching step) to form gate trench 140.

[0028] Move to Figure 2B The mask is removed. A silicon oxide layer 315 is formed on the wafer 305, i.e. on the front surface 125f and the exposed surface of the gate trench 140 (e.g., using a combination of thermal oxidation and deposition steps); the silicon oxide layer 315 is relatively thick (e.g., having a thickness of 100-200 nm).

[0029] Move to Figure 2C An N+ type doped polysilicon layer 320, namely a silicon oxide layer 315, is deposited on the wafer to fill the (coated) gate trench 140 and cover the (coated) front surface 125f.

[0030] Move to Figure 2D The doped polysilicon layer is etched downwards (e.g., using dry etching) into the gate trench 140 so that it is retained only in its lower portion; the remaining layer of doped polysilicon then forms the field plate 160 (with a desired thickness depending on the voltage to be carried by the MOS transistor).

[0031] Move to Figure 2E The silicon oxide layer is selectively etched (e.g., using dry etching); in particular, etching is applied only to the exposed portions of the silicon oxide layer to remove it. The remaining portions of the silicon oxide layer (protected by the field plate 160) then define the corresponding separation insulating layer 150.

[0032] Move to Figure 2F A layer of silicon oxide 325 is deposited on wafer 305 to fill gate trench 140 and cover front surface 125f.

[0033] Move to Figure 2G The wafer 305 is planarized (e.g., by chemical mechanical polishing, CMP, step) to remove excess silicon oxide layer 325 on the front surface 125f.

[0034] Move to Figure 2H The silicon oxide layer 325 is etched (e.g., using a dry etching step) to recess downward into the gate trench 140, leaving only the corresponding portion at its bottom with a relatively high thickness (e.g., 100-200 nm).

[0035] Move to Figure 2I Another layer of silicon oxide 330 is grown on wafer 305, namely the front surface 125f, the side surface above the gate trench 140, and a portion of the silicon oxide layer 325 (e.g., by a thermal oxidation step). Specifically, the corresponding portion of the silicon oxide layer 330 coated on the upper part of the gate trench 140 defines a corresponding gate insulating layer 145, while the corresponding portion of the silicon oxide layer 330 added to the portion of the silicon oxide layer 325 in the gate trench 140 (with a slightly increased thickness) defines a corresponding split insulating layer 165. The silicon oxide layer 330 has a relatively low thickness (e.g., 30-50 nm), which in any case is much thinner than the thickness of the split insulating layer 165 (130-250 nm in the example discussed).

[0036] Move to Figure 2JIn the solution according to embodiments of this disclosure, a sacrificial layer of a different material than one in the silicon oxide layer 330, namely the silicon oxide layer 330, is formed on wafer 305, in addition to contributing to the formation of the split insulating layer 165. For example, an auxiliary (electrically) insulating material layer, such as a silicon nitride (Si3N4) layer 335, is deposited. The silicon nitride layer 335 has a (relatively) low thickness (e.g., 70-100 nm). Specifically, the total thickness of the insulating layer formed by the stacked layers of silicon oxide 330 (alone) and silicon nitride layer 335 is (possibly strictly) below the implantation threshold, ensuring that the insulating layers 330, 335 do not substantially prevent any dopant from being implanted through them; conversely, the total thickness of the barrier insulating layer formed by the stacked split insulating layer 165 and silicon nitride layer 335 is above the implantation threshold, ensuring that the barrier insulating layers 165, 335 substantially stop any dopant implantation through them. For example, the implantation threshold is 150-250nm, preferably 180-220nm, more preferably 190-210nm, such as 200nm; the thickness of the insulating layers 330 and 335 is 0.4-0.9 times the implantation threshold, preferably 0.5-0.8 times the implantation threshold, more preferably 0.6-0.7 times the implantation threshold, such as 0.65 times the implantation threshold, while the thickness of the blocking insulating layers 165 and 335 is 1.3-2.5 times the implantation threshold, preferably 1.4-2.0 times the implantation threshold, more preferably 1.5-1.8 times the implantation threshold, such as 1.7 times the implantation threshold.

[0037] Move to Figure 2K Two (ion) implantation steps of a P-type dopant (e.g., boron) are performed consecutively in the region of the trench gate 140 (the remainder of the wafer 305 is appropriately masked). In both cases, the dopant is injected into the wafer 305 along a corresponding implantation direction that is inclined (not perpendicular) to the front surface 125f. In particular, in any plane perpendicular to the axis of the front surface 125f and the trench gate 140 (right side in the figure), the implantation direction is symmetrical to the normal of the front surface 125f; for example, the implantation direction forms an angle relative to the normal that is equal to ±45°-60°, preferably ±47-58°, more preferably ±49-56°, for example ±51-54°. In view of the above, the dopant passes only through the stacked layer of the (thinner) silicon oxide layer 330 and the silicon nitride layer 335, which are blocked by the stacked layer of the (thicker) split insulating layer 165 and the silicon nitride layer 335. As a result, the corresponding region of boron 340 is implanted below the side surface of the front surface 125f and the upper part of the gate trench 140 (and then aligned with the depth of the silicon nitride layer 335).

[0038] Move to Figure 2LA selective etching step is performed to act on the material of the silicon nitride layer but not the material of the silicon oxide layer 330 (e.g., based on phosphoric acid). As a result, the silicon nitride layer is removed without affecting the thickness of the silicon oxide layer 330 (and then the thickness of the gate insulating layer 145 and the split insulating layer 165). An N+ type doped polysilicon layer 345 is (further) deposited on the wafer 305, i.e., on a portion of the silicon oxide layer 330 on the front surface 125f, on the gate insulating layer 145, and on the split insulating layer 165, to fill the (coated) upper portion of the gate trench 140 and cover the (coated) front surface 125f. In view of the above, the doped polysilicon layer 345 is depth-aligned with the boron 340 region (except for the thickness of the removed silicon nitride layer).

[0039] Move to Figure 2M Wafer 305 is planarized (e.g., using chemical mechanical polishing, CMP step) to remove excess doped polysilicon layer on front surface 125f, leaving gate region 155. Boron region is then diffused to obtain body region 130. Given the above, gate region 155 and body region 130 are substantially depth self-aligned (except for the thickness of the removed silicon nitride layer).

[0040] Then, the process continues as usual to obtain... Figure 1 The integrated device 100 is shown. Specifically, the source region 135 is formed by an (ion) implantation step of an N-type dopant (e.g., arsenic) through a photoresist mask (and then stripped), followed by a thermal diffusion step. A relatively thick silicon oxide layer is grown on the wafer by a thermal oxidation step to form a protective layer 175. Corresponding windows of the contacts of the source contacts 180, gate contacts 185, and field plates 160 (not shown) are opened in the protective layer 175 by etching through a photoresist mask and then stripped. A metal (e.g., tungsten) is deposited on the wafer to fill the windows and cover the (coated) front surface 125f, which is then planarized (e.g., using a CMP step) to remove excess metal from the protective layer 175. Another layer of metal (e.g., copper) is deposited on the wafer, etched through a photoresist mask, and then stripped to define the contacts of the source contacts 180, gate contacts 185, and field plates 160. A metal layer (e.g., copper) is deposited on the back surface 125b of the wafer to form the drain contact 170.

[0041] The resulting integrated device 100 (with gate region 155 self-aligned with body region 130 in depth) can be identified because its distinctive features are due to the tilted implantation step. In practice, in this case, body region 130 has a bottom surface within die 110 and a recess between each pair of adjacent trench gates 140, i.e., bent inwards (towards front surface 125f); for example, the distance between its deepest point in die 110 (near trench gate 140) and its shallowest point in die 110 (midway between trench gates 140) is approximately 2-10% of the thickness of body region 130. Alternatively or concurrently, integrated device 100 can be identified by analyzing it using secondary ion mass spectrometry (SIMS); in this way, the typical dopant distribution resulting from the inward tilting movement of die 110 from the front surface 125f and (upper) side surface of trench gate 140 due to the implantation process (i.e., its concentration increasing towards a maximum and then gradually decreasing) can be indicated.

[0042] Now for reference Figure 3 A schematic block diagram of a system 300 including integrated devices according to an embodiment of the present disclosure is shown.

[0043] System 300 (e.g., a control unit for automotive applications) includes multiple components connected via a bus structure 305 (having one or more levels) between them. Specifically, one or more microprocessors (μP) 310 provide the logical capabilities of system 300; non-volatile memory (ROM) 315 stores basic code for booting system 300, and volatile memory (RAM) 320 is used as working memory by microprocessor 310. The system has a large-capacity memory 325 (e.g., flash E2PROM) for storing programs and data. Furthermore, system 300 includes multiple controllers for peripheral devices or input / output (I / O) units 330 (e.g., Wi-Fi-WNIC, Bluetooth transceiver, GPS receiver, accelerometer, gyroscope, etc.). Specifically, one or more of each peripheral device 330 includes an integrated device 100.

[0044] Modifications

[0045] Naturally, those skilled in the art can apply numerous logical and / or physical modifications and alterations to this disclosure to meet local and specific requirements. More specifically, although this disclosure has been described with a degree of particularity with reference to one or more embodiments thereof, it should be understood that various omissions, substitutions, and changes are possible in form, detail, and other embodiments. In particular, different embodiments of this disclosure may even be implemented without the specific details (e.g., numerical values) set forth in the foregoing description to provide a more thorough understanding thereof; conversely, well-known features may be omitted or simplified in order not to obscure the description with unnecessary detail. Furthermore, as a matter of general design choice, it is explicitly intended that specific elements and / or method steps described in connection with any embodiment of this disclosure may be incorporated into any other embodiment. Moreover, items presented in the same group and in different embodiments, examples, or alternatives should not be construed as being substantially equivalent to each other (but are independent, autonomous entities). In any case, each numerical value should be modified according to applicable tolerances; in particular, unless otherwise stated, the terms “substantially,” “approximately,” “roughly,” etc., should be understood to be within the range of 10%, preferably 5%, more preferably 1%. Furthermore, each numerical range should explicitly define any possible numbers on the continuum within that range (including its endpoints). Ordinal numbers or other qualifiers are used only as labels to distinguish elements with the same name, but do not in themselves imply any priority, precedence, or order. Terms including, containing, owning, encompassing, relating to, etc., should have an open, non-exhaustive meaning (i.e., not limited to the stated items), terms based on, dependent on, according to function, etc., should be interpreted as non-exclusive relationships (i.e., potentially involving more variables), the term one / a should refer to one or more items (unless otherwise explicitly stated), and the term "device" (or any device plus a functional description) should refer to any structure adapted or configured to perform the relevant function.

[0046] For example, one embodiment provides a process for manufacturing an integrated device. However, the integrated device can be manufactured using any technology, with different numbers and types of masks, or other process steps / parameters. Furthermore, the above solution can be part of an integrated device design. The design can also be created using a hardware description language; additionally, if the designer does not manufacture the chip or mask, the design can be physically transferred to others.

[0047] In one embodiment, the integrated device includes at least one MOS transistor integrated on a die of a first type of conductive semiconductor material having a main surface. However, the integrated device can be of any type (see below) and integrated on a die of any type (e.g., an epitaxial layer grown on a substrate, a single-crystal substrate, SOI, etc.) and any semiconductor material (e.g., silicon, germanium, etc. with any type and concentration of dopants).

[0048] In one embodiment, the process includes forming one or more gate trenches extending from the main surface to the die. However, the gate trenches can be of any number, shape, size, and depth (e.g., having a U-segment in a UMOS, a V-segment in a VMOS, etc.).

[0049] In one embodiment, the process includes coating a gate trench with an electrically insulating material to obtain a corresponding coated inner portion of the gate trench (coated with a corresponding isolation insulating layer) and a corresponding coated outer portion of the gate trench (coated with a corresponding gate insulating layer). However, the inner / outer portions of the gate trench can have any depth (relative or absolute); furthermore, the isolation / gate insulating layers can be any material (same or different from each other, such as silicon oxide, silicon nitride, tetraethyl orthosilicate, etc.), any thickness (relative or absolute), and they can be formed in any manner (e.g., using one or more growth steps and / or deposition steps, selective or non-selective, using possible etching steps, etc.).

[0050] In one embodiment, the process includes filling the interior of the gate trench with a conductive material forming the corresponding field plate. However, the field plates can be any material (e.g., polysilicon, metal, etc.) and can be formed in any manner (e.g., by deposition, planarization and etching steps, deposition and etching steps, selective deposition steps, etc.).

[0051] In one embodiment, the method includes covering the field plate with a corresponding split insulating layer of an electrically insulating material. However, the split insulating layers can be of any material (same or different from the split / gate insulating layers), of any thickness (same or different from the split insulating layers), and can be formed in any manner (e.g., using a deposition step, a growth step, selectively or immediately following an etching step, etc.).

[0052] In one embodiment, the process includes implanting a dopant of a second type of conductivity from the host surface into the die. However, the dopant can be of any type (e.g., boron, arsenic, etc.) and can be implanted in any manner (e.g., with any energy, length, etc.).

[0053] In one embodiment, the dopant is injected along one or more injection directions that are inclined relative to the front surface. However, the dopant can be injected along any number of injection directions that form any non-zero angle with the front surface.

[0054] In one embodiment, the dopant is selectively implanted by passing through the implantation region (the front and side surfaces outside the gate trench) and being blocked in the blocking region (at the split insulating layer). However, such selective implantation can be achieved in any manner (e.g., with insulating layers of different thicknesses, masks, etc.).

[0055] In one embodiment, the process includes diffusing the implanted dopant to form a bulk region. However, the dopant can be diffused in any manner (e.g., at any temperature, length, etc.).

[0056] In one embodiment, the process includes forming a corresponding gate region by filling the coated outer portion of the gate trench with a conductive material (thus substantially self-aligned in depth from the main surface to the body region). However, the gate regions can be of any material (e.g., the same or different relative to the field plate), and they can be formed in any manner (e.g., by deposition and planarization steps, selective deposition steps, etc.); furthermore, the gate regions and body regions can be self-aligned with any tolerance (e.g., up to 10%, preferably 5%, and more preferably 3%, such as 2%, of the depth of the body region).

[0057] Further embodiments provide additional advantageous features, however these features may be omitted entirely in the basic implementation.

[0058] Specifically, in one embodiment, the process includes implanting dopant along first and second directions in the implantation direction, forming a first angle and a second angle with relative values ​​to the normal of the front surface, respectively. However, the possibility of using more implantation directions is not excluded, even if they are not symmetrical (e.g., adding an implantation direction perpendicular to the front surface).

[0059] In one embodiment, the first angle and the second angle are ±51-54°. However, different angles have been considered.

[0060] In one embodiment, the method includes selectively implanting a dopant by passing through a through insulating layer of an electrically insulating material in a through region and blocking the dopant in a blocking insulating layer of an electrically insulating material in a blocking region, wherein the through insulating layer and the blocking insulating layer are respectively formed having thicknesses below and above an implantation threshold. However, the through / blocking insulating layers can be formed in any manner (e.g., directly through a sacrificial insulating layer, etc.) and they can have any thickness (absolute or relative).

[0061] In one embodiment, the implantation threshold is 200 nm. However, different values ​​of the implantation threshold are expected (e.g., depending on the energy, length, etc. of the implantation step).

[0062] In one embodiment, the method includes forming auxiliary insulating layers of electrically insulating material on an implantation region above a gate insulating layer and a blocking region above a split insulating layer to obtain a through insulating layer and a blocking insulating layer, respectively. However, the auxiliary insulating layer can be of any type (e.g., any material, thickness, etc.) and can be formed in any manner (e.g., deposition, growth, etc.).

[0063] In one embodiment, the process includes removing the auxiliary insulating layer after the implantation of the dopant. However, the auxiliary insulating layer can be removed in any manner (e.g., by a wet etching step, a dry etching step, etc.) until no auxiliary insulating layer remains.

[0064] In one embodiment, the electrical insulating material of the auxiliary insulating layer differs from the electrical insulating materials of the gate insulating layer and the split insulating layer. However, the material can be of any type (even if the two are the same, at least partially the same).

[0065] In one embodiment, the method includes, after implantation of the dopant, selectively etching away an auxiliary insulating layer, selectively etching the electrically insulating material acting on the auxiliary insulating layer but not on the electrically insulating materials of the gate insulating layer and the split insulating layer. However, selective etching can be performed in any manner (e.g., using any selective solution) or in a different manner (e.g., through a corresponding mask).

[0066] In one embodiment, the electrical insulating material of the auxiliary insulating layer is silicon nitride, and the electrical insulating material of the gate insulating layer and the split insulating layer is silicon oxide. However, the use of different materials is also considered.

[0067] Generally, if the same solution is achieved using equivalent methods, similar considerations apply (by using similar steps with the same functionality but with more steps or parts thereof, removing some unnecessary steps or adding more optional steps); furthermore, these steps can be performed in parallel or in an interleaved manner (at least partially).

[0068] One embodiment provides an integrated device including at least one MOS transistor integrated on a die of semiconductor material. However, the integrated device can be of any type (e.g., in raw wafer form, as a bare wafer, in a package, etc.) and includes any number and type of MOS transistors (e.g., power / signal / hybrid NMOS, PMO with cellular / simple structures, etc.).

[0069] In one embodiment, the integrated device is manufactured using the process described above. However, the integrated device can be identified by any number and type of corresponding special features (e.g., the concavity of the body region, its doping profile, etc.).

[0070] One embodiment provides a system including at least one integrated device as described above. However, the same structure can be integrated with other circuitry on the same chip; the chip can also be coupled to one or more other chips, can be mounted in an intermediate product, or can be used in a complex device. In any case, the resulting system can be of any type (e.g., for automotive applications, smartphones, computers, etc.), and can include any number of these integrated devices.

[0071] Generally, similar considerations apply if integrated devices and systems each have different structures or contain equivalent components (e.g., different materials) or have other operational characteristics. In any case, each component may be separated into multiple elements, or two or more components may be combined into a single element; furthermore, each component may be replicated to support the parallel execution of corresponding operations. Moreover, unless otherwise specified, any interaction between different components generally does not need to be sequential and may be direct or indirect through one or more intermediaries.

[0072] A process for manufacturing an integrated device (100) can be summarized as including at least one MOS transistor (105) integrated on a die (110) of a semiconductor material having a first type of conductivity on a main surface (125f), wherein the process includes forming one or more gate trenches (140) extending from the main surface (125f) into the die (110), coating the gate trenches (140) with an electrically insulating material to obtain a corresponding coated inner portion of the gate trenches (140), the gate trenches (140) being coated with a corresponding separating insulating layer (150) and the corresponding coated outer portion of the gate trenches (140) being coated with a corresponding gate insulating layer (145), and filling with a conductive material forming a corresponding field plate (160). Inside the coated gate trench (140), a corresponding split insulating layer (165) of electrically insulating material covers the field plate (160). A dopant of second type conductivity is injected into the die (110) from the main surface (125f) along one or more injection directions inclined relative to the front surface (125f). The dopant is selectively injected by passing through the injection region of the front surface (125f) and the side surface outside the gate trench (140) and blocked in the blocking region at the split insulating layer (165). The injected dopant diffuses to form the body region (130) and fills the coated external conductive material of the gate trench (140) to form the corresponding gate region (155), thereby substantially self-aligning in depth from the main surface (125f) and the body region (130).

[0073] The process may include implanting dopants along first and second directions in the implantation direction to form a first angle and a second angle having a relative value to the normal of the front surface (125f), respectively.

[0074] The first and second angles can be ±51-54°.

[0075] The process may include selectively implanting dopants by passing through an electrically insulating layer (145, 335) in a passing region and being blocked by a blocking insulating layer (160, 335) in a blocking region, wherein the passing insulating layer and the blocking insulating layer have thicknesses below and above the implantation threshold, respectively.

[0076] The injection threshold can be 200nm.

[0077] The process may include forming an auxiliary insulating layer (335) of electrically insulating material on an implantation region above a gate insulating layer (145) and a blocking region above a split insulating layer (165) to obtain through insulating layers (145, 335) and blocking insulating layers (160, 335) respectively, and removing the auxiliary insulating layer (335) after the dopant is implanted.

[0078] The electrical insulating material of the auxiliary insulating layer (335) may be different from the electrical insulating materials of the gate insulating layer (145) and the split insulating layer (165). The process may include removing the auxiliary insulating layer (335) by selectively etching the electrical insulating material of the auxiliary insulating layer (335) without affecting the gate insulating layer (145) and the split insulating layer (165) after implanting dopant.

[0079] The electrical insulating material of the auxiliary insulating layer (335) can be silicon nitride, and the electrical insulating material of the gate insulating layer (145) and the split insulating layer (165) can be silicon oxide.

[0080] The integrated device (100) can be summarized as including at least one MOS transistor (105) integrated on a die (110) of semiconductor material, the integrated device (100) being manufactured by the process.

[0081] The system (300) can be summarized as including at least one integrated device (100). Various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A process for manufacturing an integrated device, the integrated device comprising at least one MOS transistor, the at least one MOS transistor being integrated on a die of a semiconductor material having a first type of conductivity on a main surface, the process comprising: Form one or more gate trenches extending from the main surface into the die; The gate trench is coated with an electrically insulating material to obtain a corresponding coated inner portion of the gate trench coated with a corresponding separating insulating layer and a corresponding coated outer portion of the gate trench coated with a corresponding gate insulating layer. The coated interior portion of the gate trench is filled with a conductive material that forms the corresponding field plate; The field plate is covered with a corresponding split insulating layer of electrical insulating material; A dopant of a second type of conductivity is implanted from the main surface into the die along one or more implantation directions inclined relative to the main surface. The dopant is selectively implanted by passing through implantation regions at the front and side surfaces of the outer portion of the gate trench and being blocked in the blocking regions at the split insulating layer. The injected dopant diffuses to form the bulk region; as well as A corresponding gate region is formed by filling the coated outer portion of the gate trench with a conductive material, such that the corresponding gate region is substantially self-aligned in depth with the body region from the main surface; The dopants implanted with the second type of conductivity include: Dopant is selectively implanted by passing through a through insulating layer of electrically insulating material in the through region and being blocked by a blocking insulating layer of electrically insulating material in the blocking region, wherein the thicknesses of the through insulating layer and the blocking insulating layer are below and above an implantation threshold, respectively. The process further includes: An auxiliary insulating layer of electrically insulating material is formed on the injection region above the gate insulating layer and the blocking region above the split insulating layer to obtain the through insulating layer and the blocking insulating layer, respectively; and After the dopant is implanted, the auxiliary insulating layer is removed.

2. The process of claim 1, wherein the dopant implanted with the second type of conductivity comprises: Dopant is injected along a first direction and a second direction in the injection direction, thereby forming a first angle and a second angle with relative values ​​with the normal of the main surface, respectively.

3. The process according to claim 2, wherein the first angle and the second angle are in the range of ±51° to ±54°.

4. The process according to claim 1, wherein the implantation threshold is 200 nm.

5. The process according to claim 1, wherein the electrical insulating material of the auxiliary insulating layer is different from the electrical insulating materials of the gate insulating layer and the split insulating layer, the process comprising: After the dopant is implanted, the auxiliary insulating layer is removed by selective etching of the electrically insulating material acting on the auxiliary insulating layer but not on the electrically insulating material acting on the gate insulating layer and the split insulating layer.

6. The process according to claim 5, wherein the electrical insulating material of the auxiliary insulating layer is silicon nitride, and the electrical insulating materials of the gate insulating layer and the split insulating layer are silicon oxide.

7. An integrated device comprising at least one MOS transistor integrated on a die of semiconductor material, said integrated device being manufactured by the process of claim 1.

8. An electronic system comprising at least one integrated device according to claim 7.

9. A method for manufacturing a device, comprising: A gate trench is formed extending from a first surface into a semiconductor die, the semiconductor die having a first type of conductivity; A separation insulating layer is formed on the wall of the semiconductor die in the trench, the separation insulating layer having an upper surface spaced apart from the first surface of the semiconductor die; A field plate is formed by forming a doped polysilicon layer in the trench and laterally forming a doped polysilicon layer between the sidewalls of the separating insulating layer in the trench, the field plate having an upper surface substantially coplanar with the upper surface of the separating insulating layer; A split insulating layer of electrically insulating material is formed on the field plate; A body region is formed by injecting a dopant of a second type of conductivity into the semiconductor die from the first surface along one or more injection directions inclined relative to the first surface. The dopant is selectively injected by passing through the injection region at the first surface and side surface of the outer portion of the gate trench and being blocked in the blocking region of the split insulating layer. as well as A gate region is formed by filling the gate trench with a conductive material that extends from the upper surface of the split insulating layer to a level above the first surface, and the gate region is substantially self-aligned in depth with the body region from the main surface. The dopants implanted with the second type of conductivity include: Dopant is selectively implanted by passing through an insulating layer of electrically insulating material in the passage region and being blocked by a blocking insulating layer of electrically insulating material in the blocking region, wherein the thicknesses of the passing insulating layer and the blocking insulating layer are below and above the implantation threshold, respectively. The method further includes: Auxiliary insulating layers of electrically insulating material are formed on the injection region above the gate insulating layer and the blocking region above the split insulating layer, respectively, to obtain the through insulating layer and the blocking insulating layer; and The auxiliary insulating layer is removed after the dopant is injected.

10. The method of claim 9, wherein forming the split insulating layer comprises forming a first dielectric layer on the upper surface of the split insulating layer in the trench and the field plate.

11. The method of claim 10, further comprising forming a gate insulating layer by forming a second dielectric layer on the wall of the semiconductor die between the upper surface of the separated insulating layer and the first surface.

12. The method of claim 11, wherein forming the split insulating layer comprises forming the second dielectric layer on the first dielectric layer covering the upper surface of the field plate in the trench.

13. The method of claim 12, wherein the electrical insulating material of the auxiliary insulating layer is different from the material of the second dielectric layer of the gate insulating layer and the first dielectric layer of the split insulating layer, the method comprising: The auxiliary insulating layer is removed after the dopant is implanted by selective etching of the electrically insulating material acting on the auxiliary insulating layer.

14. The method of claim 13, wherein the electrical insulating material of the auxiliary insulating layer is silicon nitride, and the first dielectric layer and the second dielectric layer are silicon oxide layers.

15. The method of claim 9, wherein the dopant implanted with the second type of conductivity comprises: The dopant is injected along a first direction and a second direction in the injection direction, forming a first angle and a second angle with relative values ​​with the normal of the first surface, respectively.

16. The method of claim 15, wherein the first angle and the second angle are in the range of ±51° to ±54°.

Images