Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a gate structure, which is separated on the substrate in a device cell region, and is located at an edge of the device cell region and close to a junction of the device cell region and an isolation region, and is as an edge gate structure; an extension direction of the gate structure is a longitudinal direction, and a direction parallel to the substrate and perpendicular to the longitudinal direction is a lateral direction; a source-drain doped region, which is located in the substrate of the device cell region on both sides of the gate structure; an isolation structure, which is located between adjacent edge gate structures and in a partial thickness of the substrate of the isolation region; and a residual source-drain doped region, which is located between a side wall of the isolation structure and the substrate in the lateral direction. In the embodiment of the present application, the residual source-drain doped region is arranged to improve the layout consistency of the periphery of the edge gate structure and the periphery of other gate structures, thereby improving the layout-dependent effect, reducing the influence of the isolation structure on the performance of the surrounding devices, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.

[0003] To better adapt to the shrinking feature size, semiconductor processes are gradually transitioning from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate can control the ultrathin body (fin) from at least both sides. Compared to planar MOSFETs, the gate has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.

[0004] However, as the size of semiconductor devices continues to shrink, the distance between adjacent fin field-effect transistors also decreases. To prevent bridging between adjacent devices, the fabrication technology of doublediffusion break isolation structures (DDB isolation structures) has been introduced.

[0005] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improve the layout dependent effects (LDE) and reduce the impact of the isolation structure on the performance of devices around the isolation structure, thereby improving the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including discrete device cell regions and isolation regions located between the device cell regions; a gate structure discretely located on the substrate of the device cell regions, wherein the gate structure located at the edge of the device cell regions and near the boundary between the device cell regions and the isolation regions is an edge gate structure; the extending direction of the gate structure is longitudinal, and the direction parallel to the substrate and perpendicular to the longitudinal direction is transverse; source / drain doped regions located in the substrate of the device cell regions on both sides of the gate structure; an isolation structure located between adjacent edge gate structures and in a portion of the thickness of the isolation region in the substrate; and residual source / drain doped regions located transversely between the sidewall of the isolation structure and the substrate.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including discrete device cell regions and isolation regions located between the device cell regions; discrete gate structures formed on the substrate of the device cell regions; a gate structure located at the edge of the device cell regions and near the junction of the device cell regions and the isolation regions serving as an edge gate structure; the extension direction of the gate structure being longitudinal, and a direction parallel to the substrate and perpendicular to the longitudinal direction being transverse; source / drain doped regions formed in the substrate on both sides of the gate structure; an interlayer dielectric layer formed on the substrate on the side of the gate structure, covering the source / drain doped regions; forming an isolation trench penetrating the interlayer dielectric layer and the source / drain doped regions through the isolation regions; the isolation trench being located between adjacent edge gate structures, and a portion of the source / drain doped regions being retained along the sidewalls on both sides of the transverse isolation trench for use as residual source / drain doped regions; and forming an isolation structure in the isolation trench.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure provided by this embodiment of the invention, the isolation structure is located between adjacent edge gate structures and penetrates a portion of the thickness of the substrate of the isolation region. The semiconductor structure also includes a residual source / drain doped region located between the sidewall of the isolation structure and the substrate. Therefore, not only is the source / drain doped region provided between the edge gate structure and the substrate of the device cell region, but the residual source / drain doped region is also provided between the edge gate structure and the substrate of the isolation region. Thus, the provision of the residual source / drain doped region helps to improve the layout consistency of the periphery of the edge gate structure with the periphery of other gate structures, thereby helping to improve the layout dependent effects (LDE) and reduce the impact of the isolation structure on the performance of its surrounding devices, thereby improving the performance of the semiconductor structure.

[0011] In the semiconductor structure formation method provided in this embodiment of the invention, during the formation of the isolation trench, a portion of the source / drain doped region is retained along the sidewalls on both sides of the transverse isolation trench as a residual source / drain doped region. Therefore, not only is the source / drain doped region provided between the edge gate structure and the substrate of the device cell region, but the residual source / drain doped region is also provided between the edge gate structure and the substrate of the isolation region. Thus, the residual source / drain doped region helps to improve the layout consistency of the periphery of the edge gate structure with the periphery of other gate structures, thereby helping to improve the layout dependency effect and reduce the impact on the performance of devices around the isolation structure, thus improving the performance of the semiconductor structure. Attached Figure Description

[0012] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] Figures 5 to 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As the background technology shows, the performance of current semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example.

[0016] refer to Figures 1 to 4 The diagram shows a schematic diagram of each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 A substrate 10 is provided, including discrete device cell regions i and isolation regions ii located between the device cell regions i.

[0018] Continue to refer to Figure 1 A gate structure 11 is formed on the substrate 10 of the device cell region i. The gate structure 11 located at the edge of the device cell region i and close to the junction of the device cell region i and the isolation region ii is called the edge gate structure 11(a).

[0019] Continue to refer to Figure 1 Source and drain doped regions 12 are formed in the substrate 10 on both sides of the gate structure 11.

[0020] refer to Figure 2 An interlayer dielectric layer 13 is formed on the substrate 10 on the side of the gate structure 11, covering the source and drain doped regions 12.

[0021] refer to Figure 3 The interlayer dielectric layer 13 located between the edge gate structures 11(a), the source and drain doped regions 12 of the isolation region ii, and a portion of the thickness substrate 10 are removed to form an isolation trench 14.

[0022] refer to Figure 4 An isolation structure 15 is formed in the partition groove 14.

[0023] In the above-described forming method, the formed isolation structure 15 is used to isolate adjacent device cell regions i. Specifically, the isolation structure 15 is a double diffusion barrier (DDB) isolation structure, used to prevent bridging between adjacent device cell regions i.

[0024] However, the arrangement of the isolation structure 15 has a significant impact on the surrounding devices. Specifically, during the formation of the isolation trench 14, the method removes all the source / drain doped regions 12 of the isolation region ii, resulting in the edge gate structure 11(a) having source / drain doped regions 12 on only one side and none on the other. This reduces the layout consistency between the periphery of the edge gate structure 11(a) and the periphery of other gate structures 11. Based on the layout-dependent effects (LDE), this has a significant impact on the performance of the devices surrounding the isolation structure 15, such as affecting the threshold voltage Vt and saturation current I of the surrounding devices. dsat And so on, which can easily reduce the performance of the semiconductor structure.

[0025] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including discrete device cell regions and isolation regions located between the device cell regions; a gate structure discretely located on the substrate of the device cell regions, wherein the gate structure located at the edge of the device cell regions and near the boundary between the device cell regions and the isolation regions is an edge gate structure; the extending direction of the gate structure is longitudinal, and the direction parallel to the substrate and perpendicular to the longitudinal direction is transverse; source / drain doped regions located in the substrate of the device cell regions on both sides of the gate structure; an isolation structure located between adjacent edge gate structures and in a portion of the thickness of the isolation region in the substrate; and residual source / drain doped regions located transversely between the sidewall of the isolation structure and the substrate.

[0026] In the semiconductor structure provided in this embodiment of the invention, a residual source / drain doped region is also provided, located between the sidewall of the isolation structure and the substrate. Therefore, not only is the source / drain doped region provided between the edge gate structure and the substrate of the device cell region, but the residual source / drain doped region is also provided between the edge gate structure and the substrate of the isolation region. Thus, the provision of the residual source / drain doped region is beneficial to improving the layout consistency of the periphery of the edge gate structure and the periphery of other gate structures, thereby improving the layout dependent effects (LDE) and reducing the impact of the isolation structure on the performance of devices around the isolation structure, thereby improving the performance of the semiconductor structure.

[0027] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] refer to Figures 5 to 6 , Figure 5 It is a 3D image. Figure 6 for Figure 5 A cross-sectional view along the AA direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0029] like Figure 5 and Figure 6 As shown, in this embodiment, the semiconductor structure includes: a substrate (not shown), including discrete device cell regions I and an isolation region II located between the device cell regions I; a gate structure 120, discretely located on the substrate of the device cell regions I, with the gate structure 120 located at the edge of the device cell regions I and near the junction of the device cell regions I and the isolation region II serving as an edge gate structure 120(a); the extending direction of the gate structure 120 is longitudinal (e.g., Figure 5 As shown in the y-direction), the direction parallel to the base and perpendicular to the longitudinal direction is the transverse direction (e.g., as shown in the y-direction). Figure 5 (shown in the x-direction); source / drain doped regions 140, located in the substrate of the device cell region I on both sides of the gate structure 120; isolation structure 200, located between adjacent edge gate structures 120(a) and in a portion of the thickness of the isolation region II in the substrate; residual source / drain doped regions 300, located in the lateral direction between the sidewall of the isolation structure 200 and the substrate.

[0030] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0031] In this embodiment, the substrate is used to form a FinFET. Accordingly, the substrate is a three-dimensional substrate, comprising a substrate (not shown) and a fin 110 protruding from the substrate. In the FinFET, the gate structure 120 spans the fin 110 and covers part of the top and sidewalls of the fin 110. The gate structure 120 can control the fin 110 from three sides, thereby improving the gate structure 120's control over the channel, which in turn helps to suppress short-channel effects and improve device performance.

[0032] In this embodiment, the substrate is a silicon substrate, and the fin 110 is made of the same material as the substrate. However, the materials of the substrate and the fin 110 are not limited to this; they can also be other suitable materials.

[0033] In other embodiments, the substrate may also be other types of three-dimensional substrates. For example, when forming a gate-all-around (GAA) transistor, the substrate includes a substrate and a channel structure layer spaced apart from the substrate, the channel structure layer including one or more spaced-apart channel layers, and a gate structure correspondingly surrounding the channel layer. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is a planar substrate.

[0034] The device unit region I is used to form a device. In this embodiment, a plurality of device unit regions I are arranged along the lateral spacing, and the region located between adjacent device unit regions I is the isolation region II, which is used to achieve isolation between adjacent device unit regions I.

[0035] In this embodiment, the semiconductor structure further includes an isolation layer 115 located on the substrate exposed by the fin 110. The isolation layer 115 covers part of the sidewall of the fin 110, and the top surface of the isolation layer 115 is lower than the top surface of the fin 110.

[0036] In this embodiment, the isolation layer 115 is a shallow trench isolation (STI) structure, used to isolate adjacent fins 110, and also to isolate the substrate from the gate structure 120.

[0037] In this embodiment, the material of the insulating layer 115 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0038] When the device is in operation, the gate structure 120 is used to turn the conductive channel on and off.

[0039] In this embodiment, the gate structure 120 is located on the isolation layer 115, and the gate structure 120 spans the fin 110 and covers part of the top and part of the sidewall of the fin 110.

[0040] In this embodiment, the gate structure 120 is a metal gate structure.

[0041] Accordingly, in this embodiment, the gate structure 120 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0042] In this embodiment, the high-k gate dielectric layer is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of HfO2. In other embodiments, the high-k gate dielectric layer may also be made of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0043] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0044] The gate electrode layer serves as an electrode to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and the external circuit.

[0045] In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0046] In other embodiments, the gate structure may also be a polysilicon gate structure. The polysilicon gate structure correspondingly includes a gate oxide layer and a polysilicon gate layer located on the gate oxide layer. The material of the gate oxide layer includes silicon oxide or silicon oxynitride.

[0047] In other embodiments, the semiconductor structure may further include a gate cap layer located on top of the gate structure, the gate cap layer serving to protect the top of the gate structure. Specifically, during the formation of the isolation structure, the gate cap layer is located on top of the gate structure to prevent damage to the top of the gate structure.

[0048] In this embodiment, the semiconductor structure further includes a gate sidewall 130, located on the sidewall of the gate structure 120.

[0049] The gate sidewall 130 is used to protect the sidewall of the gate structure 120, and the gate sidewall 130 is also used to define the formation location of the source and drain doped regions 140.

[0050] The gate sidewall 130 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 130 can be a single-layer structure or a multilayer structure. In this embodiment, the gate sidewall 130 is a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

[0051] When the device is in operation, the source / drain doped regions 140 are used to provide carrier sources.

[0052] In this embodiment, the source / drain doped region 140 includes a stress layer doped with ions, and the source / drain doped region 140 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0053] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 140 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0054] When forming a PMOS transistor, the source and drain doped regions 140 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0055] In other embodiments, depending on the actual process, the material of the source / drain doped region can also be an ion-doped substrate, and the source / drain doped region is formed by ion doping the substrate accordingly.

[0056] In this embodiment, the source / drain doped region 140 is located in the fin 110 of the device cell region I on both sides of the gate structure 120.

[0057] The isolation structure 200 is used to achieve isolation between adjacent device unit regions I.

[0058] In this embodiment, the isolation structure 200 is a double diffusion break (DDB) isolation structure. The isolation structure 200 is located between adjacent edge gate structures 120(a) to achieve electrical isolation between adjacent edge gate structures 120(a) and prevent bridging between the edge gate structures 120(a) of adjacent device cell regions I.

[0059] Specifically, in this embodiment, the isolation structure 200 is located between adjacent edge gate structures 120(a) and in the fin 110 of the isolation region II.

[0060] Therefore, the material of the isolation structure 200 is a dielectric material, which gives the isolation structure 200 insulating properties and prevents bridging between adjacent devices.

[0061] Specifically, the material of the isolation structure 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and boron silicon carbide. The isolation structure 200 can be a single-layer or multi-layer structure. In this embodiment, the isolation structure 200 is a single-layer structure, and the material of the isolation structure 200 is silicon oxide. Silicon oxide is an easily obtainable insulating material, which helps to reduce the cost of the isolation structure 200 and improve process compatibility. Furthermore, silicon oxide has a low dielectric constant, which helps to improve the isolation effect of the isolation structure 200 on adjacent devices.

[0062] Along the lateral direction, the width of the isolation structure 200 should not be too small or too large. If the width of the isolation structure 200 is too small, it is easy to reduce the isolation effect of the isolation structure 200 on adjacent devices; if the width of the isolation structure 200 is too large, it is easy to cause the width of the residual source / drain doped region 300 to be too small, which in turn is easy to reduce the improvement effect of the residual source / drain doped region 300 on the layout dependency effect (LDE). Therefore, in this embodiment, along the lateral direction, the width of the isolation structure 200 is 50% to 90% of the width of the source / drain doped region 140.

[0063] In this embodiment, the bottom surface of the isolation structure 200 is lower than the bottom surface of the residual source / drain doped region 300, thereby reducing the probability of leakage current being generated between the residual source / drain doped regions 300, which is beneficial to further improve the isolation effect of the isolation structure 200 on the adjacent device unit region I.

[0064] Along the direction of the normal to the substrate surface (e.g.) Figure 5 As shown in the z-direction, compared to the bottom surface of the residual source / drain doped region 300, the bottom surface of the isolation structure 200 should not be too low; otherwise, the aspect ratio of the isolation structure 200 will be too large, easily increasing the difficulty of forming the isolation structure 200 and reducing process compatibility. Therefore, in this embodiment, along the normal direction of the substrate surface, the bottom surface of the isolation structure 200 is 5 nm to 30 nm lower than the bottom surface of the residual source / drain doped region 300.

[0065] The residual source / drain doped region 300 is used to improve the layout consistency of the periphery of the edge gate structure 120(a) with the periphery of other gate structures 120, thereby improving the layout dependent effects (LDE), reducing the impact of the isolation structure 200 on the device performance around the isolation structure 200, and improving the performance of the semiconductor structure.

[0066] Specifically, in this embodiment, the residual source / drain doped region 300 is located between the sidewall of the isolation structure 200 and the fin 110.

[0067] In this embodiment, the residual source / drain doped region 300 is obtained by etching the source / drain doped region 140 located in isolation region II. Therefore, the material of the residual source / drain doped region 300 is the same as the material of the source / drain doped region 140, which is beneficial to improving the effect of the residual source / drain doped region 300 on the layout dependence effect.

[0068] Accordingly, in this embodiment, the residual source / drain doped region 300 also includes a stress layer doped with ions. By including the stress layer doped with ions in the residual source / drain doped region 300, a portion of the stress layer remains between the edge gate structures 120(a), ensuring that stress does not directly cause failure, thereby improving the performance of the device.

[0069] In other embodiments, depending on the actual process, when the material of the source / drain doped region can be an ion-doped substrate, and the source / drain doped region is formed by ion doping of the substrate, the material of the residual source / drain doped region is also an ion-doped substrate.

[0070] In this embodiment, during the formation of the semiconductor structure, an isolation structure 200 is formed that extends through the source / drain doped region 140 of the isolation region II. The remaining source / drain doped region 140 located on the sidewall of the isolation structure 200 is then used as the residual source / drain doped region 300. As described above, the width of the isolation structure 200 along the lateral direction is 50% to 90% of the width of the source / drain doped region 140. Therefore, in this embodiment, the width of the residual source / drain doped region 300 located on one sidewall of the isolation structure 200 along the lateral direction is 5% to 25% of the width of the source / drain doped region 140.

[0071] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 150, located on the substrate on the side of the gate structure 120 and covering the source / drain doped regions 140. In this embodiment, the interlayer dielectric layer 150 is located on the isolation layer 115.

[0072] The interlayer dielectric layer 150 is used to isolate adjacent devices.

[0073] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0074] Accordingly, in this embodiment, the isolation structure 200 is located in the interlayer dielectric layer 150 and the substrate of the isolation region II.

[0075] It should be noted that, in this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 150 and the isolation layer 115 are shown in the cross-sectional view.

[0076] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0077] refer to Figure 7 and Figure 8 , Figure 7 It is a 3D image. Figure 8 for Figure 7 A cross-sectional view along the AA direction provides a substrate including discrete device cell regions I and isolation regions II located between the device cell regions I. Discrete gate structures 120 are formed on the substrate of the device cell regions I. The gate structure 120 located at the edge of the device cell region I and near the junction of the device cell region I and the isolation region II is designated as an edge gate structure 120(a). The extending direction of the gate structure 120 is longitudinal (e.g., ...). Figure 7As shown in the y-direction), the direction parallel to the base and perpendicular to the longitudinal direction is the transverse direction (e.g., as shown in the y-direction). Figure 7 (As shown in the x-direction), active and drain doped regions 140 are formed in the substrates on both sides of the gate structure 120, and an interlayer dielectric layer 150 is formed on the substrate on the side of the gate structure 120, covering the active and drain doped regions 140.

[0078] The substrate is used to provide a process platform for subsequent process manufacturing.

[0079] In this embodiment, the substrate is used to form a FinFET. Accordingly, the substrate is a three-dimensional substrate, comprising a substrate (not shown) and a fin 110 protruding from the substrate. In the FinFET, the gate structure 120 spans the fin 110 and covers a portion of the top and sidewalls of the fin 110. The gate structure 120 can control the fin 110 from three sides, thereby improving the gate structure 120's control over the channel, which in turn helps suppress short-channel effects and improve device performance.

[0080] In this embodiment, the substrate is a silicon substrate, and the fin 110 is made of the same material as the substrate. However, the materials of the substrate and the fin 110 are not limited to this; they can also be other suitable materials.

[0081] In other embodiments, the substrate may also be other types of three-dimensional substrates. For example, when forming a gate-all-around (GAA) transistor, the substrate correspondingly includes a substrate and a channel structure layer disposed on and spaced apart from the substrate, the channel structure layer including one or more spaced-apart channel layers, and the gate structure correspondingly surrounding the channel layer. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is a planar substrate.

[0082] The device unit region I is used to form a device. In this embodiment, a plurality of device unit regions I are arranged along the lateral spacing, and the region located between adjacent device unit regions I is the isolation region II, which is used to achieve isolation between adjacent device unit regions I.

[0083] In this embodiment, an isolation layer 115 is also formed on the substrate exposed by the fin 110. The isolation layer 115 covers part of the sidewall of the fin 110, and the top surface of the isolation layer 115 is lower than the top surface of the fin 110.

[0084] In this embodiment, the isolation layer 115 is a shallow trench isolation (STI) structure, used to isolate adjacent fins 110, and also to isolate the substrate from the gate structure 120.

[0085] In this embodiment, the material of the insulating layer 115 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0086] In this embodiment, the gate structure 120 is a device gate structure. When the device is working, the gate structure 120 is used to turn on and off the conductive channel.

[0087] In this embodiment, the gate structure 120 is located on the isolation layer 115, and the gate structure 120 spans the fin 110 and covers part of the top and part of the sidewall of the fin 110.

[0088] In this embodiment, the gate structure 120 is a metal gate structure.

[0089] Accordingly, in this embodiment, the gate structure 120 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer located on the work function layer.

[0090] In this embodiment, the high-k gate dielectric layer is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of HfO2. In other embodiments, the high-k gate dielectric layer may also be made of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0091] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0092] The gate electrode layer serves as an electrode to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and the external circuit.

[0093] In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0094] In other embodiments, during the step of providing the substrate, the gate structure may also be a sacrificial gate structure. The sacrificial gate structure occupies space for forming a device gate structure. Specifically, the sacrificial gate structure may be a polysilicon gate structure, comprising a gate oxide layer and a polysilicon gate layer located on the gate oxide layer.

[0095] In other embodiments, a gate cap layer may also be formed on top of the gate structure to protect the top of the gate structure. Specifically, during the subsequent formation of the isolation trench and isolation structure, the gate cap layer is located on top of the gate structure to prevent damage to the top of the gate structure.

[0096] In this embodiment, a gate sidewall 130 is also formed on the sidewall of the gate structure 120.

[0097] The gate sidewall 130 is used to protect the sidewall of the gate structure 120, and the gate sidewall 130 is also used to define the formation location of the source and drain doped regions 140.

[0098] The gate sidewall 130 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 130 can be a single-layer structure or a multilayer structure. In this embodiment, the gate sidewall 130 is a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

[0099] When the device is in operation, the source / drain doped regions 140 are used to provide carrier sources.

[0100] In this embodiment, the source / drain doped region 140 includes a stress layer doped with ions, and the source / drain doped region 140 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0101] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 140 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0102] When forming a PMOS transistor, the source and drain doped regions 140 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0103] In other embodiments, depending on the actual process, the material of the source / drain doped region can also be an ion-doped substrate, and the source / drain doped region is formed by ion doping the substrate accordingly.

[0104] In this embodiment, the source / drain doped regions 140 are located in the fins 110 on both sides of the gate structure 120.

[0105] The interlayer dielectric layer 150 serves to isolate adjacent devices. In this embodiment, the interlayer dielectric layer 150 is formed on the isolation layer 115.

[0106] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0107] In this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 150 and the isolation layer 115 are shown in the cross-sectional view.

[0108] As an example, the steps of providing a substrate, a gate structure 110, source / drain doped regions 140, and an interlayer dielectric layer 150 may include: providing a substrate; forming a discrete dummy gate structure (not shown) on the substrate of the device cell region I; forming a gate sidewall 130 on the sidewall of the dummy gate structure; forming source / drain doped regions 140 in the substrate on both sides of the dummy gate structure; forming an interlayer dielectric layer 150 covering the source / drain doped regions 140 on the substrate on the side of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer 150; and forming the gate structure 110 in the gate opening.

[0109] refer to Figures 9 to 11 An isolation trench 180 is formed, which penetrates the interlayer dielectric layer 150 and the source / drain doped region 140 of the isolation region II (e.g., Figure 11 As shown), the isolation trench 180 is located between adjacent edge gate structures 120(a), and a portion of the source / drain doped region 140 is retained on the sidewalls of both sides of the transverse isolation trench 180 for use as a residual source / drain doped region 300.

[0110] The partition groove 180 is used to provide space for forming the isolation structure.

[0111] In this embodiment, during the formation of the isolation trench 180, a portion of the source / drain doped region 140 is retained on the sidewalls of both sides of the transverse isolation trench 180 as a residual source / drain doped region 300. Therefore, not only is the source / drain doped region 140 provided between the edge gate structure 120(a) and the substrate of the device cell region I, but the residual source / drain doped region 300 is also provided between the edge gate structure 120(a) and the substrate of the isolation region II. Thus, the residual source / drain doped region 300 helps to improve the layout consistency of the periphery of the edge gate structure 120(a) with the periphery of other gate structures 120, thereby helping to improve the layout dependent effects (LDE) and reduce the impact on the performance of devices around the isolation trench 180, thus improving the performance of the semiconductor structure.

[0112] In this embodiment, during the step of forming the isolation trench 180, the isolation trench 180 is located in the interlayer dielectric layer 150 between adjacent edge gate structures 120(a) and penetrates the source / drain doped regions 140 of the isolation region II.

[0113] In this embodiment, during the step of forming the isolation trench 180, the isolation trench 180 also penetrates a portion of the thickness of the substrate at the bottom of the source / drain doped region 140. Specifically, in this embodiment, the isolation trench 180 also penetrates a portion of the thickness of the fin 110 at the bottom of the source / drain doped region 140.

[0114] Therefore, in this embodiment, the bottom surface of the isolation trench 180 is lower than the bottom surface of the residual source / drain doped region 300, thereby reducing the probability of leakage current being generated between the residual source / drain doped regions 300, which is beneficial to further improve the isolation effect of the subsequent isolation structure between adjacent device unit regions I.

[0115] Along the direction of the surface normal of the substrate 100 (e.g.) Figure 7 As shown in the z-direction, compared to the bottom surface of the source / drain doped region 140, the bottom surface of the isolation trench 180 should not be too low; otherwise, the aspect ratio of the isolation trench 180 will be too large, which will easily increase the difficulty of forming the isolation structure in the isolation trench 180 and reduce process compatibility. Therefore, in this embodiment, in the step of forming the isolation trench 180, along the direction of the normal to the substrate surface, the bottom surface of the isolation trench 180 is 5nm to 30nm lower than the bottom surface of the source / drain doped region 140.

[0116] Along the lateral direction, the width of the isolation trench 180 should not be too small or too large. If the width of the isolation trench 180 is too small, the lateral width of the isolation structure will be too small after the isolation structure is formed in the isolation trench 180, which may reduce the isolation effect of the isolation structure on adjacent devices. If the width of the isolation trench 180 is too large, the width of the residual source / drain doped region 300 may be too small, which may reduce the improvement effect of the residual source / drain doped region 300 on the layout dependency effect (LDE). Therefore, in this embodiment, along the lateral direction, the width of the isolation trench 180 is 50% to 90% of the width of the source / drain doped region 140.

[0117] Accordingly, in this embodiment, along the lateral direction, the width of the residual source / drain doped region 300 located on one side wall of the isolation structure 200 is 5% to 25% of the width of the source / drain doped region 140.

[0118] In this embodiment, the residual source / drain doped region 300 is obtained by etching the source / drain doped region 140 located in isolation region II. Therefore, the material of the residual source / drain doped region 300 is the same as the material of the source / drain doped region 140, which is beneficial to improving the effect of the residual source / drain doped region 300 on the layout dependence effect.

[0119] In this embodiment, the residual source / drain doped region 300 also includes a stress layer doped with ions. By including the stress layer doped with ions in the residual source / drain doped region 300, a portion of the stress layer remains between the edge gate structures 120(a), ensuring that stress does not directly cause failure, thereby improving the performance of the device.

[0120] In other embodiments, depending on the actual process, when the material of the source / drain doped region can be an ion-doped substrate, and the source / drain doped region is formed by ion doping of the substrate, the material of the residual source / drain doped region is also an ion-doped substrate.

[0121] In this embodiment, the step of forming the partition groove 180 includes:

[0122] like Figure 9 As shown, a hard mask layer 160 is formed on the interlayer dielectric layer 150 and the gate structure 120, and a mask opening 170 is formed in the hard mask layer 160 above the isolation region II.

[0123] The hard mask layer 160 is used as an etching mask for forming the isolation trench.

[0124] The hard mask layer 160 is selected from materials that have etching selectivity with the interlayer dielectric layer 150 and the source / drain doped region 140, so as to ensure the effectiveness of the hard mask layer 160 as an etching mask.

[0125] In this embodiment, the material of the hard mask layer 160 is silicon nitride.

[0126] The mask opening 170 is used to define the formation location and size of the partition trench.

[0127] In this embodiment, during the formation of the isolation trench, a portion of the width of the source / drain doped region 140 needs to be retained in the isolation region II as a residual source / drain doped region. Therefore, during the formation of the mask opening 170, the opening width of the mask opening 170 along the lateral direction can be appropriately reduced, so that the opening width of the mask opening 170 along the lateral direction is smaller than the width of the source / drain doped region 140 in the isolation region II. This ensures that after the subsequent etching of the interlayer dielectric layer 150 and the source / drain doped region 140 below the mask opening 170, a portion of the width of the source / drain doped region 140 can still be retained on both sides of the formed isolation trench.

[0128] like Figure 10 As shown, using the hard mask layer 160 as a mask, the interlayer dielectric layer 150 and the source / drain doped region 140 are etched along the mask opening 170 to form the isolation trench 180.

[0129] In this embodiment, the interlayer dielectric layer 150, the source / drain doped regions 140, and a portion of the substrate are etched along the mask opening 170 to form the isolation trench 180. This makes the bottom surface of the isolation trench 180 lower than the bottom surface of the residual source / drain doped regions 300, so that the residual source / drain doped regions 300 are separated by the isolation trench 180. This also helps to further reduce the risk of leakage current between adjacent residual source / drain doped regions 300.

[0130] Specifically, in this embodiment, the step of etching the interlayer dielectric layer 150 and the source / drain doped region 140 along the mask opening 170 using the hard mask layer 160 as a mask may include: etching the interlayer dielectric layer 150 of the isolation region II using the hard mask layer 160 as a mask until the source / drain doped region 140 of the isolation region II is exposed, forming an initial trench (not shown); etching the source / drain doped region 140 exposed by the initial trench and a portion of the thickness substrate at the bottom of the source / drain doped region 140 to form the isolation trench 180.

[0131] During the process of etching the interlayer dielectric layer 150 of the isolation region II to form the initial trench, depending on the actual process requirements, the interlayer dielectric layer 150 located in the isolation region II can be completely removed, or only a portion of the thickness of the interlayer dielectric layer 150 of the isolation region II can be etched, only exposing the source and drain doped regions 140 of the isolation region II.

[0132] During the etching process of the source / drain doped regions 140 and part of the substrate exposed by the initial trench, since the material of the interlayer dielectric layer 150 is a dielectric material, a high etching selectivity can be easily achieved between the source / drain doped regions 140 and the interlayer dielectric layer 150, as well as between the substrate and the interlayer dielectric layer 140, thereby enabling etching only the source / drain doped regions 140 and the substrate below the initial trench.

[0133] In this embodiment, the process for forming the isolation trench 180 includes one or both of dry etching and wet etching. As an example, the isolation trench 180 is formed by sequentially performing dry etching and wet etching processes.

[0134] like Figure 11 As shown, the hard mask layer 160 is removed.

[0135] It should be noted that the steps for forming the isolation trench 180 described above are merely an example, and the steps for forming the isolation trench 180 are not limited to this. For example, in other embodiments, the steps for forming the isolation trench may further include: etching the interlayer dielectric layer of the isolation region to form an initial trench exposing the source / drain doped regions of the isolation region; forming a mask sidewall layer on the sidewall of the initial trench; and removing the source / drain doped regions exposed by the mask sidewall layer to form the isolation trench.

[0136] In other embodiments, during the formation of the initial trench, the opening width of the initial trench can be relatively large along the lateral direction. Subsequently, a mask sidewall layer is formed on the sidewall of the initial trench to reduce the lateral dimension of the initial trench. This allows the portion of the source / drain doped region located below the mask sidewall layer to be retained under the shielding effect of the mask sidewall layer during the removal of the source / drain doped region exposed by the mask sidewall layer, and used as the residual source / drain doped region.

[0137] The material of the mask sidewall layer can be a material suitable for use as an etching mask, and the material of the mask sidewall layer has high etching selectivity with the interlayer dielectric layer, source / drain doped regions, or substrate. As an example, the material of the mask sidewall layer is silicon nitride.

[0138] The process for forming the mask sidewall layer includes atomic layer deposition (ALD). ALD has strong step coverage capability, which helps improve the adhesion of the mask sidewall layer to the initial trench sidewall, improves the thickness uniformity of the mask sidewall layer, and facilitates precise control of the formation thickness of the mask sidewall layer, thereby enabling precise control of the width of the removed source / drain doped regions.

[0139] refer to Figures 12 to 14 An isolation structure 200 is formed in the isolation groove 180.

[0140] The isolation structure 200 is used to achieve isolation between adjacent device unit regions I.

[0141] In this embodiment, the isolation structure 200 is a double diffusion break (DDB) isolation structure. The isolation structure 200 is located between adjacent edge gate structures 120(a) and is used to achieve electrical isolation between adjacent edge gate structures 120(a).

[0142] Specifically, in this embodiment, the isolation structure 200 is located between adjacent edge gate structures 120(a) and in the fin 110 of the isolation region II.

[0143] In this embodiment, the residual source / drain doped region 300 is retained between the isolation structure 200 and the edge gate structure 120(a). Compared with the complete removal of the source / drain doped region 140 of the isolation region II, the retention of the residual source / drain doped region 300 in this embodiment helps to reduce the impact of the isolation structure 200 on the performance of surrounding devices, improve the layout consistency of the periphery of the edge gate structure 120(a) with the periphery of other gate structures 120, and thus improve the layout dependency effect.

[0144] Therefore, the material of the isolation structure 200 is a dielectric material, which gives the isolation structure 200 insulating properties and prevents bridging between adjacent devices.

[0145] Specifically, the material of the isolation structure 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and boron silicon carbide. The isolation structure 200 can be a single-layer or multi-layer structure. In this embodiment, the isolation structure 200 is a single-layer structure, and the material of the isolation structure 200 is silicon oxide. Silicon oxide is an easily obtainable insulating material, which helps to reduce the cost of the isolation structure 200 and improve process compatibility. Furthermore, silicon oxide has a low dielectric constant, which helps to improve the isolation effect of the isolation structure 200 on adjacent devices.

[0146] In this embodiment, along the lateral direction, the width of the isolation structure 200 is 50% to 90% of the width of the source / drain doped region 140.

[0147] In this embodiment, the bottom surface of the isolation structure 200 is lower than the bottom surface of the residual source / drain doped region 300, thereby reducing the probability of leakage current being generated between the residual source / drain doped regions 300, which is beneficial to further improve the isolation effect of the isolation structure 200 on the adjacent device unit region I.

[0148] Specifically, in this embodiment, along the direction of the normal to the substrate surface (e.g. Figure 13 (As shown in the z-direction), the bottom surface of the isolation structure 200 is 5 nm to 30 nm lower than the bottom surface of the residual source / drain doped region 300.

[0149] In this embodiment, the step of forming the isolation structure 200 in the partition trench 180 includes: as follows Figure 12 As shown, Figure 12 Based on Figure 11 A cross-sectional view showing an insulating material layer 190 filling the partition groove 180, the insulating material layer 190 also being formed on the interlayer dielectric layer 150; as Figure 13 and Figure 14 As shown, Figure 13 It is a 3D image. Figure 14 for Figure 13 A cross-sectional view along the AA direction, with the isolation material layer 190 above the top surface of the interlayer dielectric layer 150 removed, the remaining isolation material layer 190 is used as the isolation structure 200.

[0150] In this embodiment, the process for forming the isolation material layer 190 includes one or more of the following: chemical vapor deposition, flow-through chemical vapor deposition, high aspect ratio process, atomic layer deposition process, spin coating process, plasma-enhanced chemical vapor deposition process, and low-pressure chemical vapor deposition process.

[0151] The process for forming the isolation material layer 190 has a high gap filling capability. Therefore, even when the opening width of the isolation groove 180 is smaller than that of the prior art, it is also beneficial to improve the filling quality of the isolation material layer 190 in the isolation groove 180, reduce the probability of defects such as voids in the isolation material layer 190, and correspondingly improve the film formation quality of the isolation structure 200. This, in turn, helps to improve the isolation effect of the isolation structure 200 on adjacent device unit areas.

[0152] In this embodiment, a chemical mechanical planarization (CMP) process is used to remove the isolation material layer 190 that is above the top surface of the interlayer dielectric layer 150. CMP is a global planarization process with high planarization efficiency and is beneficial for improving the flatness of the planarized film surface. Therefore, by selecting CMP, it is beneficial to remove the isolation material layer 190 that is above the top surface of the interlayer dielectric layer 150, while also improving the top surface flatness of the isolation structure 180 and the interlayer dielectric layer 150, thereby providing a flat top surface for subsequent processes.

[0153] It should be noted that in this embodiment, the gate structure 120 is used as an example of a device gate structure for illustration.

[0154] In other embodiments, when the gate structure is a sacrificial gate structure during the step of providing the substrate, the method for forming the semiconductor structure further includes: after forming the isolation structure, removing the sacrificial gate structure and forming a gate opening in the interlayer dielectric layer; and forming a device gate structure in the gate opening. The device gate structure is correspondingly a metal gate structure.

[0155] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes discrete device cell regions and isolation regions located between the device cell regions; The gate structure is discretely located on the substrate of the device cell region. The gate structure located at the edge of the device cell region and near the junction of the device cell region and the isolation region is called the edge gate structure. The extension direction of the gate structure is longitudinal, and the direction parallel to the substrate and perpendicular to the longitudinal direction is transverse. The source / drain doped regions are located in the substrate of the device cell regions on both sides of the gate structure; the source / drain doped regions include stress layers doped with ions; An isolation structure is located between adjacent edge gate structures and in a portion of the thickness of the substrate of the isolation region; The residual source / drain doped region is located laterally between the sidewall of the isolation structure and the substrate, and is disposed laterally on both sides of the isolation structure; the residual source / drain doped region and the source / drain doped region are continuous doped regions formed by the same process, and the residual source / drain doped region includes a stress layer doped with ions; the bottom surface of the isolation structure is lower than the bottom surface of the residual source / drain doped region.

2. The semiconductor structure as described in claim 1, characterized in that, Along the lateral direction, the width of the isolation structure is 50% to 90% of the width of the source / drain doped region.

3. The semiconductor structure as described in claim 1, characterized in that, Along the direction of the normal to the substrate surface, the bottom surface of the isolation structure is 5 nm to 30 nm lower than the bottom surface of the residual source / drain doped region.

4. The semiconductor structure as described in claim 1, characterized in that, When forming an NMOS transistor, the material of the stress layer includes Si or SiC; When forming a PMOS transistor, the material of the stress layer includes Si or SiGe.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an interlayer dielectric layer, located on the substrate on the side of the gate structure and covering the source and drain doped regions; The isolation structure is located in the interlayer dielectric layer and the substrate of the isolation zone.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a substrate and fins protruding from the substrate; The gate structure spans the fin and covers a portion of the top and a portion of the sidewalls of the fin; The source and drain doped regions are located in the fins of the device cell regions on both sides of the gate structure; The isolation structure is located between adjacent edge gate structures and within the fins of the isolation region; The residual source / drain doped region is located between the sidewall of the isolation structure and the fin.

7. The semiconductor structure as described in claim 1, characterized in that, The gate structure is a metal gate structure; or, the gate structure is a polysilicon gate structure.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including discrete device cell regions and isolation regions located between the device cell regions. Discrete gate structures are formed on the substrate of the device cell regions. Gate structures located at the edges of the device cell regions and near the boundary between the device cell regions and the isolation regions are designated as edge gate structures. The extension direction of the gate structures is longitudinal, and the direction parallel to the substrate and perpendicular to the longitudinal direction is transverse. Source and drain doped regions are formed in the substrate on both sides of the gate structures. An interlayer dielectric layer is formed on the substrate on the side of the gate structures, covering the source and drain doped regions. The source and drain doped regions include stress layers doped with ions. An isolation trench is formed that penetrates the interlayer dielectric layer and the source / drain doped regions of the isolation region. The isolation trench is located between adjacent edge gate structures, and a portion of the source / drain doped regions is retained along the sidewalls of both sides of the transverse isolation trench as residual source / drain doped regions. The residual source / drain doped regions and the source / drain doped regions are continuous doped regions formed by the same process. The residual source / drain doped regions include a stress layer doped with ions. An isolation structure is formed in the isolation trench, the bottom surface of which is lower than the bottom surface of the residual source / drain doped region.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the isolation trench includes: forming a hard mask layer on the interlayer dielectric layer and the gate structure, wherein a mask opening is formed in the hard mask layer above the isolation region; and etching the interlayer dielectric layer and the source / drain doped regions along the mask opening to form the isolation trench.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the isolation trench includes: etching the interlayer dielectric layer of the isolation region to form an initial trench that exposes the source and drain doped regions of the isolation region; A mask sidewall layer is formed on the sidewall of the initial trench; The source / drain doped regions exposed by the mask sidewall layer are removed to form the isolation trench.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for forming the partition trench includes one or both of dry etching and wet etching.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming an isolation structure in the partition trench includes: forming an isolation material layer filling the partition trench, the isolation material layer also being located on the interlayer dielectric layer; removing the portion of the isolation material layer above the top surface of the interlayer dielectric layer, the remaining isolation material layer being used as the isolation structure.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the isolation material layer includes one or more of the following: chemical vapor deposition, flow-through chemical vapor deposition, high aspect ratio process, atomic layer deposition process, spin coating process, plasma-enhanced chemical vapor deposition process, and low-pressure chemical vapor deposition process.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the isolation trench, the isolation trench also penetrates a portion of the thickness of the substrate at the bottom of the source / drain doped region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the isolation trench, along the direction of the normal to the substrate surface, the bottom surface of the isolation trench is 5 nm to 30 nm lower than the bottom surface of the source / drain doped region.

16. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the isolation trench, along the transverse direction, the width of the isolation trench is 50% to 90% of the width of the source / drain doped region.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, the gate structure is a sacrificial gate structure; The method for forming the semiconductor structure further includes: after forming the isolation structure, removing the sacrificial gate structure and forming a gate opening in the interlayer dielectric layer; A device gate structure is formed in the gate opening.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a substrate, the substrate includes a substrate and a fin protruding from the substrate, the gate structure spans the fin and covers a portion of the top and a portion of the sidewalls of the fin, and the source / drain doped regions are located in the fins on both sides of the gate structure; In the step of forming the isolation trench, the isolation trench is located in the interlayer dielectric layer between adjacent edge gate structures and penetrates the source and drain doped regions of the isolation region.

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