Method for manufacturing a semiconductor

Abstract

A method of fabricating a semiconductor is described herein. The implant mask formation techniques mentioned in the method of fabrication include increasing an initial aspect ratio of a pattern in an implant mask through non-lithography techniques, which can include forming a hardening resistant layer on the implant mask. The pattern can be formed to an initial aspect ratio through optical lithography techniques that reduce or minimize the likelihood of the pattern collapsing during pattern formation. Next, a hardening resistant layer is formed on the implant mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the opening or trench of the pattern and the width of the opening or trench. In this way, the pattern in the implant mask can be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of the pattern collapsing during pattern formation.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor. Background Technology

[0002] Digital cameras and other optical imaging devices employ image sensors. Image sensors convert optical images into digital data that can be represented as digital images. An image sensor includes a pixel sensor array and supporting logic. The pixel sensors in the array are unit devices used to measure incident light, and the supporting logic facilitates the readout of the measurements. One type of image sensor commonly used in optical imaging devices is the backside illumination (BSI) image sensor. BSI image sensors can be manufactured at low cost, in small size, and with high integration into semiconductor processes. Furthermore, BSI image sensors can feature low operating voltage, low power consumption, high quantum efficiency, and low readout noise, and allow random access. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method of manufacturing a semiconductor includes the following steps: forming a pattern in a photoresist layer above a substrate, wherein the pattern includes a plurality of trenches through the photoresist layer; performing an anti-hardening operation on the photoresist layer to form a hardened layer on a top surface of the photoresist layer and on a plurality of sidewalls of the trenches; and after performing the anti-hardening operation, performing an ion implantation operation to use the pattern as an implantation mask to form one or more isolation wells in the substrate.

[0004] According to some embodiments of this disclosure, a method of manufacturing a semiconductor includes the following steps: forming a plurality of trenches through a photoresist layer above a substrate; performing a surface treatment operation using a perfluorinated compound on a top surface of the photoresist layer and a plurality of sidewalls of the trenches, wherein the perfluorinated compound reacts with the photoresist layer to form a hardened layer on the top surface of the photoresist layer and the plurality of sidewalls of the trenches, wherein the carbon density of the hardened layer is greater than that of the photoresist layer; and after performing the surface treatment operation, performing an ion implantation operation to form a plurality of isolation wells in the substrate using the photoresist layer and the trenches as an implantation mask.

[0005] According to some embodiments of this disclosure, a method of manufacturing a semiconductor includes the following steps: forming a plurality of trenches through a photoresist layer above a substrate, wherein an aspect ratio between a height and a width of the plurality of trenches is equal to or less than 8; after forming the trenches, increasing the aspect ratio of the trenches to equal to or greater than 10; after increasing the aspect ratio and using the photoresist layer, performing an ion implantation operation to form a plurality of isolation wells in the substrate based on the trenches; forming an isolation structure in the substrate and above the isolation wells; forming a plurality of photodiodes including a plurality of pixel sensors in a pixel array between the isolation wells and between the isolation structure; forming a plurality of color filter regions above the photodiodes; and forming a microlens layer above the color filter regions. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A diagram of an instance environment in which the systems and / or methods described herein can be implemented;

[0008] Figure 2 and Figure 3 This is a diagram of the example pixel sensor described in this article;

[0009] Figures 4A to 4O This is a diagram illustrating the implementation of the example described in this article;

[0010] Figure 5 yes Figure 1 A diagram of one or more device components;

[0011] Figures 6 to 8 This is a flowchart of an example process related to the formation of isolation wells.

[0012] [Symbol Explanation]

[0013] AA: Line

[0014] H1~3: Height

[0015] T1: Thickness

[0016] W1~3: Width

[0017] 100: Environment

[0018] 102: Sedimentation tools

[0019] 104: Exposure Tools

[0020] 106: Developer Tools

[0021] 108: Etching Tools

[0022] 110: Flattening tool

[0023] 112: Electroplating tools

[0024] 114: Ion Implantation Tools

[0025] 116: Wafer / Chip Transfer Tools

[0026] 200: pixel array

[0027] 202: Pixel Sensor

[0028] 204: Isolation Well

[0029] 300: pixel array

[0030] 302a~c: Pixel sensor

[0031] 304:Substrate

[0032] 306: Photodiode

[0033] 308: Isolation Well

[0034] 310: Isolation Structure

[0035] 312:ARC

[0036] 314: Dielectric layer

[0037] 316: Metal layer

[0038] 318: Grid Structure

[0039] 320a~c: Color filter area

[0040] 322: Microlens layer

[0041] 400: Implementation Example

[0042] 402: Photoresist layer

[0043] 404: Pattern

[0044] 406: Hardened layer

[0045] 408: Implant Mask

[0046] 410: Ions

[0047] 412: Opening

[0048] 414: Opening

[0049] 500: Device

[0050] 510: Bus

[0051] 520: Processor

[0052] 530: Memory

[0053] 540: Storage Components

[0054] 550: Input component

[0055] 560: Output Component

[0056] 570: Communication Components

[0057] 600: Process

[0058] 610: Square

[0059] 620: Square

[0060] 630: Square

[0061] 700: Process

[0062] 710: Square

[0063] 720: Square

[0064] 730: Square

[0065] 800: Process

[0066] 810: Square

[0067] 820: Square

[0068] 830: Square

[0069] 840: Square

[0070] 850: Square

[0071] 860: Square

[0072] 870: Square Detailed Implementation

[0073] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0074] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element(s) or feature(s), spatial relative terms such as "below," "under," "lower," "above," "upper," and the like are used herein. Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0075] Isolation wells can be used to provide electrical isolation between photodiodes of adjacent pixel sensors in a pixel array. Isolation wells can be formed via ion implantation. An implantation mask can be patterned to define the location of the isolation well in the substrate in which it is to be formed. Several problems can arise when forming patterns in an implantation mask. For example, a high aspect ratio implantation mask used to form a high aspect ratio isolation well may experience strong capillary action during the cleaning process. Here, capillary action causes cleaning agent to be drawn into openings or trenches in the implantation mask. When the implantation mask dries, the cleaning agent in the openings or trenches can exert stress on the implantation mask, and if the implantation mask has a high aspect ratio (e.g., if the aspect ratio between the height and width of the opening or trench is above about 8), this can cause the pattern in the implantation mask to collapse.

[0076] Some embodiments described herein provide techniques for implant mask formation to reduce and / or minimize implant mask collapse and / or other failures during implant mask formation. The techniques described herein can be used to increase the aspect ratio of implant masks, enabling the formation of ultra-high aspect ratio implant masks (e.g., implant masks with openings between structures having an aspect ratio of about 10 or greater). Ultra-high aspect ratio isolation masks can be used to form ultra-high aspect ratio isolation wells with similar aspect ratios, enabling the size of pixel sensors including the isolation wells to be reduced to sub-micron dimensions (e.g., width or diameter). This enables size reduction in pixel arrays and complementary metal oxide (CMOS) image sensors including pixel sensors, and enables increased pixel sensor density in pixel arrays, which further improves the performance of the pixel array.

[0077] As described herein, an implantable mask can be formed by patterning a photoresist layer. The pattern may include multiple trenches (and / or other types of openings) having an initial aspect ratio equal to or less than about 8 between the trench height and the trench width. Next, an anti-curing operation is performed to conformally form an anti-curing layer on the pattern and the sidewalls of the trenches. The anti-curing operation may include performing a surface treatment operation using a perfluorinated compound conformally deposited on the pattern and the sidewalls of the trenches. The perfluorinated compound may locally and partially crosslink with the material of the photoresist layer to form a cured carbon-based shell as the anti-curing layer on the photoresist layer.

[0078] The formation of the anti-hardening layer increases the initial aspect ratio of the grooves in the implant mask pattern from about 8 or less to a final aspect ratio of about 10 or greater. In this way, the implant mask is initially formed with a relatively low aspect ratio via optical lithography (which reduces the likelihood of collapse and other pattern defects in the implant mask), and the aspect ratio of the implant mask is increased via non-lithography techniques. Furthermore, the increased stiffness of the anti-hardening layer (e.g., relative to the photoresist layer) can further reduce the likelihood of pattern collapse by improving the implant mask's ability to block or resist ion implantation into the photomask layer during ion implantation operations.

[0079] Therefore, the formation of the anti-hardening layer can be combined with optical lithography to form an ultra-high aspect ratio implantation mask, rather than solely using optical lithography. This improves pattern quality (e.g., increases pattern resolution and reduces pattern defects), enabling an increase in the aspect ratio of isolation wells formed using ultra-high aspect ratio implantation masks, an increase in the full well capacity (FWC) of isolation wells, and / or enabling deeper implantation of isolation wells.

[0080] Figure 1This is a diagram of instance environment 100, in which the systems and / or methods described in this article can be implemented. For example... Figure 1 As shown, environment 100 may include a plurality of semiconductor processing tools 102-114 and a wafer / wafer transfer tool 116. The plurality of semiconductor processing tools 102-114 may include deposition tools 102, exposure tools 104, developer tools 106, etching tools 108, planarization tools 110, electroplating tools 112, ion implantation tools 114, and / or other types of semiconductor processing tools. Tools included in example environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities, and other examples.

[0081] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, instance environment 100 includes multiple types of deposition tools 102.

[0082] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., deep ultraviolet light, extreme ultraviolet (EUV) light, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0083] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer exposed to a radiation source, thereby developing a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by using a chemical developer to dissolve either the exposed or unexposed portions of the photoresist layer.

[0084] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, and / or the like. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gases to isotropically or directionally etch the one or more portions.

[0085] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or electroplated material. Planarization tool 110 can use a combination of chemical and mechanical forces (e.g., chemical etching and abrasive-free polishing) to polish or planarize the surface of a semiconductor device. Planarization tool 110 may combine a polishing pad and a retainer (e.g., whose diameter is typically larger than the diameter of the semiconductor device) using abrasive and etchant chemical slurries. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and secured in place by the retainer. The dynamic polishing head can rotate on different axes of rotation to remove material and even out any irregularities in the topography of the semiconductor device, making the semiconductor device flat or planar.

[0086] Electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, electroplating tool 112 may include a copper electroplating apparatus, an aluminum electroplating apparatus, a nickel electroplating apparatus, a tin electroplating apparatus, a composite material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating apparatus, and / or an electroplating apparatus for one or more other types of conductive materials, metals, and / or similar materials.

[0087] Ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. Ion implantation tool 114 can generate ions from a source material (such as a gas or solid) in an arc chamber. The source material can be supplied to the arc chamber, and an arc voltage is discharged between the cathode and electrodes to generate a plasma containing ions from the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed towards the substrate, such that the ions are implanted below the surface of the substrate.

[0088] Wafer / wafer transfer equipment 116 includes mobile robots, robotic arms, trams or railcars, overhead hoist transport (OHT) systems, automated materially handling systems (AMHS), and / or other types of devices for transferring wafers and / or wafers between semiconductor processing equipment 102-114 and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some implementations, wafer / wafer transfer equipment 116 may be a programmable device designed to travel a specific path and / or be semi-autonomous or autonomous.

[0089] Figure 1 The number and configuration of the devices shown are provided as one or more instances. In practice, additional devices, fewer devices, different devices, or devices may exist. Figure 1 The devices with these different configurations are shown. Furthermore, Figure 1 The two or more devices shown can be implemented within a single device, or Figure 1 The single device shown may be implemented as multiple, distributed devices. Additionally or alternatively, a group of devices in environment 100 (e.g., one or more devices) may perform one or more functions described as being performed by another group of devices in environment 100.

[0090] Figure 2 A top-down view of pixel array 200 is shown. In some implementations, pixel array 200 may be included in an image sensor. The image sensor may include a complementary metal-oxide-semiconductor (CMOS) image sensor, a back-illuminated (BSI) CMOS image sensor, a front-side illuminated (FSI) CMOS image sensor, or another type of image sensor. Figure 2 As shown, the pixel array 200 may include a plurality of pixel sensors 202. Figure 2 As further shown, the pixel sensor 202 can be configured as a grid. In some implementations, the pixel sensor 202 is square (e.g., Figure 2 (As shown in the example). In some implementations, the pixel sensor 202 includes other shapes, such as circular, octagonal, rhomboid, and / or other shapes.

[0091] Pixel sensor 202 can be used to sense and / or accumulate incident light (e.g., light directed towards pixel array 200). For example, pixel sensor 202 can absorb and accumulate photons of incident light in a photodiode. The accumulation of photons in the photodiode can generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge can correspond to a larger intensity or brightness, and a smaller amount of charge can correspond to a smaller intensity or brightness).

[0092] In some implementations, the pixel sensor 202 has a size (e.g., width or diameter) of approximately 1 micrometer. In some implementations, the pixel sensor 202 has a size (e.g., width or diameter) of less than approximately 1 micrometer. In these examples, the pixel sensor 202 may be referred to as a submicron pixel sensor. Submicron pixel sensors can reduce the pixel sensor pitch (e.g., the distance between adjacent pixel sensors) in the pixel array 200, which can enable increased pixel sensor density in the pixel array 200 (which can improve the performance of the pixel array 200).

[0093] Pixel sensor 202 can be electrically and optically isolated via one or more isolation wells 204 included in pixel array 200. Isolation wells 204 can include multiple interconnect doped regions of the substrate of pixel array 200. The doped regions can be doped with various types of ions (e.g., p-type ions, n-type ions) via ion implantation. Isolation wells 204 can be included around pixel sensor 202, such that isolation wells 204 surround pixel sensor 202, as... Figure 2 As shown above, pixel array 200 may be included in a BSI CMOS image sensor. In these examples, isolation wells 204 may be formed from the back side of pixel array 200.

[0094] The pixel array 200 can be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of the image sensor. The BEOL metallization stack can electrically connect the pixel array 200 to a control circuitry system that can measure the accumulation of incident light in the pixel sensor 202 and convert the measurement into an electrical signal.

[0095] As shown above, Figure 2 It is provided as an instance. Other instances may differ from those provided. Figure 2 The description.

[0096] Figure 3 This is a diagram of the example pixel array 300 described herein. In some embodiments, the pixel array 300 is configured and / or implements a pixel sensor 202 and is included in the pixel array 200. In some embodiments, the pixel array 300 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0097] like Figure 3 As shown, pixel array 300 may include a plurality of adjacent pixel sensors, such as pixel sensors 302a-302c. In some embodiments, pixel sensors 302a-302c are configured as pixel sensors 202 included in pixel array 200. In some embodiments, pixel sensors 302a-302c include pixel sensors of various shapes, such as square pixel sensors, octagonal pixel sensors, pixel sensors of another shape, or combinations thereof. Pixel array 300 may include more than Figure 3 The number of pixels shown may be larger or smaller.

[0098] Pixel sensor 302 may be formed in substrate 304, which may include a semiconductor wafer substrate, a semiconductor wafer, or another type of substrate in which semiconductor pixels may be formed. In some embodiments, substrate 304 is formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material capable of generating charge from photons of incident light.

[0099] Each pixel sensor 302 may include a photodiode 306. The photodiode 306 may include regions of a substrate 304 doped with various types of ions to form pn-junction regions or PIN junctions (e.g., junctions between p-type portions, intrinsically (or undoped) portions, and n-type portions). For example, the substrate 304 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 306, and with a p-type dopant to form a second portion (e.g., a p-type portion). The photodiode 306 can be used to absorb photons of incident light. The absorption of photons causes the photodiode 306 to accumulate charge (called photocurrent) due to the photoelectric effect. Here, photons bombard the photodiode 306, causing the emission of electrons from the photodiode 306. The emission of electrons leads to the formation of electron-hole pairs, where electrons migrate towards the cathode of the photodiode 306, and these holes migrate towards the anode, thereby generating a photocurrent.

[0100] The pixel array 300 may include multiple regions to provide electrical and / or optical isolation between pixel sensors 302. The pixel array 300 may include multiple isolation wells 308 in a substrate 304. The isolation wells 308 may include cell p-well regions (CPWs), deep p-well regions (DPWs), and / or other types of doped regions. The isolation wells 308 may surround the photodiode 306 of the pixel sensor 302. Each isolation well 308 may include p... + Doped silicon material or another p + Doped materials, n + Doped silicon material or another n + Doped materials, and / or another type of doped material.

[0101] Isolation wells 308 (or subsets thereof) can be formed by one or more ion implantation operations using an implantation mask formed using one or more implantation mask formation techniques described herein. The implantation mask formation techniques enable isolation wells 308 to be formed with a high aspect ratio (or ultra-high aspect ratio) between the height (H1) and width (W1) of isolation wells 308. As an example, the implantation mask formation techniques enable isolation wells 308 to be formed with an aspect ratio of about 10 or greater to achieve a larger isolation well height (H1) and / or a smaller isolation well width (W1), which can provide improved full-well capacity (FWC) and / or improved isolation performance for isolation wells 308. Examples of the height (H1) of isolation wells 308 range from about 1800 nm to about 2100 nm to provide sufficient optical and / or electrical isolation and reduce damage to the substrate 304. In one example, the width (W1) of the isolation well 308 ranges from about 180 nanometers to about 210 nanometers to provide sufficient optical and / or electrical isolation and reduce damage to the substrate 304. However, other values ​​for the height (H1), width (W1), and / or aspect ratio are within the scope of this disclosure.

[0102] An isolation structure 310 (e.g., a deep trench isolation (DTI) structure or a shallow trench isolation (STI) structure) may be included in a substrate 304 above the isolation well 308. The isolation structure 310 may include one or more trenches extending downwards to the substrate 304 and similar to the isolation well 308 surrounding the photodiode 306. The isolation structure 310 provides optical isolation between the pixel sensor 302 and one or more adjacent pixel sensors 302 to reduce the amount of optical crosstalk between the pixel sensor 302 and one or more adjacent pixel sensors 302. Specifically, the isolation structure 310 may absorb, refract, and / or reflect incident light, which can reduce the amount of incident light traveling through the pixel sensor 302 into adjacent pixel sensors 302 and being absorbed by the adjacent pixel sensors 302. The isolation structure 310 may include one or more dielectric materials, such as silicon oxide (SiO2). x (For example, silicon dioxide (SiO2) and hafnium oxide (HfO) x Hafnium silicon oxide (HfSiO) x Aluminum oxide (Al) x O y ), and / or another oxide material.

[0103] An antireflective coating (ARC) 312 may be present on and / or on the substrate 304, on and / or on the isolation structure 310, and / or on and / or on the photodiode 306. ARC 312 may include a suitable material for reducing reflection of incident light projected toward the photodiode 306. For example, ARC 312 may include a nitrogen-containing material and / or another type of material.

[0104] Dielectric layer 314 may be present above and / or on ARC 312. Dielectric layer 314 may comprise organic materials, oxides, nitrides, and / or another type of dielectric material, such as silicon oxide (SiOx) (e.g., silicon dioxide (SiO2)), hafnium oxide (HfO) x Hafnium oxide (HfSiOx), aluminum oxide (Al) x O y Silicon nitride (Si) x N y Zirconium dioxide (ZrO) x ), magnesium oxide (MgO) x ), Yttrium oxide (Y) x O y ), tantalum oxide (Ta x O y Titanium oxide (TiO) x lanthanum oxide (La) x O y Barium oxide (BaO) x Silicon carbide (SiC) and lanthanum aluminum oxide (LaAlO) x ), strontium oxide (SrO), and zirconium silicon oxide (ZrSiO) x ), and / or calcium oxide (CaO), and other examples.

[0105] Metal layer 316 may be present above and / or on dielectric layer 314. Metal layer 316 may comprise a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), another type of conductive material, and / or an alloy comprising one or more of the foregoing. Metal layer 316 may be used to reflect a portion of the incident light to reduce optical crosstalk.

[0106] The mesh structure 318 may be located above and / or on the ARC 312, above the isolation structure 310, and / or above the substrate 304. The mesh structure 318 may include multiple interconnect rows formed by one or more layers etched to form rows. The mesh structure 318 may be located above the pixel sensor 302 and may surround the periphery of the pixel sensor 302. The mesh structure 318 may be used in conjunction with the isolation structure 310 and the isolation well 308 to provide optical isolation and additional crosstalk reduction.

[0107] In some implementations, the mesh structure 318 includes a dielectric layer 314 and a metal layer 316, and may be referred to as a metal mesh or a composite metal grid (CMG). The metal layer 316 can be used to reflect and / or absorb incident light to reduce optical crosstalk between adjacent pixel sensors 302. In some implementations, the metal layer 316 is omitted from the mesh structure 318, and the mesh structure 318 may be referred to as an oxide mesh, a dielectric mesh, or a color filter in a box (CIAB) mesh, among other examples.

[0108] Each color filter region 320 may be included in the region surrounded by the grid structure 318. For example, color filter region 320a may be formed between rows of the grid structure 318 above the photodiode 306 of pixel sensor 302a, color filter region 320b may be formed between rows of the grid structure 318 above the photodiode 306 of pixel sensor 302b, color filter region 320c may be formed between rows of the grid structure 318 above the photodiode 306 of pixel sensor 302c, and so on. The refractive index of the color filter region 320 may be greater than that of the grid structure 318 to increase the probability of total internal reflection in the color filter region 320 at the interface between the sidewalls of the color filter region 320 and the sidewalls of the grid structure 318, which can improve the quantum efficiency of pixel sensor 302.

[0109] Each color filter region 320 can be used to filter incident light to allow incident light of a specific wavelength to reach the photodiode 306 of the associated pixel sensor 302. For example, color filter region 320a included in pixel sensor 302a can filter red light for pixel sensor 302a (and therefore, pixel sensor 302a can be a red pixel sensor), color filter region 320b included in pixel sensor 302b can filter green light for pixel sensor 302b (and therefore, pixel sensor 302b can be a green pixel sensor), color filter region 320c included in pixel sensor 302c can filter blue light for pixel sensor 302c (and therefore, pixel sensor 302c can be a blue pixel sensor), and so on.

[0110] The blue filter area allows incident light components with wavelengths up to 450 nm to pass through filter area 320 while blocking other wavelengths. The green filter area allows incident light components with wavelengths up to 550 nm to pass through filter area 320 while blocking other wavelengths. The red filter area allows incident light components with wavelengths up to 650 nm to pass through filter area 320 while blocking other wavelengths. The yellow filter area allows incident light components with wavelengths up to 580 nm to pass through filter area 320 while blocking other wavelengths.

[0111] In some implementations, the color filter 320 may be non-discriminative or unfiltered, forming a white pixel sensor. The non-discriminative or unfiltered color filter 320 may include a material that allows light of all wavelengths to pass into the associated photodiode 306 (e.g., to determine total brightness to improve the photosensitivity of the image sensor). In some implementations, the color filter 320 may be an NIR bandpass filter, defining a near-infrared (NIR) pixel sensor. The NIR bandpass filter 320 may include a material that allows a portion of incident light in the NIR wavelength range to pass into the associated photodiode 306 while blocking visible light.

[0112] Microlens layer 322 may be included on and / or on color filter area 320. Microlens layer 322 may include respective microlenses in pixel sensors 302. For example, a microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302a, another microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302b, another microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302c, and so on.

[0113] As shown above, Figure 3 It is provided as an instance. Other instances may differ from those provided. Figure 3 The description.

[0114] Figures 4A to 4OThis is a diagram of Example Implementation 400 described herein. Example Implementation 400 may be an example process or method for forming a pixel array 300. Example Implementation 400 may include an implantation mask formation technique for forming isolation wells 308 of the pixel array 300. Combined with Figures 4A to 4O The described implant mask forming technique can reduce and / or prevent pattern collapse and / or other types of failures in the implant mask used to form the isolation well 308. Therefore, combined with Figures 4A to 4O The described implantation mask formation technique allows the mask pattern to be formed with an increased aspect ratio (e.g., equal to and / or greater than about 10), which enables the formation of ultra-high aspect ratio implantation wells (e.g., equal to and / or greater than about 10) and / or enables pixel sensor size (or pixel sensor pitch) to be reduced to submicron size.

[0115] like Figure 4A As shown, pixel sensors 302 (e.g., pixel sensors 302a, 302b, 302c, and the like) may be formed in substrate 304. Substrate 304 may include a silicon substrate, a substrate formed of a material including silicon, a III-V compound semiconductor substrate such as a gallium arsenide (GaAs) substrate, a silicon-on-insulator (SOI) substrate, or another type of substrate capable of generating charge from photons of incident light.

[0116] Figure 4B The illustration shows a top-down view of pixel array 300 and a cross-sectional view along line AA. (See illustration.) Figure 4B As shown, a photoresist layer 402 may be formed above and / or on the substrate 304. The photoresist layer 402 may include a photoresist material. The deposition tool 102 may deposit the photoresist material using a spin-coating technique or another deposition technique to form the photoresist layer 402.

[0117] Figure 4C The illustration shows another top-down view of pixel array 300 and another cross-sectional view along line AA. (See illustration.) Figure 4C As shown, a pattern 404 can be formed in the photoresist layer 402 by removing multiple portions of the photoresist layer 402. The pattern 404 can be formed by exposing the photoresist layer 402 to a radiation source (e.g., using an exposure tool 104) and removing the exposed or unexposed portions of the photoresist layer 402 (e.g., using a developer tool 106). In this way, the pattern 404 is formed onto the substrate 304 through the photoresist layer 402 (e.g., from the top surface of the photoresist layer 402 through the bottom surface of the photoresist layer 402). Figure 4C As further shown, pattern 404 may include a grid shape.

[0118] The mesh may include multiple trenches intersecting at different locations within the photoresist layer 402. The deposition tool 102 may be formed through the photoresist layer 402 into trenches with an initial width (W2) ranging from about 200 nanometers to about 260 nanometers to reduce and / or minimize capillary action in the trenches that could cause the pattern 404 to collapse. However, other values ​​for the initial width (W2) are within the scope of this disclosure. Furthermore, the deposition tool 102 may be formed through the photoresist layer 402 into trenches with a height (H2) of about 1 micrometer to about 2 micrometers to reduce and / or minimize the likelihood of pattern 404 collapse. However, other values ​​for the height (H2) are within the scope of this disclosure.

[0119] Figure 4D The illustration shows another top-down view of pixel array 300 and another cross-sectional view along line AA. (See illustration.) Figure 4D As shown, a hardened layer 406 may be formed above and / or on the top surface of the photoresist layer 402 and on the sidewalls of the trenches of the pattern 404 on the photoresist layer 402. To form the hardened layer 406, an anti-hardening operation may be performed on the top surface of the photoresist layer 402 and the sidewalls of the trenches. The anti-hardening operation increases the hardness of the top surface of the photoresist layer 402 and the sidewalls of the trenches, which reduces damage to the top surface of the photoresist layer 402 and the sidewalls of the trenches during ion implantation operations to form the isolation well 308.

[0120] Anti-hardening operations may include performing surface treatment on the top surface of the photoresist layer 402 and the sidewalls of the trenches using a perfluorinated compound. The perfluorinated compound may include compounds comprising carbon-fluorine bonds and carbon-carbon bonds, such as fluorinated carbon (C₂). x F y ), fluorinated hydrocarbons (C x HF y Perfluorinated compounds, and / or other types of perfluorinated compounds. The deposition tool 102 can use PECVD technology and / or another CVD technology to deposit the perfluorinated compound onto the top surface of the photoresist layer 402 and the sidewalls of the trench. The perfluorinated compound can contact the top surface of the photoresist layer 402 and the sidewalls of the trench, and can react with the material of the photoresist layer 402, and can locally and partially crosslink with the material of the photoresist layer 402 to form a hardened layer 406.

[0121] The hardened layer 406 may include a carbon-based shell, which has a greater carbon density than the material of the photoresist layer 402 due to the carbon in the perfluorinated compound. This greater carbon density increases the hardness of the top surface of the photoresist layer 402 and the sidewalls of the trenches, which reduces damage to the top surface of the photoresist layer 402 and the sidewalls of the trenches during ion implantation operations to form the isolation well 308.

[0122] like Figure 4D As further shown, the hardening layer 406 may have a thickness (T1) ranging from about 10 nanometers to about 30 nanometers to reduce the initial width of the trenches in pattern 404, thereby increasing the aspect ratio between the height (H3) and width (W3) of the trenches to be equal to or greater than about 10. In this way, the increased aspect ratio of the trenches can be used to form the isolation well 308 with an ultra-high aspect ratio. The hardening layer 406 can reduce the width of the trenches in pattern 404 to a width (W3) ranging from about 180 nanometers to about 230 nanometers, thereby enabling the isolation well 308 to be formed with an ultra-high aspect ratio. However, other values ​​of the width (W3) are within the scope of this disclosure. The deposition tool 102 may perform an anti-hardening operation (e.g., by depositing a perfluorinated compound) for a duration ranging from about 30 seconds to about 120 seconds to achieve a thickness (T1) of the hardening layer 406 ranging from about 10 nanometers to about 30 nanometers. However, other durations are within the scope of this disclosure. The height (H3) of the trench can range from about 1,000 nanometers to about 3,000 nanometers to achieve an aspect ratio of about 10 or greater for the trench.

[0123] like Figure 4E As shown in the cross-sectional view, isolation wells 308 can be formed in substrate 304 based on an implantation mask 408 (e.g., which may include a photoresist layer 402, a hardening layer 406, and a pattern 404). For example, ion implantation tool 114 can dope multiple portions of substrate 304 by implanting ions 410 (e.g., p-type ions, n-type ions) into substrate 304 through trenches in the pattern 404 of the implantation mask 408. Ion implantation tool 114 can use source materials such as boron, phosphorus, and / or another type of source material to generate ions, and can implant ions using high-energy implantation processes (e.g., at 500,000 electron-volts (eV) and / or at different energy levels).

[0124] The ion implantation tool 114 can use the implantation mask 408 to form the isolation well 308 with a high aspect ratio (or ultra-high aspect ratio) between the height (H1) and width (W1) of the isolation well 308. For example, the ion implantation tool 114 can form the isolation well 308 with an aspect ratio of about 10 or greater to achieve a greater isolation well height (H1) and / or a smaller isolation well width (W1), which can provide the isolation well 308 with increased overall well capacity and / or improved isolation performance.

[0125] like Figure 4F As shown in the cross-sectional view, the remaining portions of photoresist layer 402 and hardened layer 406 can be removed from substrate 304. Various techniques can be used to remove the remaining portions of photoresist layer 402 and hardened layer 406, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others.

[0126] like Figure 4G As shown in the cross-sectional view, a plurality of openings 412 can be formed in the substrate 304 above the isolation well 308. A deposition tool 102 can form a photoresist layer on the substrate 304, an exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, a developer tool 106 can develop and remove portions of the photoresist layer to expose the pattern, and an etching tool 108 can etch portions of the substrate 304 to form the openings 412. The etching tool 108 can etch the openings 412 downwards into the substrate 304 (e.g., from the top surface of the substrate 304) up to or near the isolation well 308. In some embodiments, after the etching tool 108 etches the substrate 304, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, a plasma ashing device, and / or another technique).

[0127] like Figure 4H As shown in the cross-sectional view, opening 412 can be filled with oxide material and / or another type of dielectric material to form isolation structure 310. Deposition tool 102 can deposit oxide material in opening 412 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples). In some embodiments, planarization tool 110 planarizes the oxide material after deposition.

[0128] like Figure 4I As shown in the cross-sectional view, one or more semiconductor processing tools can form a plurality of photodiodes 306 in substrate 304. For example, ion implantation tool 114 can use ion implantation technology to dope portions of substrate 304 between trenches of isolation structure 310 and between isolation wells 308 to form respective photodiodes 306 for a plurality of pixel sensors 302 (e.g., pixel sensors 302a-302c). Substrate 304 can be doped with various types of ions to form pn-junctions of the respective photodiodes 306. For example, substrate 304 can be doped with n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 306 and with p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 306. In some embodiments, another technique such as diffusion is used to form photodiodes 306.

[0129] like Figure 4J As shown in the cross-sectional view, ARC 312 can be formed above and / or on substrate 304, above and / or on photodiode 306, and above and / or on isolation structure 310. Deposition tool 102 can use CVD technology, PVD technology, ALD technology, or a combination thereof. Figure 1Another type of deposition technique is described to deposit ARC 312. A planarization tool 110 can planarize ARC 312 after deposition.

[0130] like Figure 4K As shown in the cross-sectional view, dielectric layer 314 may be formed above and / or on ARC 312. Deposition tool 102 may use CVD, PVD, ALD, or a combination thereof. Figure 1 Another type of deposition technique is described to deposit dielectric layer 314. Planarization tool 110 can planarize dielectric layer 314 after deposition.

[0131] like Figure 4L As shown in the cross-sectional view, a metal layer 316 may be formed above and / or on a dielectric layer 314. A deposition tool 102 may use CVD, PVD, ALD, or another type of deposition technique to deposit the material of the metal layer 316, and an electroplating tool 112 may use an electroplating operation, or a combination thereof, to deposit the material of the metal layer 316. A planarization tool 110 may planarize the metal layer 316 after deposition.

[0132] like Figure 4M As shown in the cross-sectional view, portions of the metal layer 316 and the dielectric layer 314 can be removed to form an opening 414 through the metal layer 316 and the dielectric layer 314. The remaining portions of the metal layer 316 and the dielectric layer 314 can form a mesh structure 318. The opening 414 can be formed by coating the metal layer 316 with a photoresist (e.g., using a deposition tool 102); forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using a developer tool 106); and etching through the metal layer 316 to a portion of the dielectric layer 314 and / or through the dielectric layer 314 (e.g., using an etching tool 108) based on the pattern in the photoresist.

[0133] like Figure 4NAs shown in the cross-sectional view, each color filter region 320 of the pixel sensors 302 in the pixel array 300 can be formed in the openings 414 between the grid structures 318. For example, a color filter region 320a can be formed in the opening 414 above the photodiode 306 of pixel sensor 302a, a color filter region 320b can be formed in the opening 414 above the photodiode 306 of pixel sensor 302b, a color filter region 320c can be formed in the opening 414 above the photodiode 306 of pixel sensor 302c, and so on. Each color filter region 320 can be formed between the grid structures 318 to reduce color mixing between adjacent pixel sensors 302. Semiconductor processing tools (e.g., deposition tool 102) can deposit the color filter regions 320 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, or PEALD).

[0134] like Figure 4O As shown in the cross-sectional view, a microlens layer 322 comprising multiple microlenses is formed above and / or on the color filter area 320 and above and / or on the mesh structure 318. The microlens layer 322 may include individual microlenses of each of the pixel sensors 302 included in the pixel array 300. For example, microlenses may be formed above and / or on the color filter area 320a of pixel sensor 302a, microlenses may be formed above and / or on the color filter area 320b of pixel sensor 302b, microlenses may be formed above and / or on the color filter area 320c of pixel sensor 302c, and so on.

[0135] As shown above, Figures 4A to 4O It is provided as an instance. Other instances may differ from those provided. Figures 4A to 4O The description.

[0136] Figure 5 This is a diagram of an example component of device 500. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or wafer / wafer transfer tools 116 may include one or more devices 500 and / or one or more components of device 500. Figure 5 As shown, the device 500 may include a bus 510, a processor 520, a memory 530, a storage component 540, an input component 550, an output component 560, and a communication component 570.

[0137] Bus 510 includes components that enable wired and / or wireless communication between components of device 500. Processor 520 includes a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 520 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 520 includes one or more processors that can be programmed to perform functions. Memory 530 includes random access memory, read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0138] Storage component 540 stores information and / or software related to the operation of device 500. For example, storage component 540 may include a hard disk drive, disk drive, optical disk drive, solid-state drive, optical disk, multi-format digital optical disk, and / or another type of non-transitory computer-readable media. Input component 550 enables device 500 to receive input, such as user input and / or read input. For example, input component 550 may include a touchscreen, keyboard, keypad, mouse, buttons, microphone, switch, sensor, GPS component, accelerometer, gyroscope, and / or actuator. Output component 560 enables device 500 to provide output, such as via a display, speaker, and / or one or more light-emitting diodes. Communication component 570 enables device 500 to communicate with other devices, such as via wired and / or wireless connections. For example, communication component 570 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0139] Device 500 may execute one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 530 and / or storage component 540) may store a set of instructions (e.g., one or more instructions, code, software code, and / or program code) for execution by processor 520. Processor 520 may execute the set of instructions to perform one or more processes described herein. In some embodiments, execution of the set of instructions by one or more processors 520 causes one or more processors 520 and / or device 500 to perform one or more processes described herein. In some embodiments, a fixed-line circuit system may be used in place of or in combination with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of physical hardware circuit systems and software.

[0140] Figure 5 The number and configuration of components shown are provided as examples. Device 500 may include additional components, fewer components, different components, or components with... Figure 5The components shown are configured differently. Additionally or alternatively, a group of components of device 500 (e.g., one or more components) may perform one or more functions described as being performed by another group of components of device 500.

[0141] Figure 6 This is a flowchart of an example process 600 related to the formation of the isolation well. In some implementations, Figure 6 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 6 One or more process blocks may be executed by one or more components of the device 500, such as processor 520, memory 530, storage component 540, input component 550, output component 560, and / or communication component 570.

[0142] like Figure 6 As shown, process 600 may include forming a pattern in a photoresist layer above a substrate, wherein the pattern includes a plurality of trenches (blocks 610) through the photoresist layer. For example, as described above, one or more of the semiconductor processing tools 102-114 may form a pattern 404 in a photoresist layer 402 above a substrate 304. In some embodiments, pattern 404 includes a plurality of trenches through the photoresist layer 402.

[0143] like Figure 6 As shown, process 600 may include performing an anti-hardening operation on the photoresist layer to form a hardened layer on the top surface of the photoresist layer and on the sidewalls of the plurality of trenches (block 620). For example, as described above, one or more of the semiconductor processing tools 102-114 may perform an anti-hardening operation on the photoresist layer 402 to form a hardened layer 406 on the top surface of the photoresist layer 402 and on the sidewalls of the plurality of trenches.

[0144] like Figure 6 As further shown, process 600 may include performing an ion implantation operation after performing an anti-hardening operation to form one or more isolation wells (block 630) in the substrate using a pattern as an implantation mask. For example, as described above, after performing an anti-hardening operation, one or more of the semiconductor processing tools 102-114 may perform an ion implantation operation to form one or more isolation wells (e.g., isolation wells 204 and / or 308) in the substrate 304 using a pattern 404 as an implantation mask 408.

[0145] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0146] In a first embodiment, one or more isolation wells are included in a pixel array (e.g., 200 and / or 300), and the one or more isolation wells provide optical isolation between adjacent pixel sensors (e.g., pixel sensors 202 and / or 302) in the pixel array. In a second embodiment, alone or in combination with the first embodiment, the carbon density of the hardened layer 406 is greater than the carbon density of the photoresist layer 402. In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming a pattern 404 in the photoresist layer 402 includes forming a pattern 404 such that the aspect ratio between the height (H2) and the width (W2) of the plurality of trenches is equal to or less than about 8. In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the formation of the hardened layer 406 increases the aspect ratio to equal to or greater than about 10.

[0147] In a fifth embodiment, individually or in combination with one or more of the first to fourth embodiments, after the hardened layer 406 is formed, the width (W3) of the trenches in the plurality of trenches is in the range of about 180 nanometers to about 230 nanometers. In a sixth embodiment, individually or in combination with one or more of the first to fifth embodiments, before the hardened layer 406 is formed, the width (W2) of the trenches is in the range of about 230 nanometers to about 260 nanometers. In a seventh embodiment, individually or in combination with one or more of the first to sixth embodiments, performing the anti-hardening operation includes performing the anti-hardening operation for a duration of about 30 seconds to about 120 seconds.

[0148] although Figure 6 The example block for process 600 is shown, but in some implementations, process 600 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in other processes. Figure 6 These are the different configurations of the blocks depicted. Alternatively or additionally, two or more blocks in process 600 can be executed in parallel.

[0149] Figure 7 This is a flowchart of example process 700 associated with the formation of the isolation well. In some implementations, Figure 7 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 7 One or more process blocks may be executed by one or more components of the device 500, such as processor 520, memory 530, storage component 540, input component 550, output component 560, and / or communication component 570.

[0150] like Figure 7 As shown, process 700 may include forming a plurality of trenches (block 710) through a photoresist layer above the substrate. For example, as described above, one or more of the semiconductor processing tools 102 to 114 may form a plurality of trenches through a photoresist layer 402 above the substrate 304.

[0151] like Figure 7 As further shown, process 700 may include performing a surface treatment operation on the top surface of the photoresist layer and the sidewalls of the plurality of trenches using a perfluorinated compound (block 720). For example, as described above, one or more of the semiconductor processing tools 102-114 may perform a surface treatment operation on the top surface of the photoresist layer 402 and the sidewalls of the plurality of trenches using a perfluorinated compound. In some embodiments, the perfluorinated compound reacts with the photoresist layer 402 to form a hardened layer 406 on the top surface of the photoresist layer 402 and the sidewalls of the plurality of trenches. In some embodiments, the carbon density of the hardened layer 406 is greater than the carbon density of the photoresist layer 402.

[0152] like Figure 7 As further shown, process 700 may include performing an ion implantation operation after performing a surface treatment operation to form a plurality of isolation wells (block 730) in the substrate using a photoresist layer and a plurality of trenches as implantation masks. For example, after performing a surface treatment operation, one or more of the semiconductor processing tools 102-114 may perform an ion implantation operation to form a plurality of isolation wells (e.g., isolation wells 204 and / or 308) in the substrate 304 using a photoresist layer 402 and a plurality of trenches as implantation masks 408.

[0153] Process 700 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0154] In the first embodiment, the perfluorinated compound includes fluorinated carbon (C60 ... x F y ) or fluorinated hydrocarbons (C x HF y At least one of the following. In the second embodiment, either alone or in combination with the first embodiment, performing a surface treatment operation using a perfluorinated compound includes depositing the perfluorinated compound onto the top surface of the photoresist layer 402 and the sidewalls of the plurality of trenches via a PECVD operation. In the third embodiment, either alone or in combination with one or more of the first and second embodiments, a plurality of isolation wells surround a plurality of pixel sensors (e.g., pixel sensors 202 and / or 302) included in a pixel array (e.g., pixel arrays 200 and / or 300).

[0155] In a fourth embodiment, the perfluorinated compound, alone or in combination with one or more of the first to third embodiments, is locally and partially crosslinked with the photoresist layer 402 to form a hardened layer 406. In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the thickness of the hardened layer 406 is in the range of about 10 nanometers to about 30 nanometers. In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the formation of the hardened layer 406 increases the aspect ratio between the height (H3) and width (W3) of the plurality of trenches to be equal to or greater than about 10.

[0156] although Figure 7 The example block for process 700 is shown, but in some implementations, process 700 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in other processes. Figure 7 These are the different configurations of the blocks depicted. Alternatively or additionally, two or more blocks in process 700 can be executed in parallel.

[0157] Figure 8 This is a flowchart of an example process 800 associated with the formation of the isolation well. In some implementations, Figure 8 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally or alternatively, Figure 8 One or more process blocks may be executed by one or more components of the device 500, such as processor 520, memory 530, storage component 540, input component 550, output component 560, and / or communication component 570.

[0158] As shown in Figure 8, process 800 may include forming a plurality of trenches (block 810) through a photoresist layer above the substrate. For example, as described above, one or more of the semiconductor processing tools 102-114 may form a plurality of trenches through a photoresist layer 402 above the substrate 304. In some embodiments, the aspect ratio between the height (H2) and width (W2) of the plurality of trenches is equal to or less than about 8.

[0159] like Figure 8 As further shown, process 800 may include increasing the aspect ratio of the multiple trenches to about 10 or greater after forming the multiple trenches (block 820). For example, as described above, one or more of the semiconductor processing tools 102-114 may increase the aspect ratio of the multiple trenches to about 10 or greater after forming the multiple trenches.

[0160] like Figure 8As further shown, process 800 may include performing an ion implantation operation after increasing the aspect ratio and using a photoresist layer to form a plurality of isolation wells in the substrate based on a plurality of trenches (block 830). For example, as described above, one or more of the semiconductor processing tools 102-114 may perform an ion implantation operation after increasing the aspect ratio and using a photoresist layer 402 to form a plurality of isolation wells (e.g., isolation wells 204 and / or 308) in the substrate 304 based on a plurality of trenches.

[0161] like Figure 8 As further shown, process 800 may include forming an isolation structure (block 840) in the substrate and over the plurality of isolation wells. For example, as described above, one or more of the semiconductor processing tools 102 to 114 may form an isolation structure 310 in the substrate 304 and over the plurality of isolation wells.

[0162] like Figure 8 As further shown, process 800 may include a plurality of photodiodes (block 850) formed between a plurality of isolation wells and between isolation structures, comprising a plurality of pixel sensors in a pixel array. For example, as described above, one or more of semiconductor processing tools 102-114 may form a plurality of photodiodes 306 comprising a plurality of pixel sensors (e.g., pixel sensors 202 and / or 302) in a pixel array (e.g., pixel array 200 and / or 300) between a plurality of isolation wells and between isolation structures 310.

[0163] like Figure 8 As further shown, process 800 may include forming a plurality of color filter areas (block 860) over a plurality of photodiodes. For example, as described above, one or more of the semiconductor processing tools 102 to 114 may form a plurality of color filter areas 320 over a plurality of photodiodes 306.

[0164] like Figure 8 As further shown, process 800 may include forming a microlens layer (block 870) over a plurality of color filter areas. For example, as described above, one or more of the semiconductor processing tools 102 to 114 may form a microlens layer 322 over a plurality of color filter areas 320.

[0165] Process 800 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0166] In a first embodiment, increasing the aspect ratio of the multiple trenches includes forming a carbon-based shell (e.g., a hardened layer 406) on the sidewalls of the multiple trenches. In a second embodiment, alone or in combination with the first embodiment, the carbon-based shell protects the sidewalls during ion implantation operations. In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the carbon-based shell includes depositing a perfluorinated compound on the sidewalls of the multiple trenches, wherein the perfluorinated compound is crosslinked with the photoresist layer 402 to form the carbon-based shell. In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the thickness (T1) of the carbon-based shell is in the range of about 10 nanometers to about 30 nanometers.

[0167] although Figure 8 The example block for process 800 is shown, but in some implementations, process 800 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in other processes. Figure 8 These are the different configurations of the blocks depicted. Alternatively or concurrently, two or more blocks in process 800 can be executed in parallel.

[0168] In this manner, the implant mask formation technique described herein includes improving the initial aspect ratio of a pattern in the implant mask using non-lithography techniques, which may include forming an anti-hardening layer on the implant mask. The pattern can be formed to an initial aspect ratio using optical lithography techniques, which reduces or minimizes the possibility of pattern collapse during pattern formation. Subsequently, an anti-hardening layer is formed on the implant mask to increase the height of the pattern and decrease its width, thereby increasing the aspect ratio between the height and width of the openings or grooves in the pattern. Thus, the pattern in the implant mask can be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the possibility of pattern collapse during pattern formation.

[0169] As described in more detail above, some embodiments described herein provide a method of manufacturing a semiconductor. The manufacturing method includes forming a pattern in a photoresist layer over a substrate, wherein the pattern includes a plurality of trenches through the photoresist layer. The manufacturing method includes performing an anti-hardening operation on the photoresist layer to form a hardened layer on the top surface of the photoresist layer and on the sidewalls of the plurality of trenches. The manufacturing method includes performing an ion implantation operation after performing the anti-hardening operation to form one or more isolation wells in the substrate using the pattern as an implantation mask. In some embodiments, the one or more isolation wells are included in a pixel array; and wherein the one or more isolation wells provide optical isolation between a plurality of adjacent pixel sensors in the pixel array. In some embodiments, the carbon density of the hardened layer is greater than the carbon density of the photoresist layer. In some embodiments, the step of forming the pattern in the photoresist layer includes the following steps: forming the pattern such that an aspect ratio between a height and a width of the trenches is equal to or less than about 8. In some embodiments, the formation of the hardened layer increases the aspect ratio to equal to or greater than about 10. In some embodiments, after the hardened layer is formed, the width of one of the trenches is in the range of about 180 nanometers to about 230 nanometers. In some embodiments, before the hardened layer is formed, the width of the trench is in the range of about 230 nanometers to about 260 nanometers. In some embodiments, the step of performing the anti-hardening operation includes the following steps: performing the anti-hardening operation for a duration in the range of about 30 seconds to about 120 seconds.

[0170] As described in more detail above, some embodiments described herein provide a method of manufacturing a semiconductor. The manufacturing method includes forming a plurality of trenches through a photoresist layer above a substrate. The manufacturing method includes performing a surface treatment operation on the top surface of the photoresist layer and the sidewalls of the plurality of trenches using a perfluorinated compound, wherein the perfluorinated compound reacts with the photoresist layer to form a hardened layer on the top surface of the photoresist layer and the sidewalls of the plurality of trenches, and wherein the hardened layer has a greater carbon density than the carbon density of the photoresist layer. The manufacturing method includes performing an ion implantation operation after performing the surface treatment operation to form a plurality of isolation wells in the substrate using the photoresist layer and the plurality of trenches as an implantation mask. In some embodiments, the perfluorinated compound comprises at least one of the following: carbon monofluoride (C x F y ), or monofluorinated hydrocarbons (C x HF yIn some embodiments, the step of performing the surface treatment operation using the perfluorinated compound includes the following steps: depositing the perfluorinated compound onto the top surface of the photoresist layer and the sidewalls of the trenches via a plasma-enhanced chemical vapor deposition operation. In some embodiments, the isolation wells surround a plurality of pixel sensors included in a pixel array. In some embodiments, the perfluorinated compound is locally and partially crosslinked with the photoresist layer to form the hardened layer. In some embodiments, the thickness of the hardened layer is in the range of about 10 nanometers to about 30 nanometers. In some embodiments, the formation of the hardened layer increases the aspect ratio between the height and width of the trenches to be equal to or greater than about 10.

[0171] As described in more detail above, some embodiments described herein provide a method of manufacturing a semiconductor. The manufacturing method includes forming a plurality of trenches through a photoresist layer above a substrate, wherein the aspect ratio between the height and width of the plurality of trenches is equal to or less than about 8. The manufacturing method includes increasing the aspect ratio of the plurality of trenches to greater than or equal to about 10 after forming the plurality of trenches. The manufacturing method includes performing an ion implantation operation after increasing the aspect ratio and using the photoresist layer to form a plurality of isolation wells in the substrate based on the plurality of trenches. The manufacturing method includes forming isolation structures in the substrate and above the plurality of isolation wells. The manufacturing method includes forming a plurality of photodiodes, including a plurality of pixel sensors in a pixel array, between the plurality of isolation wells and between the isolation structures. The manufacturing method includes forming a plurality of color filter regions above the plurality of photodiodes. The manufacturing method includes forming a microlens layer above the plurality of color filter regions. In some embodiments, the step of increasing the aspect ratio of the trenches includes the following step: forming a carbon-based shell on a plurality of sidewalls of the trenches. In some embodiments, the carbon-based shell protects the sidewalls during the ion implantation operation. In some embodiments, the step of forming the carbon-based shell includes the following step. A perfluorinated compound is deposited on the sidewalls of the trenches, wherein the perfluorinated compound crosslinks with the photoresist layer to form the carbon-based shell. In some embodiments, the thickness of the carbon-based shell is in the range of about 10 nanometers to about 30 nanometers.

[0172] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor, characterized in that, Includes the following steps: A pattern is formed in a photoresist layer above a substrate, wherein the pattern includes a plurality of trenches passing through the photoresist layer, wherein the aspect ratio between a height of the plurality of trenches and a width of the plurality of trenches is less than 8; An anti-curing operation is performed on the photoresist layer to form a curing layer on a top surface of the photoresist layer and on the sidewalls of the plurality of trenches; and After performing the anti-hardening operation, an ion implantation operation is performed to use the pattern as an implantation mask to form one or more isolation wells in the substrate.

2. The manufacturing method as described in claim 1, characterized in that, The one or more isolation wells are included in a pixel array; and The one or more isolation wells provide optical isolation between multiple adjacent pixel sensors in the pixel array.

3. The manufacturing method as described in claim 1, characterized in that, The carbon density of the hardened layer is greater than that of the photoresist layer.

4. The manufacturing method as described in claim 1, characterized in that, The thickness of the hardened layer is in the range of 10 nanometers to 30 nanometers.

5. The manufacturing method as described in claim 1, characterized in that, The formation of this hardened layer increases the aspect ratio to 10 or greater.

6. The manufacturing method as described in claim 1, characterized in that, After the hardened layer is formed, the width of one of the plurality of trenches is in the range of 180 nanometers to 230 nanometers.

7. The manufacturing method as described in claim 6, characterized in that, Before the hardened layer is formed, the width of the trench is in the range of 230 nanometers to 260 nanometers.

8. The manufacturing method as described in claim 1, characterized in that, The steps for performing this anti-hardening operation include the following: The duration of the anti-hardening operation is within a range of 30 to 120 seconds.

9. A method for manufacturing a semiconductor, characterized in that, Includes the following steps: Multiple trenches are formed through a photoresist layer above a substrate, wherein the aspect ratio between a height and a width of the multiple trenches is less than 8; A surface treatment operation is performed on a top surface of the photoresist layer and on a plurality of sidewalls of the plurality of trenches using a perfluorinated compound, wherein the perfluorinated compound reacts with the photoresist layer to form a hardened layer on the top surface of the photoresist layer and on a plurality of sidewalls of the plurality of trenches, and wherein the carbon density of the hardened layer is greater than that of the carbon density of the photoresist layer. and After performing the surface treatment operation, an ion implantation operation is performed to form multiple isolation wells in the substrate using the photoresist layer and the plurality of trenches as an implantation mask.

10. The manufacturing method as described in claim 9, characterized in that, The perfluorinated compound contains at least one of the following: Carbon monofluoride (CF x F y ), or monofluorinated hydrocarbon (C x HF y ).

11. The manufacturing method as described in claim 9, characterized in that, The steps for performing this surface treatment using a perfluorinated compound include the following: The perfluorinated compound is deposited onto the top surface of the photoresist layer and the sidewalls of the plurality of trenches via a plasma-enhanced chemical vapor deposition operation.

12. The manufacturing method as described in claim 9, characterized in that, The plurality of isolation wells surround a plurality of pixel sensors included in a pixel array.

13. The manufacturing method as described in claim 9, characterized in that, The perfluorinated compound is locally and partially crosslinked with the photoresist layer to form the hardened layer.

14. The manufacturing method as described in claim 9, characterized in that, The thickness of the hardened layer is in the range of 10 nanometers to 30 nanometers.

15. The manufacturing method as described in claim 9, characterized in that, The formation of the hardened layer increases the aspect ratio between the height and width of the plurality of trenches to 10 or greater.

16. A method for manufacturing a semiconductor, characterized in that, Includes the following steps: Multiple trenches are formed through a photoresist layer above a substrate, wherein the aspect ratio between a height and a width of the multiple trenches is less than 8; After the plurality of trenches are formed, the aspect ratio of the plurality of trenches is increased to be equal to or greater than 10; After increasing the aspect ratio and using the photoresist layer, an ion implantation operation is performed to form multiple isolation wells in the substrate based on the multiple trenches; An isolation structure is formed in the substrate and above the plurality of isolation wells; Multiple photodiodes, including multiple pixel sensors in a pixel array, are formed between the multiple isolation wells and between the isolation structures. Multiple color filter areas are formed above the plurality of photodiodes; and A microlens layer is formed above the plurality of color filter areas.

17. The manufacturing method as described in claim 16, characterized in that, The step of increasing the aspect ratio of the plurality of trenches includes the following steps: A carbon-based shell is formed on multiple sidewalls of the multiple trenches.

18. The manufacturing method as described in claim 17, characterized in that, The carbon-based shell protects the multiple sidewalls during the ion implantation operation.

19. The manufacturing method as described in claim 17, characterized in that, The process of forming the carbon-based shell includes the following steps: A perfluorinated compound is deposited on the sidewalls of the plurality of trenches, wherein the perfluorinated compound crosslinks with the photoresist layer to form the carbon-based shell.

20. The manufacturing method as described in claim 17, characterized in that, The thickness of the carbon-based shell is in the range of 10 nanometers to 30 nanometers.

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