Drive device

Abstract

A driving device includes a substrate, a first metal line, and a second metal line. The first metal line is located in a first metal layer and is coupled to a transistor and a capacitor. The second metal line is located in a second metal layer and is used to receive a reference signal, wherein the first metal line and the second metal line overlap in a direction perpendicular to the plane of the driving device.

Description

Technical Field

[0001] The present disclosure relates to a driving device, and particularly to a driving circuit applied to a light-emitting diode display. Background Art

[0002] In the driving circuit of a common light-emitting diode display nowadays, in terms of pixel design, there is an easy presence of parasitic capacitance between the gate terminal of the driving transistor and the metal layer receiving the data signal. When the voltage of the data signal changes, the voltage change is easily coupled to the gate terminal of the driving transistor through the parasitic capacitance, thereby affecting the brightness of the panel. Summary of the Invention

[0003] The Summary of the Invention aims to provide a simplified summary of the present disclosure to enable readers to have a basic understanding of the present disclosure. This Summary of the Invention is not a complete overview of the present disclosure, and its intention is not to point out the important / critical elements of the embodiments of the present disclosure or to define the scope of the present disclosure.

[0004] One technical embodiment of the present disclosure relates to a driving device, which includes a substrate, a first metal wire, and a second metal wire. The first metal wire is located in a first metal layer and is coupled to a transistor and a capacitor. The second metal wire is located in a second metal layer and is used to receive a reference signal, wherein the first metal wire and the second metal wire overlap in a direction perpendicular to the plane of the driving device.

[0005] Therefore, according to the technical content of the present disclosure, the driving device shown in the embodiments of the present disclosure can reduce the influence of the parasitic capacitance between metal layers on the driving transistor, so as to achieve the effect of stable brightness of the panel.

[0006] After referring to the following embodiments, those skilled in the art to which the present disclosure pertains can easily understand the basic concept and other inventive purposes of the present disclosure, as well as the technical means and embodiments adopted by the present disclosure. Brief Description of the Drawings

[0007] To make the above and other purposes, features, advantages, and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows:

[0008] Figure 1 is a detailed circuit diagram showing a driving device according to an embodiment of the present disclosure.

[0009] Figure 2 is a detailed circuit diagram showing a driving device according to an embodiment of the present disclosure.

[0010] Figure 3 is a top view of the structure of a driving device as shown in Figure 2 according to an embodiment of the present disclosure.

[0011] Figure 4 FIG. Figure 4 is a top view showing the structure of a driving device according to an embodiment of the present disclosure.

[0012] Figure 5 FIG. is a top view showing the structure of a driving device according to an embodiment of the present disclosure.

[0013] In accordance with the usual operation mode, various features and elements in the figures are not drawn to scale, and they are drawn in a way to best present the specific features and elements related to the present disclosure. In addition, the same or similar element symbols are used to refer to similar elements / components in different drawings.

[0014] Description of reference numerals:

[0015] 100, 100A, 300, 400, 500: Driving device

[0016] 310, 410, 510: Substrate

[0017] 320, 420, 520: First metal wire

[0018] 330, 430, 540: Second metal wire

[0019] 340, 440, 550: Third metal wire

[0020] 530: First insulating layer

[0021] Vdata: Data signal

[0022] Vref: Reference signal

[0023] EM, AT, CS, RS, WS, VDD: Signals

[0024] T1~T8: Transistors

[0025] C1, C2: Capacitors

[0026] Cgd: Parasitic capacitance

[0027] Cx: Parasitic capacitance

[0028] T1_G: Gate terminal

[0029] Q1: Node

[0030] V1, V2: Through holes Detailed implementation manners

[0031] To make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the embodiments and specific examples of the present disclosure; however, this is not the only form for implementing or applying the specific examples of the present disclosure. The embodiments cover the features of multiple specific examples and the method steps and their sequences for constructing and operating these specific examples. However, the same or equivalent functions and step sequences can also be achieved using other specific examples.

[0032] Unless otherwise defined in this specification, the meanings of the scientific and technical terms used herein are the same as those understood and commonly used by those skilled in the technical field to which the present disclosure pertains. In addition, in the case of not conflicting with the context, the singular nouns used in this specification cover the plural forms of the nouns; and when the plural nouns are used, they also cover the singular forms of the nouns.

[0033] In addition, regarding the "coupled" used herein, it may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, and may also refer to two or more elements operating or acting on each other.

[0034] Figure 1 is a detailed circuit diagram showing a driving device according to an embodiment of the present disclosure. As shown in the figure, in the driving device 100 disclosed in an embodiment of the present disclosure, the parasitic capacitance Cgd is coupled to the gate terminal T1_G of the driving transistor T1, and the parasitic capacitance Cgd couples the data signal Vdata to the gate terminal T1_G of the driving transistor T1. For example, the data signal Vdata can be a variable voltage source. However, the voltage difference by which the data signal Vdata varies will also be coupled to the gate terminal T1_G of the driving transistor T1 through the parasitic capacitance Cgd, resulting in an unstable voltage received at the gate terminal T1_G, but the present disclosure is not limited thereto.

[0035] Figure 2 is a detailed circuit diagram showing a driving device according to an embodiment of the present disclosure. As shown in the figure, in the driving device 100A disclosed in an embodiment of the present disclosure, the parasitic capacitance Cx is coupled to the gate terminal T1_G of the driving transistor T1, and the parasitic capacitance Cx is used to couple the reference signal Vref to the gate terminal T1_G of the driving transistor T1. For example, the reference signal Vref can be a stable voltage source or grounded. Therefore, the reference signal Vref has no varying voltage difference, so the voltage coupled to the gate terminal T1_G of the driving transistor T1 through the parasitic capacitance Cx is a stable voltage, but the present disclosure is not limited thereto.

[0036] Figure 3 is shown according to an embodiment of the present disclosure as Figure 2Top view of the structure of the driving device shown. As shown in the figure, the driving device 300 includes a substrate 310, a first metal wire 320, and a second metal wire 330. In terms of the connection relationship, the first metal wire 320 is located in the first metal layer and is coupled to the transistor T1 and the capacitor C1. The second metal wire 330 is located in the second metal layer, and the first metal wire 320 and the second metal wire 330 overlap in a direction perpendicular to the plane of the driving device 300 (e.g., the XY plane) (e.g., the Z direction perpendicular to the XY plane).

[0037] For example, the substrate 310 can be any semiconductor, such as amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low temperature poly-silicon (LTPS), but the present disclosure is not limited thereto.

[0038] To reduce the influence of the parasitic capacitance between metal layers on the driving transistor to achieve stable brightness of the panel, the present disclosure provides the following detailed description of the related operations of the driving device 300 shown Figure 3 as follows.

[0039] Please refer to Figure 2 and Figure 3 together. In one embodiment, the second metal wire 330 is used to receive the reference signal Vref. For example, the reference signal Vref can be a stable voltage or ground, so there is no changing voltage difference in the reference signal Vref. Therefore, the voltage coupled to the gate terminal T1_G of the driving transistor T1 via the parasitic capacitance Cx is a stable voltage, but the present disclosure is not limited thereto.

[0040] Please refer to Figure 3 . In one embodiment, the first metal wire 320 and the second metal wire 330 partially overlap in a direction perpendicular to the plane of the driving device 300.

[0041] Please refer to Figure 2 and Figure 3 together. In one embodiment, the driving device 300 further includes a third metal wire 340. The third metal wire 340 is located in the second metal layer and is used to receive the data signal Vdata. The data signal Vdata is transmitted to the capacitor C1 via the third metal wire 340, and the data signal Vdata is coupled to the transistor T1 via the capacitor C1.

[0042] In one embodiment, the third metal wire 340 and the second metal wire 330 do not overlap in a direction perpendicular to the plane of the driving device 300.

[0043] In one embodiment, the second metal line 330 is parallel to the third metal line 340 and spaced apart by a distance.

[0044] Please refer to Figure 3 , in one embodiment, the driving device 300 includes a substrate 310, a first metal layer where the first metal line 320 is located, a first insulating layer (not shown in the figure), a via hole V2, a second metal layer where the second metal line 330 is located, and a second insulating layer (not shown in the figure). In terms of the connection relationship, the first metal layer is located above the substrate 310, the first insulating layer is stacked above the first metal layer, the second metal layer is coupled to the first metal layer through the via hole V2 penetrating the first insulating layer, and the second insulating layer is stacked above the second metal layer.

[0045] Figure 4 FIG. is a top view showing the structure of a driving device according to an embodiment of the present disclosure. As shown in the figure, the driving device 400 includes a substrate 410, a first metal line 420, and a second metal line 430. In terms of the connection relationship, the first metal line 420 is located in the first metal layer and is coupled to the transistor T1 and the capacitor C1. The second metal line 430 is located in the second metal layer, and the first metal line 420 and the second metal line 430 do not overlap in a direction perpendicular to the plane of the driving device 400 (e.g., the XY plane) (e.g., the Z direction perpendicular to the XY plane).

[0046] For example, the substrate 410 can be any semiconductor, such as amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low temperature poly-silicon (LTPS), but the present disclosure is not limited thereto.

[0047] In operation, in one embodiment, the second metal line 430 is used to receive a data signal Vdata. For example, the data signal Vdata can be a variable voltage source. However, since the first metal line 420 and the second metal line 430 do not overlap in a direction perpendicular to the plane of the driving device 400, the parasitic capacitance between the first metal line 420 and the second metal line 430 is very small. Therefore, the voltage difference change of the data signal Vdata will not be coupled to the gate terminal T1_G of the transistor T1 through the parasitic capacitance, but the present disclosure is not limited thereto.

[0048] Please refer to together Figure 1 and Figure 4 , in one embodiment, the data signal Vdata is transmitted to the capacitor C1 via the second metal line 430, and the data signal Vdata is coupled to the transistor T1 via the capacitor C1.

[0049] Please refer to Figure 4, in one embodiment, the driving device 400 further includes a third metal line 440 located in the second metal layer for receiving a reference signal Vref, and the shape of the third metal line 440 is the same as that of the second metal line 430. For example, the shape of the second metal line 430 can be a bent trace design, and the shape of the third metal line 340 can also be the same as that of the second metal line 430, which is also a bent trace design. Through the bent trace design of the second metal line 430, the first metal line 420 and the second metal line 430 can be made not to overlap in the direction perpendicular to the plane of the driving device 400, but the present disclosure is not limited thereto.

[0050] In one embodiment, the driving device 400 includes a substrate 410, a first metal layer where the first metal line 420 is located, a first insulating layer (not shown in the figure), a via hole V2, a second metal layer where the second metal line 430 is located, and a second insulating layer (not shown in the figure). In terms of the connection relationship, the first metal layer is located above the substrate 410, the first insulating layer is stacked above the first metal layer, the second metal layer is coupled to the first metal layer through the via hole V2 penetrating the first insulating layer, and the second insulating layer is stacked above the second metal layer.

[0051] For example, the first metal line 420 can be located in the first metal layer and coupled to the transistor T1 and the capacitor C1. The second metal line 430 can be located in the second metal layer, and the first metal line 420 and the second metal line 430 do not overlap in the direction perpendicular to the plane of the driving device 400, but the present disclosure is not limited thereto.

[0052] Figure 5 is a top view showing the structure of a driving device according to an embodiment of the present disclosure. As shown in the figure, the driving device 500 includes a substrate 510, a first metal line 520, a first insulating layer 530, and a second metal line 540. In terms of the connection relationship, the first metal line 520 is located in the first metal layer and coupled to the transistor T1 and the capacitor C1. The first insulating layer 530 is disposed on the first metal layer, and the second metal line 540 is located in the second metal layer and disposed on the first insulating layer 530, and the first metal line 520, the first insulating layer 530, and the second metal line 540 overlap in the direction perpendicular to the plane of the driving device 400 (for example, the XY plane) (for example, the Z direction perpendicular to the XY plane). In one embodiment, the first insulating layer 530 is disposed between the first metal line 520 and the second metal line 540, and the present disclosure can isolate the electrical relationship between the first metal line 520 and the second metal line 540 through the first insulating layer 530, so that the parasitic capacitance between the first metal line 520 and the second metal line 540 becomes smaller.

[0053] For example, the substrate 510 can be any semiconductor, such as amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low temperature poly-silicon (LTPS), but the present disclosure is not limited thereto.

[0054] In operation, in one embodiment, the second metal line 540 is used to receive the data signal Vdata. For example, the data signal Vdata can be a variable voltage source, and the first insulating layer 530 can be a thickened insulating layer. Since the thickened insulating layer 530 between the first metal line 520 and the second metal line 540 can increase the distance between the first metal line 520 and the second metal line 540, the parasitic capacitance between the first metal line 520 and the second metal line 540 is very small. Therefore, the voltage difference changed by the data signal Vdata will not be coupled to the gate terminal T1_G of the transistor T1 through the parasitic capacitance, but the present disclosure is not limited thereto.

[0055] Please refer to Figure 2 and Figure 5 , in one embodiment, the data signal Vdata is transmitted to the capacitor C1 via the second metal line 540, and the data signal Vdata is coupled to the transistor T1 via the capacitor C1.

[0056] Please refer to Figure 5 , in one embodiment, the driving device 500 includes a substrate 510, a first metal layer where the first metal line 520 is located, a first insulating layer 530, a via hole V2, a second metal layer where the second metal line 540 is located, and a second insulating layer (not shown in the figure). In terms of the connection relationship, the first metal layer is located above the substrate, the first insulating layer 530 is stacked above the first metal layer, the second metal layer is coupled to the first metal layer through the via hole V2 penetrating the first insulating layer, and the second insulating layer is stacked above the second metal layer.

[0057] For example, the first metal line 520 can be located in the first metal layer and coupled to the transistor T1 and the capacitor C1, the second metal line 540 can be located in the second metal layer, and the first metal line 520, the first insulating layer 530, and the second metal line 540 overlap in the direction perpendicular to the plane of the driving device, but the present disclosure is not limited thereto.

[0058] As can be seen from the above embodiments of the present disclosure, applying the present disclosure has the following advantages. The driving device shown in the embodiments of the present disclosure can reduce the influence of the parasitic capacitance between metal layers on the driving transistor, so as to achieve the effect of stable brightness of the panel.

[0059] Although specific embodiments of the present disclosure are disclosed in the above embodiments, they are not intended to limit the present disclosure. Please note that in the foregoing drawings, the shapes, sizes, proportions, etc. of the elements are only for illustration and are provided for those skilled in the technical field to which the present disclosure belongs to understand the present disclosure, and are not intended to limit the present disclosure. Those skilled in the technical field to which the present disclosure belongs can make various changes and modifications without departing from the principles and concepts of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the appended claims.

Claims

1. A driving device, comprising: A substrate; A first metal wire, located in a first metal layer, and coupled to a transistor and a capacitor; and A second metal wire, located in a second metal layer, and configured to receive a reference signal, wherein the first metal wire and the second metal wire overlap in a direction perpendicular to a plane of the driving device, wherein the second metal wire has a first length in a first direction of the plane and a second length less than the first length in a second direction of the plane, the first direction being perpendicular to the second direction, the first metal wire has a first side overlapping the second metal wire in the direction perpendicular to the plane, and a length of the first side in the first direction is greater than a length of the transistor in the first direction.

2. The driving device according to claim 1, wherein the first metal wire and the second metal wire partially overlap in the direction perpendicular to the plane of the driving device.

3. The driving device according to claim 1, further comprising: A third metal wire, located in the second metal layer, and configured to receive a data signal, and the data signal is transmitted to the capacitor via the third metal wire, and the data signal is coupled to the transistor via the capacitor.

4. The driving device according to claim 3, wherein the third metal wire and the second metal wire do not overlap in the direction perpendicular to the plane of the driving device.

5. The driving device according to claim 4, wherein the first metal wire and the third metal wire are parallel and separated by a distance.

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