Display device

Abstract

A display device according to one embodiment comprises: a first insulating layer arranged on an insulating substrate; a lower electrode arranged on the above-mentioned first insulating layer; a second insulating layer arranged on the above-mentioned first insulating layer, having an opening portion overlapping with the above-mentioned lower electrode and formed in a lattice shape; a power supply line arranged on the above-mentioned second insulating layer, having a first wiring portion extending in a first direction, a second wiring portion extending in a second direction intersecting the above-mentioned first direction, and a third wiring portion respectively connected to the above-mentioned first wiring portion and the above-mentioned second wiring portion and having a width different from the width of each of the above-mentioned first wiring portion and the above-mentioned second wiring portion; an organic layer including a light-emitting layer, arranged in the above-mentioned opening portion, and covering the above-mentioned lower electrode; and an upper electrode respectively connected to the above-mentioned first wiring portion, the above-mentioned second wiring portion, and the above-mentioned third wiring portion, and covering the above-mentioned organic layer.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-217104 filed on December 25, 2020, the entire contents of which are incorporated by reference. Technical Field

[0002] The present invention relates to a display device. Background Art

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. Display elements have an organic layer between a pixel electrode and a common electrode. In addition to a light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer. Such organic layers are formed, for example, by vacuum evaporation.

[0004] For example, in masked evaporation, a fine mask with openings corresponding to each pixel is used. However, due to the processing accuracy of the fine mask and the deformation of the opening shape, the formation accuracy of the thin film formed by evaporation may decrease. Therefore, it is desirable to form an organic layer of a desired shape without using a fine mask.

[0005] In one example, a technique is known in which an organic layer and a cathode (second electrode) are divided using a pixel division structure. In such a technique, in order to supply a predetermined potential to the divided cathode, the cathode must be reliably electrically connected to a power supply wiring. Summary of the Invention

[0006] An object of the present invention is to provide a display device capable of supplying a predetermined potential to an upper electrode of a display element.

[0007] A display device according to one embodiment includes:

[0008] An insulating substrate; a first insulating layer arranged on the insulating substrate; a lower electrode arranged on the first insulating layer; a second insulating layer arranged on the first insulating layer, having an opening overlapping with the lower electrode and formed in a lattice shape; a power supply line arranged on the second insulating layer, having a first wiring portion extending in a first direction, a second wiring portion extending in a second direction intersecting the first direction, and a third wiring portion respectively connected to the first wiring portion and the second wiring portion and having a width different from that of the first wiring portion and the second wiring portion; an organic layer including a light-emitting layer, arranged in the opening, covering the lower electrode; and an upper electrode respectively connected to the first wiring portion, the second wiring portion, and the third wiring portion, covering the organic layer.

[0009] According to one embodiment, a display device capable of supplying a predetermined potential to an upper electrode of a display element can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram showing a configuration example of a display device DSP according to an embodiment.

[0011] Figure 2 Yes Figure 1 A plan view of an example of a pixel PX shown.

[0012] Figure 3 It is along Figure 2 The cross-sectional view along line A-B is shown.

[0013] Figure 4 It means composition Figure 3 A plan view of an example of the second layer 32 of the partition wall 30 is shown.

[0014] Figure 5 Is to express Figure 2 A plan view of an example of a partition wall 30 on which the feed line FL is overlapped is shown.

[0015] Figure 6 Yes Figure 1 A plan view of another example of a pixel PX is shown.

[0016] Figure 7 It is a plan view showing another example of the second layer 32 constituting the partition wall 30 .

[0017] Figure 8 It is a plan view showing another example of the second layer 32 constituting the partition wall 30 .

[0018] Figure 9 Is to express Figure 6 A plan view of an example of a partition wall 30 on which the feed line FL is overlapped is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0020] Furthermore, the disclosure is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art within the scope of the invention are naturally within the scope of the present invention. Furthermore, the drawings may schematically illustrate the width, thickness, shape, etc. of various components, as compared to actual configurations, for the sake of clarity. However, these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and the drawings, components that perform the same or similar functions as those described in the preceding drawings may be denoted by the same reference numerals, and repeated detailed descriptions may be omitted as appropriate.

[0021] In the drawings, the X-axis, Y-axis, and Z-axis are shown as mutually orthogonal, as necessary, to facilitate understanding. The direction along the X-axis is referred to as the X-direction or the first direction, the direction along the Y-axis is referred to as the Y-direction or the second direction, and the direction along the Z-axis is referred to as the Z-direction or the third direction. The plane defined by the X-axis and the Y-axis is referred to as the X-Y plane, and the plane defined by the X-axis and the Z-axis is referred to as the X-Z plane. A view observing the X-Y plane is referred to as a plan view.

[0022] The display device DSP of this embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and is installed in televisions, computers, portable terminals, mobile phones, etc. In addition, the display element described below can be used as a light-emitting element in a lighting device, and the display device DSP can also be used in other electronic devices such as lighting devices.

[0023] Figure 1 1 is a diagram showing an example configuration of a display device DSP according to this embodiment. The display device DSP includes a display portion DA for displaying images on an insulating base 10. The base 10 is an insulating substrate and may be glass or a flexible resin film.

[0024] The display unit DA includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP1, SP2, and SP3. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Furthermore, in addition to the three sub-pixels described above, the pixel PX may also include four or more sub-pixels, including sub-pixels of other colors such as white.

[0025] A configuration example of one sub-pixel SP included in the pixel PX will be briefly described.

[0026] That is, the sub-pixel SP includes a pixel circuit 1 and a display element 20 driven and controlled by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0027] Regarding the pixel switch 2, the gate electrode is connected to the scanning line GL, the source electrode is connected to the signal line SL, and the drain electrode is connected to one electrode constituting the capacitor 4 and the gate electrode of the driving transistor 3. Regarding the driving transistor 3, the source electrode is connected to the other electrode constituting the capacitor 4 and the power supply line PL, and the drain electrode is connected to the anode of the display element 20. The cathode of the display element 20 is connected to the power supply line FL. The structure of the pixel circuit 1 is not limited to the example shown in the figure.

[0028] The display element 20 is an organic light-emitting diode (OLED) serving as a light-emitting element. For example, sub-pixel SP1 includes a display element that emits light corresponding to a red wavelength, sub-pixel SP2 includes a display element that emits light corresponding to a green wavelength, and sub-pixel SP3 includes a display element that emits light corresponding to a blue wavelength. A pixel PX includes multiple sub-pixels SP1, SP2, and SP3 that display different colors, enabling multi-color display.

[0029] However, the display elements 20 of the sub-pixels SP1 , SP2 , and SP3 may be configured to emit light of the same color. This enables monochrome display.

[0030] Furthermore, when the display element 20 of each of the sub-pixels SP1, SP2, and SP3 emits white light, a color filter may be provided facing the display element 20. For example, the sub-pixel SP1 may include a red filter facing the display element 20, the sub-pixel SP2 may include a green filter facing the display element 20, and the sub-pixel SP3 may include a blue filter facing the display element 20. This enables multi-color display.

[0031] Alternatively, when the display element 20 of each of the sub-pixels SP1 , SP2 , and SP3 emits ultraviolet light, multi-color display can be achieved by arranging a light conversion layer facing the display element 20 .

[0032] The structure of the display element 20 will be described later.

[0033] Figure 2 Yes Figure 1 A plan view of an example of a pixel PX shown.

[0034] The sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are each formed into a substantially rectangular shape extending in the second direction Y and are arranged in the first direction X. The outer shape of each sub-pixel corresponds to the outer shape of the light-emitting area EA of the display element 20, but this is simplified and does not necessarily reflect the actual shape. Here, it is assumed that the light-emitting area EA is formed into a rectangle with short sides extending in the first direction X and long sides extending in the second direction Y.

[0035] The insulating layer 12, described in detail later, is formed in a lattice pattern extending in the first direction X and the second direction Y in plan view, surrounding each of the sub-pixels SP1, SP2, and SP3, or the display element 20 of each sub-pixel. This insulating layer 12 is sometimes referred to as a rib, a partition wall, or a bank. The insulating layer 12 has a plurality of openings OP, including openings OP1 and OP2. The light-emitting area EA is formed in the openings OP of the insulating layer 12. Details of the light-emitting area EA will be described later.

[0036] The feed line FL is arranged on the upper surface U1 of the insulating layer 12. The feed line FL includes a first wiring portion FL1, a second wiring portion FL2, and a third wiring portion FL3. These first wiring portion FL1, second wiring portion FL2, and third wiring portion FL3 are formed integrally or continuously.

[0037] The first wiring portion FL1 extends in the first direction X and has a constant width W1 along the second direction Y. These first wiring portions FL1 are arranged on portions of the grid-shaped upper surface U1 that extend in the first direction X. For each sub-pixel, a pair of first wiring portions FL1 are arranged to face each other, sandwiching the light-emitting area EA.

[0038] The second wiring portion FL2 extends in the second direction Y and has a constant width W2 along the first direction X. This second wiring portion FL2 is arranged on the portion of the grid-shaped upper surface U1 that extends in the second direction Y. For each sub-pixel, a pair of second wiring portions FL2 are arranged to face each other, sandwiching the light-emitting area EA.

[0039] The third wiring portion FL3 is connected to each of the first wiring portion FL1 and the second wiring portion FL2. These third wiring portions FL3 are arranged at the intersections of the grid-shaped upper surface U1. For each sub-pixel, four third wiring portions FL3 are arranged facing each other at the four corners of the light-emitting area EA.

[0040] In other words, the first wiring portion FL1 is arranged between two third wiring portions FL3 arranged in the first direction X at a distance therebetween, and the second wiring portion FL2 is arranged between two third wiring portions FL3 arranged in the second direction Y at a distance therebetween.

[0041] The third wiring portion FL3 has a width different from the width W1 of the first wiring portion FL1 and the width W2 of the second wiring portion FL2 . Figure 2 In the example shown, the third wiring portion FL3 is formed into a substantially quadrilateral having a width WX along the first direction X and a width WY along the second direction Y. The width WY is larger than the width W1 (WY>W1). The width WX is larger than the width W2 (WX>W2).

[0042] As indicated by the dashed line, the upper electrode E2 of the display element 20 overlaps not only with the light-emitting area EA but also with the insulating layer 12 between the light-emitting area EA and the power supply line FL. Furthermore, the upper electrode E2 is in contact with the first wiring portion FL1, the second wiring portion FL2, and the third wiring portion FL3. Thus, a predetermined potential is supplied to the upper electrode E2 from the power supply line FL.

[0043] Figure 3 It is along Figure 2 The cross-sectional view along line A-B is shown.

[0044] Here, attention is focused on two display elements adjacent to each other in the first direction X. For convenience, the display element located on the left side of the drawing is referred to as display element 21 , and the display element located on the right side of the drawing is referred to as display element 22 .

[0045] The display element 21 includes a lower electrode (first lower electrode) E11 , an organic layer (first organic layer) OR1 , and an upper electrode (first upper electrode) E21 .

[0046] The display element 22 includes a lower electrode (second lower electrode) E12 , an organic layer (second organic layer) OR2 , and an upper electrode (second upper electrode) E22 .

[0047] Figure 1 The pixel circuit 1 shown is arranged on a substrate 10 and covered by an insulating layer 11. Figure 3 , only the driving transistor 3 included in the pixel circuit 1 is simplified. The insulating layer (first insulating layer) 11 corresponds to the base layer of the display elements 21 and 22. The insulating layer (second insulating layer) 12 is arranged on the insulating layer 11. The insulating layers 11 and 12 are, for example, organic insulating layers.

[0048] The lower electrodes E11 and E12 are arranged on the insulating layer 11 and spaced apart in the first direction X. The lower electrodes E11 and E12 are each arranged for each sub-pixel or each display element and are electrically connected to the driving transistor 3. Such lower electrodes E11 and E12 are sometimes referred to as pixel electrodes, anodes, etc.

[0049] The lower electrodes E11 and E12 are transparent electrodes formed of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the lower electrodes E11 and E12 may be metal electrodes formed of a metal material such as silver or aluminum. Furthermore, the lower electrodes E11 and E12 may be a stack of transparent electrodes and metal electrodes. For example, the lower electrodes E11 and E12 may be a stack of a transparent electrode, a metal electrode, and a transparent electrode stacked in that order, or may be a stack of three or more layers.

[0050] The insulating layer 12 is disposed between the lower electrode E11 and the lower electrode E12 . The insulating layer 12 has an opening OP1 , an opening OP2 , inclined surfaces S1 and S2 , and an upper surface U1 .

[0051] The opening OP1 is formed in a region overlapping with the lower electrode E11 and is a through hole that penetrates the insulating layer 12 to the lower electrode E11. The peripheral portion of the lower electrode E11 is covered by the insulating layer 12, and the central portion of the lower electrode E11 is exposed from the insulating layer 12 at the opening OP1.

[0052] The opening OP2 is formed in a region overlapping with the lower electrode E12 and is a through hole that penetrates the insulating layer 12 to the lower electrode E12. The peripheral portion of the lower electrode E12 is covered by the insulating layer 12, and the central portion of the lower electrode E12 is exposed from the insulating layer 12 at the opening OP2.

[0053] Upper surface U1 and inclined surfaces S1 and S2 correspond to the surface between opening OP1 and opening OP2 in insulating layer 12. Inclined surface S1 faces opening OP1. Inclined surface S2 faces opening OP2. Upper surface U1 is located between inclined surfaces S1 and S2. While upper surface U1 and inclined surfaces S1 and S2 are, for example, flat surfaces, they may also be curved surfaces.

[0054] The organic layer OR1 includes a light emitting layer EL1. The organic layer OR1 is arranged in the opening OP1 and covers the lower electrode E11. Figure 3 In the example shown, the organic layer OR1 is disposed on the inclined surface S1 and also disposed on a portion of the upper surface U1 , but is separated from the power supply line FL.

[0055] The organic layer OR2 includes a light-emitting layer EL2 . The light-emitting layer EL2 may be formed of the same material as the light-emitting layer EL1 (the organic layers OR1 and OR2 emit the same luminous color) or a different material (the organic layers OR1 and OR2 emit different luminous colors).

[0056] The organic layer OR2 is disposed in the opening OP2 to cover the lower electrode E12. Figure 3 In the example shown, the organic layer OR2 is disposed on the inclined surface S2 and also on a portion of the upper surface U1, but is separated from the power supply line FL. On the upper surface U1, the organic layer OR2 is separated from the organic layer OR1. The power supply line FL is located between the organic layers OR1 and OR2 on the upper surface U1.

[0057] Furthermore, the organic layers OR1 and OR2 may further include various functional layers, such as a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, an electron blocking layer, or other functional layers.

[0058] The upper electrode E21 is stacked on the organic layer OR1, covering the entire organic layer OR1, including its peripheral edge. Furthermore, the upper electrode E21 is in contact with the power supply line FL on the upper surface U1. The portion of the organic layer OR1 located between the lower electrode E11 and the upper electrode E21, without the insulating layer 12 intervening, can form the light-emitting region of the display element 21. The portion of the organic layer OR1 located between the inclined surface S1 and the upper surface U1, because it is located between the insulating layer 12 and the upper electrode E21, emits little light.

[0059] The upper electrode E22 is laminated on the organic layer OR2, covering the entire organic layer OR2, including its peripheral portion. Furthermore, the upper electrode E22 is connected to the power supply line FL on the upper surface U1. The upper electrode E22 is separated from the upper electrode E21. The portion of the organic layer OR2 located between the lower electrode E12 and the upper electrode E22, without the insulating layer 12 intervening, can form the light-emitting region of the display element 22. The portion of the organic layer OR2 located between the inclined surface S2 and the upper surface U1, because it is located between the insulating layer 12 and the upper electrode E22, emits little light.

[0060] These upper electrodes E21 and E22 are arranged for each sub-pixel or each display element, but are electrically connected to each other because they are connected to the power supply line FL. Such upper electrodes E21 and E22 are sometimes called common electrodes, counter electrodes, cathodes, etc.

[0061] The upper electrodes E21 and E22 are semi-transparent metal electrodes formed from a metal material such as magnesium or silver. Alternatively, the upper electrodes E21 and E22 may be transparent electrodes formed from a transparent conductive material such as ITO or IZO. Furthermore, the upper electrodes E21 and E22 may be a laminate of a transparent electrode and a metal electrode.

[0062] The partition wall 30 is located between the display element 21 and the display element 22 and is disposed on the insulating layer 12. Figure 3 In the example shown, the partition wall 30 is arranged on the power supply line FL. More specifically, the partition wall 30 includes a first layer 31 and a second layer 32.

[0063] The first layer 31 is connected to the power supply line FL and is arranged between the organic layer OR1 and the organic layer OR2 and between the upper electrode E21 and the upper electrode E22. The first layer 31 has a side surface S11 facing the opening OP1, a side surface S12 facing the opening OP2, and an upper surface U11 between the side surface S11 and the side surface S12. The first layer 31 exposes the area of ​​the power supply line FL facing the opening OP1 and the area facing the opening OP2. In other words, the power supply line FL extends between the side surface S11 and the organic layer OR1 and is connected to the upper electrode E21. In addition, the power supply line FL extends between the side surface S12 and the organic layer OR2 and is connected to the upper electrode E22. Such a first layer 31 can be a conductor or an insulator.

[0064] The second layer 32 is in contact with the upper surface U11. The second layer 32 extends from the side surface S11 toward the opening OP1 and further extends from the side surface S12 toward the opening OP2. The second layer 32 can be a conductor or an insulator. Furthermore, the second layer 32 can be formed of a different material from the first layer 31 or the same material as the first layer 31.

[0065] Such partition walls 30 are formed in a lattice shape in a plan view. Figure 2 The grid-shaped power supply lines FL shown overlap.

[0066] The organic layer (third organic layer) OR3 covers the upper surface U21 of the second layer 32. The organic layer OR3 is covered by an upper electrode (third upper electrode) E23. The organic layer OR3 is formed of the same material as the organic layers OR1 and OR2, but is separated from both organic layers OR1 and OR2. Furthermore, the upper electrode E23 is formed of the same material as the upper electrodes E21 and E22, but is separated from both upper electrodes E21 and E22.

[0067] Figure 4 It means composition Figure 3 A plan view of an example of the second layer 32 of the partition wall 30 is shown.

[0068] The second layer 32 includes a first portion 321, a second portion 322, and a third portion 323. The first portion 321, the second portion 322, and the third portion 323 are formed integrally or continuously.

[0069] The first portion 321 extends in the first direction X. The pair of first portions 321 is disposed so as to face each other with the opening OP1 interposed therebetween.

[0070] The second portion 322 extends in the second direction Y. The pair of second portions 322 is arranged to face each other with the opening OP1 interposed therebetween.

[0071] The third portion 323 is connected to each of the first portion 321 and the second portion 322. The four third portions 323 are arranged to face each other at the four corners of the opening OP1.

[0072] Furthermore, the third portion 323 has an arc-shaped edge E323 facing the opening OP1. The edge E323 is closer to the opening OP1 than the edge E321 of the first portion 321 facing the opening OP1 and the edge E322 of the second portion 322 facing the opening OP1. Figure 4 In the example shown, the edges E321, E322, and E323 do not overlap with the opening OP1 in a plan view. However, the edge E323 may overlap with the opening OP1 in a plan view in some cases.

[0073] Figure 5 Yes Figure 3 1 is a plan view of an example of the partition wall 30. In addition, here, the outer shape of the second layer 32 in the partition wall 30 is shown, and the power supply line FL is shown by a dotted line.

[0074] In a plan view, the first portion 321 overlaps with the first wiring portion FL1 , the second portion 322 overlaps with the second wiring portion FL2 , and the third portion 323 overlaps with the third wiring portion FL3 .

[0075] The first portion 321 has a substantially constant width W11 along the second direction Y. In one example, the first portion 321 is formed to be wider than the first wiring portion FL1. That is, the width of the first portion 321 along the second direction Y is greater than the width of the first wiring portion FL1 along the second direction Y. Alternatively, the first portion 321 may be formed to have the same width as the first wiring portion FL1, or may be formed to be thinner than the first wiring portion FL1.

[0076] The second portion 322 has a substantially constant width W12 along the first direction X. In one example, the second portion 322 is formed to be wider than the second wiring portion FL2. That is, the width of the second portion 322 along the first direction X is greater than the width of the second wiring portion FL2 along the first direction X. Alternatively, the second portion 322 and the second wiring portion FL2 may be formed to have the same width, or the second portion 322 may be formed to be thinner than the second wiring portion FL2.

[0077] The third portion 323 has a width WX1 along the first direction X and a width WY1 along the second direction Y. The width WY1 is larger than the width W11 (WY1>W11). The width WX1 is larger than the width W12 (WX1>W12).

[0078] In the third portion 323 of this shape, widths WX1 and WY1 vary continuously. For example, width WX1 is equal to width W12 near second portion 322 and gradually increases as it moves away from second portion 322. Similarly, width WY1 is equal to width W11 near first portion 321 and gradually increases as it moves away from first portion 321.

[0079] Next, a method for manufacturing the display elements 21 and 22 having the above-described structure will be briefly described.

[0080] For example, after forming the lower electrodes E11 and E12, an organic insulating layer is formed and patterned to form the insulating layer 12. Then, after forming at least one of the metal layer and the insulating layer, the partition wall 30 is formed by patterning.

[0081] Then, the layers constituting the organic layer OR are formed, for example, by vacuum deposition. Here, the organic layers OR1 and OR2 are formed in the openings OP1 and OP2, respectively, and the organic layer OR3 is formed on the partition wall 30. In other words, the organic layers OR1 and OR2 are formed spaced apart from each other without using a fine mask.

[0082] Then, the upper electrode E2 is formed by sputtering, for example. At this time, upper electrodes E21 and E22 are formed in openings OP1 and OP2, respectively, and upper electrode E23 is formed on partition wall 30. That is, upper electrodes E21 and E22 are formed spaced apart from each other without using a fine mask.

[0083] The radiation angle of the material forming the upper electrode E2 is greater than that of the material forming the organic layer OR. Therefore, the material forming the organic layer OR barely reaches below the second layer 32 of the partition wall 30, exposing the power supply line FL. Meanwhile, the material forming the upper electrode E2 also winds around into the area blocked by the second layer 32 of the partition wall 30. This forms the upper electrodes E21 and E22, which are in contact with the first wiring portion FL1, the second wiring portion FL2, and the third wiring portion FL3 of the power supply line FL, respectively.

[0084] As described above, partition walls 30 are arranged between adjacent display elements 20, and the organic layer OR formed without fine masking is divided by the partition walls 30. Thus, a display element 20 having an organic layer OR of a desired shape is provided. Consequently, compared to the case of using a fine mask, manufacturing costs can be reduced, and steps such as fine mask alignment are unnecessary, making it possible to easily form the organic layer OR of a desired shape. Furthermore, in the display element 20, a light-emitting region can be formed in a predetermined area, and undesired light emission in the region overlapping the insulating layer 12 is suppressed.

[0085] Similarly to the organic layer OR, the upper electrodes E2 are also divided by the partition walls 30. However, each upper electrode E2 is connected to the power supply line FL located below the partition walls 30. Furthermore, since the power supply line FL is arranged to surround the upper electrodes E2, substantially the entire peripheral edge of the upper electrode E2 is in contact with the power supply line FL (the first wiring portion FL1, the second wiring portion FL2, and the third wiring portion FL3). This ensures a sufficient contact area between the upper electrode E2 and the power supply line FL, allowing a predetermined potential to be supplied to the entire surface of the upper electrode E2.

[0086] Figure 6 Yes Figure 1 A plan view of another example of a pixel PX.

[0087] Figure 6 The example shown is similar to Figure 2 Compared with the example shown in FIG. 1 , the shape of the third wiring portion FL3 is different. That is, the power supply line FL has a first wiring portion FL1, a second wiring portion FL2, and a third wiring portion FL3 that are formed integrally or continuously. Figure 2 The example shown is constructed in the same way.

[0088] The third wiring portion FL3 is connected to the first wiring portion FL1 and the second wiring portion FL2. Figure 6 In the example shown, the third wiring portion FL3 is formed in a substantially cross shape, having a width WX along the first direction X and a width WY along the second direction Y. Width WY is smaller than width W1 of the first wiring portion FL1 (WY < W1). Width WX is smaller than width W2 of the second wiring portion FL2 (WX < W2).

[0089] As indicated by the dashed line, the upper electrode E2 of the display element 20 overlaps not only with the light-emitting area EA but also with the insulating layer 12 between the light-emitting area EA and the power supply line FL. Furthermore, the upper electrode E2 is in contact with the first wiring portion FL1, the second wiring portion FL2, and the third wiring portion FL3. Thus, a predetermined potential is supplied to the upper electrode E2 from the power supply line FL.

[0090] Figure 7 It is a plan view showing another example of the second layer 32 constituting the partition wall 30 .

[0091] The second layer 32 includes a first portion 321, a second portion 322, and a third portion 323. These first portion 321, second portion 322, and third portion 323 are formed integrally or continuously. The edge E321 of the first portion 321 and the edge E322 of the second portion 322 are each formed into a convex arcuate shape toward the opening OP1. The edges E321 and E322 are connected to each other at the third portion 323. In a plan view, the edges E321 and E322 do not overlap with the opening OP1.

[0092] The planar shape of the second layer 32 that respectively surrounds other openings adjacent to the opening OP1 in the first direction X, other openings adjacent to the opening OP1 in the second direction Y, and other openings adjacent to the opening OP1 in the inclined direction (diagonal direction) is the same as the planar shape of the second layer 32 that surrounds the opening OP1.

[0093] Figure 8 It is a plan view showing another example of the second layer 32 constituting the partition wall 30 . Figure 8 The example shown is equivalent to Figure 4 The example shown is similar to Figure 7 Combinations of examples shown.

[0094] That is, the planar shape of the second layer 32 that surrounds the other openings adjacent to the opening OP1 in the first direction X and the other openings adjacent to the opening OP1 in the second direction Y is the same as that of the second layer 32. Figure 4 The planar shape of the second layer 32 surrounding the opening OP1 shown is the same.

[0095] Furthermore, the planar shape of the second layer 32 surrounding the other openings adjacent to the opening OP1 in the oblique direction (diagonal direction) is compared with the planar shape of the second layer 32 surrounding the other openings adjacent to the opening OP1 in the oblique direction (diagonal direction). Figure 7 The planar shape of the second layer 32 surrounding the opening OP1 shown is the same.

[0096] Figure 9 Is to express Figure 6 FIG. 1 is a plan view of an example of a partition wall 30 on which the power supply line FL is overlapped. Figure 7 The outer shape of the second layer 32 is shown, and the power supply line FL is indicated by a dotted line.

[0097] In a plan view, the first portion 321 overlaps with the first wiring portion FL1 , the second portion 322 overlaps with the second wiring portion FL2 , and the third portion 323 overlaps with the third wiring portion FL3 .

[0098] The first portion 321 extends in the first direction X and has a width W11 along the second direction Y. The width W11 varies continuously, for example, and gradually decreases as it approaches the third portion 323. The width W11 is smallest at the connection between the first portion 321 and the third portion 323.

[0099] The second portion 322 extends in the second direction Y and has a width W12 along the first direction X. The width W12 also changes continuously, for example, gradually decreasing as it approaches the third portion 323. The width W12 is smallest at the connection between the second portion 322 and the third portion 323.

[0100] Such other examples also achieve the same effects as described above.

[0101] According to the present embodiment described above, a display device capable of supplying a predetermined potential to the upper electrode of the display element can be provided.

[0102] Based on the display devices described above as the embodiments of the present invention, all display devices implemented by those skilled in the art with appropriate design changes also fall within the scope of the present invention as long as they include the gist of the present invention.

[0103] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, and these variations should also be understood to fall within the scope of the present invention. For example, with respect to the above-mentioned embodiments, variations obtained by those skilled in the art by appropriately adding, deleting, or changing the design of constituent elements, or by adding, omitting, or changing the conditions of processes, as long as they retain the gist of the present invention, are also within the scope of the present invention.

[0104] Furthermore, other effects brought about by the configurations described in the above embodiments that are clear from the description of this specification or that can be appropriately conceived by those skilled in the art should naturally be understood as brought about by the present invention.

Claims

1. A display device, characterized in that: have: insulating substrate; a first insulating layer disposed on the insulating substrate; A lower electrode is disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, having an opening overlapping with the lower electrode and formed in a lattice pattern; a power supply line disposed on the second insulating layer, comprising a first wiring portion extending in a first direction, a second wiring portion extending in a second direction intersecting the first direction, and a third wiring portion connected to the first wiring portion and the second wiring portion and having a width different from the widths of the first wiring portion and the second wiring portion; an organic layer including a light-emitting layer, disposed in the opening and covering the lower electrode; and an upper electrode, which is in contact with the first wiring portion, the second wiring portion, and the third wiring portion, respectively, and covers the organic layer; The width of the third wiring portion along the second direction is greater than the width of the first wiring portion along the second direction; The width of the third wiring portion along the first direction is greater than the width of the second wiring portion along the first direction; The third wiring portion is formed into a quadrilateral; It also includes a partition wall arranged above the power supply line, The partition wall has: a first layer having a side surface facing the opening; and a second layer, overlapping the first layer and extending from the side toward the opening; In a plan view, the second layer is formed in a lattice shape and includes a first portion extending in the first direction and overlapping with the first wiring portion, a second portion extending in the second direction and overlapping with the second wiring portion, and a third portion connected to the first and second portions and overlapping with the third wiring portion. The width of the third portion along the second direction is greater than the width of the first portion along the second direction; The width of the third portion along the first direction is greater than the width of the second portion along the first direction; The third portion has an arc-shaped edge facing the opening.

2. The display device according to claim 1, wherein The width of the first portion along the second direction is greater than the width of the first wiring portion along the second direction; A width of the second portion along the first direction is larger than a width of the second wiring portion along the first direction.

3. The display device according to claim 2, wherein The edge portion does not overlap with the opening portion in a plan view.

4. A display device, characterized in that: have: insulating substrate; a first insulating layer disposed on the insulating substrate; A lower electrode is disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, having an opening overlapping with the lower electrode and formed in a lattice pattern; a power supply line disposed on the second insulating layer, comprising a first wiring portion extending in a first direction, a second wiring portion extending in a second direction intersecting the first direction, and a third wiring portion connected to the first wiring portion and the second wiring portion and having a width different from the widths of the first wiring portion and the second wiring portion; an organic layer including a light-emitting layer, disposed in the opening and covering the lower electrode; and an upper electrode, which is in contact with the first wiring portion, the second wiring portion, and the third wiring portion, respectively, and covers the organic layer; The width of the third wiring portion along the second direction is smaller than the width of the first wiring portion along the second direction; A width of the third wiring portion along the first direction is smaller than a width of the second wiring portion along the first direction.

5. The display device according to claim 4, wherein The third wiring portion is formed in a cross shape.

6. The display device according to claim 4, wherein Also provided is a partition wall disposed above the power supply line; The partition wall has: a first layer having a side surface facing the opening; and a second layer, overlapping the first layer and extending from the side toward the opening; In a plan view, the second layer is formed in a lattice shape and includes a first portion extending in the first direction and overlapping with the first wiring portion, a second portion extending in the second direction and overlapping with the second wiring portion, and a third portion connected to the first and second portions and overlapping with the third wiring portion. The width of the third portion along the second direction is smaller than the width of the first portion along the second direction; A width of the third portion along the first direction is smaller than a width of the second portion along the first direction.

7. The display device according to claim 6, wherein The edge of the first portion and the edge of the second portion are each formed in a convex shape toward the opening.

8. The display device according to claim 7, wherein: The edge portion does not overlap with the opening portion in a plan view.

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