GaN-based HEMTs and their preparation methods using local pre-etching ohmic processes

Abstract

This invention discloses a GaN-based HEMT employing a local pre-etching ohmic process and its fabrication method. The method includes selecting an epitaxial substrate; etching a buffer layer of a first predetermined thickness from both ends of the active region of the epitaxial substrate to form an electrically isolated region; etching a barrier layer of a second predetermined thickness to form two sets of patterned array regions; depositing an alloy pre-deposition layer in the two sets of patterned array regions; depositing ohmic metal on the source electrode patterned region and drain electrode patterned region located on the barrier layer and alloy pre-deposition layer, respectively, to form the source electrode and drain electrode; growing a passivation layer on the barrier layer, source electrode, and drain electrode; etching the passivation layer to the surface of the barrier layer to form a gate trench; and depositing gate electrode metal in the gate trench to form the gate electrode. This invention reduces the annealing temperature and contact resistance of the gold-free ohmic contact, lowers the device knee voltage, and improves the power-added efficiency; it also improves the flatness of the ohmic contact surface and reduces the metal outward expansion at the edge of the source and drain electrodes.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a GaN-based HEMT using a local pre-etching ohmic process and its preparation method. Background Technology

[0002] Gallium nitride (GaN) material possesses excellent physical properties such as a large bandgap, high electron saturation velocity and migration velocity, and radiation resistance. GaN-based high electron mobility transistors (HEMTs) exhibit outstanding performance. The high carrier density and high mobility of the two-dimensional electron gas (2DEG) confined at the AlGaN / GaN heterojunction interface enable low on-resistance, minimizing power loss and self-heating. Their high breakdown field strength and high electron drift velocity enable high-frequency and high-power applications. Therefore, GaN-based HEMT transistors have attracted significant attention. Currently, most GaN-based HEMT devices use SiC substrates, but SiC-based GaN is expensive, and the small substrate size leads to low production capacity, failing to meet 5G requirements. To reduce manufacturing costs and significantly increase production capacity, it is imperative to fabricate GaN-based HEMTs on large-size silicon substrates. Silicon-based standard complementary metal-oxide-semiconductor (CMOS) production lines are mature and can greatly improve tape-out efficiency. However, GaN-based HEMTs currently generally employ alloy ohmic contact processes, where Au diffusion into silicon causes deep-level contamination. Therefore, conventional GaN ohmic contacts are incompatible with CMOS processes. Thus, the development of CMOS-compatible gold-free ohmic contacts with sufficiently low contact resistance (<0.2 Ω·mm) is a key condition for manufacturing Si-based GaN HEMT devices on mature CMOS production lines. Low contact resistance (Rc) is crucial for device performance, including output power, high efficiency, high frequency performance, and noise performance. Therefore, high-quality ohmic contacts with low resistance, good thermal stability, and smooth surface morphology are essential to ensuring optimal device performance of GaN-based HEMTs.

[0003] Currently, both domestically and internationally, Ti / Al-based ohmic metals are commonly used in device fabrication to achieve gold-free CMOS-compatible ohmic contacts, resulting in lower ohmic contact resistance. These methods include:

[0004] In 2011, Hyung-Seok Lee et al. used techniques such as ohmic groove etching to fabricate an AlGaN / GaN HEMT device with a gate length of 3µm on a Si substrate. The ohmic metal used was a Ti / Al / W metal scheme, the annealing temperature was 880℃, the contact resistance was 0.49Ω·mm, and the saturation current was 400mA / mm.

[0005] In 2018, Li Qixin et al. used techniques such as trench etching to fabricate an AlGaN / GaN HEMT device with a gate length of 3µm on a Si substrate. The ohmic metal used was a Ti / Al / Ti / TiW metal scheme, the annealing temperature was 700℃, the contact resistance was 0.99Ω·mm, and the saturation current was 345.7mA / mm.

[0006] In summary, the current international standard for achieving Si-based GaN CMOS compatibility is Ti / Al-based gold-free ohmic contact technology. However, these technologies all have the following problems:

[0007] 1. While using ohmic groove pre-etching to reduce ohmic contact resistance, it also causes etch damage to the barrier layer, depleting part of the two-dimensional electron gas in the channel, resulting in a lower saturation current of the device and thus reducing the output power density of the device.

[0008] 2. Ohmic annealing causes the metal to expand outward, resulting in a rough surface morphology and reduced edge sharpness, making it unsuitable for short-gate long millimeter-wave device applications;

[0009] 3. Ti / Al metals have poor thermal stability and poor radio frequency reliability; Summary of the Invention

[0010] To address the aforementioned problems in the prior art, this invention provides a GaN-based HEMT employing a local pre-etching ohmic process and its preparation method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0011] A method for preparing GaN-based HEMTs using a local pre-etching ohmic process includes:

[0012] Select an epitaxial substrate, wherein the epitaxial substrate comprises a substrate layer, a nucleation layer, a buffer layer and a barrier layer stacked sequentially from bottom to top;

[0013] The active region of the epitaxial substrate is etched from both ends to the buffer layer of a first preset thickness to form an electrically isolated region, wherein the first preset thickness is less than the thickness of the buffer layer.

[0014] The barrier layer of a second preset thickness is etched to form two sets of patterned array regions, wherein the second preset thickness is less than the thickness of the barrier layer;

[0015] An alloy pre-deposited layer, wherein the alloy pre-deposited layer is Si, is deposited within the two sets of patterned array regions. x Ta y Al z alloy;

[0016] Ohmic metals are deposited on the source electrode pattern region and the drain electrode pattern region located on the barrier layer and the alloy pre-deposition layer, respectively, to form the source electrode and the drain electrode;

[0017] A passivation layer is grown on the barrier layer, the source electrode, and the drain electrode;

[0018] The passivation layer is etched down to the surface of the barrier layer to form a gate trench;

[0019] A gate electrode metal is deposited in the gate trench to form a gate electrode, which is located between the source electrode and the drain electrode.

[0020] In one embodiment of the present invention, etching the buffer layer from both ends of the active region of the epitaxial substrate to a first predetermined thickness to form an electrically isolated region includes:

[0021] Photolithographically etched isolation regions onto the barrier layer;

[0022] The barrier layer of the isolation region of the epitaxial substrate is dry-etched using an ICP process down to the buffer layer of the first preset thickness to form an electrically isolated region.

[0023] Remove the first photoresist outside the electrically isolated region.

[0024] In one embodiment of the present invention, before etching the barrier layer to a second predetermined thickness to form two sets of patterned array regions, the method further includes:

[0025] Si was prepared using the hot isostatic pressing method of powder metallurgy. x Ta y Al z alloy.

[0026] In one embodiment of the present invention, the barrier layer of a second predetermined thickness is etched to form two sets of patterned array regions, including:

[0027] A first release adhesive is prepared on the barrier layer;

[0028] A second photoresist is prepared on the first release adhesive;

[0029] The second photoresist in the two array regions is exposed;

[0030] The second photoresist after exposure is developed to remove the first stripper and the second photoresist in the array area;

[0031] The barrier layer of the second preset thickness in the array region is etched using an ICP process to form two sets of patterned array regions.

[0032] In one embodiment of the present invention, an alloy pre-deposited layer is deposited within the two sets of patterned array regions, including:

[0033] Si was deposited in the two patterned array regions using magnetron sputtering or electron beam evaporation. x Ta y Al z Alloys are used to form an alloy pre-deposited layer.

[0034] In one embodiment of the present invention, ohmic metal is deposited on the source electrode pattern region and the drain electrode pattern region located on the barrier layer and the alloy pre-deposition layer, respectively, to form the source electrode and the drain electrode, including:

[0035] A second release adhesive is prepared on the barrier layer and the alloy pre-deposited layer;

[0036] A third photoresist is prepared on the second release adhesive;

[0037] The third photoresist in the source electrode pattern area and the drain electrode pattern area is exposed;

[0038] The third photoresist after exposure is developed to remove the second and third release adhesives from the source electrode pattern area and the drain electrode pattern area;

[0039] The ohmic metal is deposited on the barrier layer and the alloy pre-deposition layer in the source electrode pattern region and the drain electrode pattern region using a magnetron sputtering process. The ohmic metal includes a pre-deposition layer, a contact layer, a catalyst layer, a barrier layer and a cap layer stacked sequentially from bottom to top.

[0040] A rapid annealing process is used to anneal the alloy pre-deposited layer and the ohmic metal to sink into the buffer layer to form the source electrode and the drain electrode.

[0041] In one embodiment of the present invention, a passivation layer is grown on the barrier layer, the source electrode, and the drain electrode, comprising:

[0042] A passivation layer is prepared on the barrier layer, the source electrode, and the drain electrode using a PECVD process.

[0043] In one embodiment of the present invention, etching the passivation layer to the surface of the barrier layer to form a gate trench includes:

[0044] A third release adhesive is prepared on the passivation layer;

[0045] A fourth photoresist is prepared on the third release adhesive;

[0046] The fourth photoresist in the gate electrode pattern area is exposed;

[0047] The fourth photoresist after exposure is developed to remove the third stripper and the fourth photoresist in the gate electrode pattern area;

[0048] The passivation layer of the gate electrode pattern area is etched to the surface of the barrier layer using an ICP process to form a gate trench.

[0049] In one embodiment of the present invention, depositing gate electrode metal within the gate trench to form a gate electrode includes:

[0050] The gate electrode metal is deposited in the gate trench using a magnetron sputtering process to form the gate electrode.

[0051] An embodiment of the present invention also provides a GaN-based HEMT using a local pre-etching ohmic process, prepared using the preparation method described in any of the above embodiments, wherein the GaN-based HEMT comprises:

[0052] An epitaxial substrate, the epitaxial substrate comprising a substrate layer, a nucleation layer, a buffer layer and a barrier layer stacked sequentially from bottom to top;

[0053] Two sets of patterned array regions of a second preset thickness are provided within the barrier layer;

[0054] An alloy pre-deposited layer is provided in each of the two sets of patterned array regions;

[0055] Active electrodes and drain electrodes are respectively disposed on the two alloy pre-deposited layers and the barrier layer;

[0056] A passivation layer is provided on the barrier layer, the source electrode, and the drain electrode;

[0057] A gate electrode is disposed within the gate trench of the passivation layer.

[0058] The beneficial effects of this invention are:

[0059] 1. This invention utilizes Si x Ta y Al z The pre-deposited alloy layer significantly reduces the annealing temperature and contact resistance of the gold-free ohmic contact, lowers the knee voltage of the device, and improves the power-added efficiency. It also improves the flatness of the ohmic contact surface and improves the metal expansion at the edges of the source and drain electrodes, making it suitable for the fabrication of millimeter-wave devices with small source-drain spacing.

[0060] 2. This invention utilizes a patterned array region formed within a barrier layer, and fabricates Si within this patterned array region. x Ta y Al z The alloy pre-deposited layer of the alloy material effectively increases the contact area between the metal layer and the barrier layer, and increases the probability of electron tunneling in the barrier layer at the etched deep hole, thereby reducing the ohmic contact resistance, reducing the etch area of ​​the barrier layer, reducing the damage of etching to 2EDG, thereby increasing the saturation current, and thus improving the power amplification characteristics of the transistor.

[0061] 3. The etching process of the patterned array region of the ohmic contact layer used in this invention has strong compatibility. The local pre-etching of the patterned array region in this invention can be completed using existing photolithography and etching machines, which is low-cost and easy to maintain.

[0062] 4. This invention can greatly improve production capacity by adopting a complete set of gold-free processes and being compatible with Si-based CMOS production lines.

[0063] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0064] Figure 1 This is a schematic flowchart of a method for preparing GaN-based HEMTs using a local pre-etching ohmic process, provided in an embodiment of the present invention.

[0065] Figures 2a to 2i This is a schematic diagram of a method for preparing GaN-based HEMTs using a local pre-etching ohmic process, provided in an embodiment of the present invention.

[0066] Figure 3 This is a schematic diagram of a graphical array region provided in an embodiment of the present invention;

[0067] Figure 4 This is a schematic diagram of a GaN-based HEMT using a local pre-etching ohmic process, provided in an embodiment of the present invention. Detailed Implementation

[0068] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0069] Example 1

[0070] Please see Figure 1 And Figure 2, Figure 1 This is a schematic flowchart of a method for preparing GaN-based HEMTs using a local pre-etching ohmic process, provided by an embodiment of the present invention. Figures 2a to 2iThis is a schematic diagram illustrating a method for fabricating a GaN-based HEMT using a local pre-etching ohmic process, as provided in an embodiment of the present invention. This embodiment provides a method for fabricating a GaN-based HEMT using a local pre-etching ohmic process, which includes:

[0071] Step 1, please refer to Figure 2a An epitaxial substrate 10 is selected, which includes a substrate layer 101, a nucleation layer 102, a buffer layer 103 and a barrier layer 104 stacked sequentially from bottom to top.

[0072] Furthermore, the substrate layer 101 is made of Si, the nucleation layer 102 is made of AlN, the buffer layer 103 is made of GaN, and the barrier layer 104 is made of AlGaN.

[0073] In this embodiment, after selecting the epitaxial substrate 10, it is also necessary to clean the epitaxial substrate 10.

[0074] Specifically, the epitaxial substrate 10 is first ultrasonically treated in acetone for 2 minutes, then boiled in a positive stripping solution heated in a 60°C water bath for 10 minutes. Subsequently, the epitaxial substrate 10 is ultrasonically treated in acetone and ethanol for 3 minutes each, and the residual acetone and ethanol are washed away with deionized water. Finally, the epitaxial substrate 10 is cleaned with HF solution for 30 seconds, then cleaned with deionized water and dried with ultrapure nitrogen.

[0075] Step 2, please refer to Figure 2b The active region of the epitaxial substrate 10 is etched to a first preset thickness from both ends to the buffer layer 103 to form an electrical isolation region 20. The first preset thickness is less than the thickness of the buffer layer 103. The thickness of the buffer layer 103 is the overall thickness of the buffer layer 103. The electrical isolation region 20 is used to achieve active region isolation.

[0076] Step 2.1: Photolithographically etch an isolation region on the barrier layer 104, wherein the isolation region is the area used to form the electrically isolated region 20.

[0077] Step 2.11: Bake the epitaxial substrate 10.

[0078] Specifically, the epitaxial substrate 10 is baked on a hot plate at 200°C for 5 minutes.

[0079] Step 2.12: Prepare the first photoresist on the barrier layer 104.

[0080] Specifically, the first photoresist is sprayed onto the barrier layer 104 using a spin coater at a speed of 3600 rpm. After the spin coat is completed, the photoresist is baked on a hot plate at 100°C for 1 minute.

[0081] Step 2.13: Expose the first photoresist in the isolation region of barrier layer 104.

[0082] Specifically, the epitaxial substrate 10 is placed in a lithography machine to expose the first photoresist in the isolation region.

[0083] Step 2.14: Develop the first photoresist after exposure and remove the first photoresist in the isolation area to form isolation areas at both ends of the barrier layer 104.

[0084] Specifically, the epitaxial substrate 10 after exposure is placed in a developer to remove the first photoresist in the isolation area, and then rinsed with ultrapure water and dried with nitrogen.

[0085] Step 2.2: Use ICP (Inductively Coupled Plasma) process to dry etch the barrier layer 104 of the isolation region of the epitaxial substrate 10 to a buffer layer 103 of a first preset thickness to form an electrically isolated region 20.

[0086] Specifically, the barrier layer 104 to the buffer layer 103 of the first preset thickness in the isolation region is dry etched using the ICP process to achieve mesa isolation of the active region. The etching gas is Cl2 / BCl3, the pressure is 5 mTorr, the upper electrode power is 100 W, the lower electrode power is 10 W, and the etching time is 40 s.

[0087] Step 2.3: Remove the first photoresist outside the electrically isolated region 20.

[0088] Specifically, the epitaxial substrate 10 with active region isolation completed is sequentially placed in acetone solution, stripping solution, acetone solution and ethanol solution for cleaning to remove the first photoresist outside the electrically isolated region 20, and then cleaned with deionized water and dried with nitrogen gas.

[0089] Step 3: Prepare Si using powder metallurgy hot isostatic pressing. x Ta y Al z alloy.

[0090] Step 3.1: Place silicon powder, tantalum powder and aluminum powder into a V-type powder mixer in an atomic ratio of 1:1:10 and mix for 12 hours under inert gas protection.

[0091] Step 3.2: Load the mixed powder into a rubber sleeve mold, seal it, and place it in a cold isostatic press. Press it to 200 MPa and hold it for 40 minutes to perform cold isostatic pressing treatment to obtain silicon-tantalum-aluminum billet.

[0092] Step 3.3: Place the silicon-tantalum-aluminum billet into a stainless steel sleeve and seal it. Then, place it under a vacuum of 6×10⁻⁶. -3The gas is degassed by heating to 400℃ under pressure for 8 hours.

[0093] Step 3.4: Place the degassed casing into a hot isostatic pressing furnace, and achieve a vacuum degree of 6×10⁻⁶. -3 After Pa, the temperature is raised to 1100℃, and the pressure of the hot press head is maintained at 140MPa for 3 hours.

[0094] Step 3.5: The obtained tantalum-aluminum-silicon alloy sputtering target rough is machined to obtain the tantalum-aluminum-silicon alloy sputtering target, i.e., Si. x Ta y Al z alloy.

[0095] Step 4, please refer to Figure 2c The barrier layer 104 of a second preset thickness is etched to form two sets of patterned array regions 30. The second preset thickness is less than the thickness of the barrier layer 104. The thickness of the barrier layer 104 is the overall thickness of the barrier layer 104. The patterned array regions 30 are composed of an array of holes.

[0096] Further, please see Figure 3 The patterned array region 30 includes a square array region, a circular array region, or a rhombus array region, that is, the shape of the holes forming the patterned array region 30 includes square, circular, or rhombus.

[0097] Further, please see Figure 3 The distance c between the two columns of patterns in the patterned array region 30 is 1-10 μm.

[0098] Further, please see Figure 3 The dimensions of the patterned array region 30 are (5-20)μm×100μm, where 5μm≦a≤20μm, and b is designed according to the device application scenario, for example, it can be 100μm.

[0099] Furthermore, the second preset thickness is 5-20nm.

[0100] Step 4.1: Prepare the first release adhesive on the barrier layer 104.

[0101] Specifically, the epitaxial substrate 10 with the electrically isolated region 20 is first baked on a hot plate at 200°C for 5 minutes; then, a first release adhesive is spun onto the epitaxial substrate 10 with a thickness of 0.35 μm, and the first release adhesive is baked on a hot plate at 200°C for 5 minutes.

[0102] Step 4.2: Prepare a second photoresist on the first release adhesive.

[0103] Specifically, a second photoresist is spun onto the first release adhesive, with a spun thickness of 0.77 μm, and the epitaxial substrate 10 for preparing the second photoresist is baked on a hot plate at 100°C for 1 min.

[0104] Step 4.3: Expose the second photoresist in the two array regions, where the array regions are the areas used to form the electrically isolated region 20.

[0105] Specifically, the exposed epitaxial substrate 10 is placed in a photolithography machine, and then the photoresist in the array region is exposed.

[0106] Step 4.4: Develop the second photoresist after exposure to remove the first release adhesive and the second photoresist in the array area.

[0107] Specifically, the exposed epitaxial substrate 10 is placed in a developer solution to remove the second photoresist and the first release agent in the array region, and then rinsed with ultrapure water and dried with nitrogen.

[0108] Step 4.5: Use ICP process to dry etch the barrier layer 104 of the second preset thickness in the array region to form two sets of patterned array regions 30.

[0109] Specifically, for the epitaxial substrate 10 that has undergone photolithography, the barrier layer 104 of the second preset thickness is etched by dry etching using ICP process to achieve the etching of the patterned array grooves in the ohmic region. The etching gas used is Cl2 / BCl3, with a BCl3 flow rate of 20 sccm, a Cl2 flow rate of 8 sccm, a pressure of 5 mTorr, an upper electrode power of 60 W, a lower electrode power of 15 W, and an etching time of 15 s.

[0110] Afterwards, the epitaxial substrate 10, which has been photolithographically etched and patterned in the patterned array region 30, is removed using a plasma stripper to remove the thin layer of photoresist that has not been properly developed in the patterned array region 30. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0111] Step 5, please refer to Figure 2d An alloy pre-deposited layer 40 is deposited within two sets of patterned array regions 30. The alloy pre-deposited layer 40 is Si. x Ta y Al z alloy.

[0112] Specifically, the epitaxial substrate 10, after plasma resist removal, is placed in the Sputter magnetron sputtering stage, and the vacuum level in the reaction chamber of the magnetron sputtering stage reaches 2×10⁻⁶. -6 Following the Torr process, a 20 nm thick Si layer is sputtered onto the barrier layer 104 within the patterned array region 30. x Ta y Alz Alloy, to form an alloy pre-deposited layer 40.

[0113] In this embodiment, in order to form the alloy pre-deposited layer 40, it is also necessary to strip the metal outside the patterned array region 30.

[0114] Specifically, first, the epitaxial substrate 10 with patterned array sputtering is immersed in acetone for more than 40 minutes and then ultrasonically treated; then, the sample is placed in a stripping solution at 60°C and heated in a water bath for 5 minutes; after that, the epitaxial substrate 10 is ultrasonically cleaned in acetone solution and ethanol solution for 3 minutes in sequence; finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0115] Step 6: Deposit ohmic metal on the source electrode pattern region and the drain electrode pattern region located on the barrier layer 104 and the alloy pre-deposition layer 40, respectively, to form the source electrode 60 and the drain electrode 70, wherein the source electrode pattern region is the region for forming the source electrode and the drain electrode pattern region is the region for forming the drain electrode.

[0116] Step 6.1: Prepare a second release adhesive on the barrier layer 104 and the alloy pre-deposited layer 40.

[0117] Specifically, firstly, the epitaxial substrate 10, in which the alloy pre-deposition layer has been deposited within the patterned array region 30, is placed on a hot plate at 200°C and baked for 5 minutes; then, a second release adhesive is spun onto the barrier layer 104 and the alloy pre-deposition layer 40, with a release adhesive thickness of 0.35 μm, and baked on a hot plate at 200°C for 5 minutes.

[0118] Step 6.2: Prepare the third photoresist on the second release adhesive.

[0119] Specifically, a third photoresist is spun onto the second release adhesive to a thickness of 0.77 μm, and then baked on a hot plate at 100°C for 1 min.

[0120] Step 6.3: Expose the third photoresist in the source electrode pattern area and the drain electrode pattern area.

[0121] Specifically, the epitaxial substrate 10, on which the second release agent and the third photoresist are prepared on the barrier layer 104 and the alloy pre-deposited layer 40, is placed in a photolithography machine to expose the third photoresist in the source electrode pattern area and the drain electrode pattern area.

[0122] Step 6.4: Develop the third photoresist after exposure to remove the second and third release adhesives from the source electrode pattern area and the drain electrode pattern area.

[0123] Specifically, the exposed epitaxial substrate 10 is placed in a developer solution to remove the second release adhesive and the third photoresist in the source electrode pattern area and the drain electrode pattern area, and then rinsed with ultrapure water and dried with nitrogen.

[0124] Step 6.5: Apply base coat.

[0125] Specifically, the epitaxial substrate 10 with completed source electrode patterning and drain electrode patterning is subjected to a plasma stripper to remove the undeveloped photoresist thin layer in the source electrode patterning and drain electrode patterning areas. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0126] Step 6.6, please refer to Figure 2e Ohmic metal 50 is deposited on the barrier layer 104 and alloy pre-deposition layer 40 in the source electrode pattern region and the drain electrode pattern region using a magnetron sputtering process. Ohmic metal 50 includes a pre-deposition layer, a contact layer, a catalyst layer, a barrier layer and a cap layer stacked sequentially from bottom to top.

[0127] Furthermore, the material of the pre-deposited layer can be Si, Ge, or Si. x Ge y Si x Ti y Si x Ta y Al z or Si x Ti y Al z Where X, Y, and Z represent the atomic ratios of different elements.

[0128] Preferably, the material of the pre-deposited layer is Si. x Ta y Al z The alloy has a thickness of 20nm-100nm, with Si content of 10%-50%, Ta content of 10%-30%, and Al content of 20%-80%.

[0129] Furthermore, the material of the contact layer can be Ti, Ta, or Ti2. x Al y Or Ta x Al y .

[0130] Furthermore, the catalyst layer can be made of Al.

[0131] Furthermore, the material of the barrier layer can be Ta, Ti, Ni, or Mo.

[0132] Furthermore, the material of the cap layer can be Au, TiN, TiW, W, TiC, or TaN.

[0133] Specifically, the epitaxial substrate 10, after plasma resist removal, is placed in the Sputter magnetron sputtering stage, and the vacuum level in the reaction chamber of the magnetron sputtering stage reaches 2×10⁻⁶. -6 After Torr, the following layers are sputtered sequentially on the barrier layer 104 in the source electrode pattern region and the drain electrode pattern region: a pre-deposited layer with a thickness of 20 nm, a Ta contact layer with a thickness of 20 nm, an Al catalyst layer with a thickness of 20 nm, a Ta barrier layer with a thickness of 30 nm, and a TaN cap layer with a thickness of 70 nm.

[0134] Step 6.7: Strip away the metal outside the source electrode pattern area and the drain electrode pattern area.

[0135] Specifically, firstly, the epitaxial substrate 10 after plasma resist removal is immersed in acetone for more than 40 minutes and then subjected to ultrasonic treatment; then, the epitaxial substrate 10 with ohmic metal 50 is placed in a stripping solution at 60°C and heated in a water bath for 5 minutes; then, the epitaxial substrate 10 with ohmic metal 50 is placed in acetone solution and ethanol solution sequentially and ultrasonically cleaned for 3 minutes; then, the epitaxial substrate 10 with ohmic metal 50 is rinsed with ultrapure water and dried with nitrogen gas.

[0136] Step 6.9, please refer to Figure 2f The alloy pre-deposited layer 40 and the ohmic metal 50 are annealed using a rapid annealing process to sink the alloy pre-deposited layer 40 and the ohmic metal 50 to the buffer layer 103 to form the source electrode 60 and the drain electrode 70.

[0137] Specifically, the epitaxial substrate 10 processed in step 6.8 is placed in a rapid annealing furnace, nitrogen gas is introduced into the rapid annealing furnace for 10 minutes, and then the annealing furnace temperature is set to 700°C in a nitrogen atmosphere. Then, high-temperature annealing is performed for 60 seconds to allow the ohmic metal 50 in the source electrode pattern region and the drain electrode pattern region, as well as the alloy pre-deposited layer 40 in the patterned array region 30, to sink to the buffer layer 103, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel, forming the source electrode 60 and the drain electrode 70.

[0138] Step 7, please refer to Figure 2g A passivation layer 80 is grown on the barrier layer 104, the source electrode 60, and the drain electrode 70.

[0139] Step 7.1: Clean the surface of the epitaxial substrate 10 that forms the active electrode 60 and the drain electrode 70.

[0140] Specifically, firstly, the epitaxial substrate 10 forming the active electrode 60 and the drain electrode 70 is placed in an acetone solution and ultrasonically cleaned for 3 minutes with an ultrasonic intensity of 3.0.

[0141] Then, the epitaxial substrate 10 forming the active electrode 60 and the drain electrode 70 is placed in a stripping solution at a temperature of 60°C and heated in a water bath for 5 minutes.

[0142] Next, the epitaxial substrate 10, which forms the active electrode 60 and the drain electrode 70, is sequentially immersed in acetone solution and ethanol solution for ultrasonic cleaning for 3 minutes, with an ultrasonic intensity of 3.0.

[0143] Finally, the epitaxial substrate 10 forming the active electrode 60 and the drain electrode 70 is rinsed with ultrapure water and dried with nitrogen.

[0144] Step 7.2: A passivation layer 80 is prepared on the barrier layer 104, source electrode 60 and drain electrode 70 using PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

[0145] Specifically, a passivation layer 80 with a thickness of 120 nm is grown on the barrier layer 104, the source electrode 60, and the drain electrode 70 using a PECVD process. The growth process conditions are as follows: NH3 and SiH4 are used as the Si source and N source, respectively, with a preferred flow ratio of SiH4:NH3 = 2:1; the deposition temperature is 250 °C; the reaction chamber pressure is 600 mTorr; the RF power is 22 W; and the reaction time is 15 min.

[0146] Preferably, the passivation layer 80 is made of SiN.

[0147] Step 8, please refer to Figure 2h The passivation layer 80 is etched onto the surface of the barrier layer 104 to form the gate trench 90.

[0148] Step 8.1: Prepare a third release adhesive on the passivation layer 80.

[0149] Specifically, the epitaxial substrate 10 with the passivation layer 80 is first baked on a hot plate at 200°C for 5 minutes; then, a third release adhesive is spun onto the passivation layer 80 with a thickness of 0.35 μm, and baked on a hot plate at 200°C for 5 minutes.

[0150] Step 8.2: Prepare the fourth photoresist on the third release adhesive.

[0151] Specifically, a fourth photoresist is spun onto the third release adhesive, with a thickness of 0.77 μm, and then baked on a hot plate at 90°C for 1 min.

[0152] Step 8.3: Expose the fourth photoresist in the gate electrode pattern area.

[0153] Specifically, an epitaxial substrate 10 with a third release agent and a fourth photoresist prepared on a passivation layer 80 is placed in a photolithography machine to expose the fourth photoresist in the gate electrode pattern area.

[0154] Step 8.4: Develop the fourth photoresist after exposure to remove the third and fourth release adhesives from the gate electrode pattern area.

[0155] Specifically, the exposed epitaxial substrate 10 is placed in a developer solution to remove the third release agent and the fourth photoresist in the gate electrode pattern area, and then rinsed with ultrapure water and dried with nitrogen.

[0156] Step 8.5: Apply base film.

[0157] Specifically, the epitaxial substrate 10 with completed gate electrode pattern area photolithography is used to remove the undeveloped photoresist layer inside the epitaxial substrate 10 using a plasma stripper, and the processing time is 5 minutes.

[0158] Step 8.6: Use ICP process to dry etch the passivation layer 80 to the surface of the barrier layer 104 of the gate electrode pattern area to form the gate trench 90.

[0159] Specifically, the passivation layer 80 of the gate electrode pattern area is removed to the surface of the barrier layer 104 using an ICP device under dry etching conditions where the reaction gases are CF4 and O2, the reaction chamber pressure is 10 mTorr, and the radio frequency powers of the upper and lower electrodes are 100 W and 10 W, respectively, to form the gate trench 90.

[0160] Step 9, please refer to Figure 2i Gate electrode metal is deposited in gate trench 90 to form gate electrode 100, which is located between source electrode 60 and drain electrode 70.

[0161] Specifically, the epitaxial substrate 10 with the gate trench 90 opening is placed in the Sputter magnetron sputtering stage, and the vacuum level of the reaction chamber of the sputtering stage reaches 2×10⁻⁶. -6 After Torr, gate electrode metal is sputtered onto the photoresist outside the gate trench 90. The gate electrode metal consists of a metal stack structure composed of two layers of metal, 80nm TiN and 50nm Pt, stacked sequentially from bottom to top.

[0162] Next, the epitaxial substrate 10 with sputtered gate electrode metal is immersed in acetone for more than 40 minutes and then ultrasonically treated. Then, the epitaxial substrate 10 with sputtered gate electrode metal is placed in a stripping solution at 60°C and heated in a water bath for 5 minutes to remove the gate electrode metal outside the gate trench 90 and form the gate electrode 100 in the gate trench 90. Then, the epitaxial substrate 10 with the gate electrode metal removed from the gate trench 90 is ultrasonically cleaned in acetone solution and ethanol solution for 3 minutes in sequence. Finally, it is rinsed with ultrapure water and dried with nitrogen to complete the fabrication of the device.

[0163] In this invention, due to Ta's high melting point and large atomic number, Ta-based ohmic contacts exhibit excellent performance in terms of solid-state reactions and surface morphology between metals. Through Si x Ta y Al z Si prepared by alloy target or Si, Ta, Al co-sputtering x Ta y Al z The alloy pre-deposited layer can form an ohmic contact with low contact resistance and a smooth, sharp surface morphology under low-temperature annealing. Furthermore, due to the edge-concentration effect of ohmic electrodes, the current is mainly concentrated at the electrode edges. Therefore, by etching a patterned array of AlGaN barrier layers in the source and drain ohmic edge regions, it is possible to effectively increase the contact area between the metal layer (including the alloy pre-deposited layer and the ohmic metal) and the barrier layer, and improve the electron tunneling probability of the barrier layer at the etched deep holes, thereby reducing the ohmic contact resistance. Moreover, it can significantly reduce damage to the 2EDG, thus forming a high-current, low-resistance, gold-free ohmic contact.

[0164] The GaN-based HEMT device prepared by this invention can be used in 5G base station systems, satellite navigation, radar systems, and mobile phone SoCs, etc.

[0165] The GaN-based HEMT device prepared by this invention achieves a reduction in the annealing temperature of the gold-free ohmic contact and forms a low-resistivity gold-free ohmic contact with a sharp surface morphology, while maintaining the characteristic of a large saturation current.

[0166] Example 2

[0167] Please see Figure 4 , Figure 4 This is a schematic diagram of a GaN-based HEMT using a local pre-etch ohmic process provided in an embodiment of the present invention. Based on the above embodiment, the present invention also provides a GaN-based HEMT using a local pre-etch ohmic process, the GaN-based HEMT comprising:

[0168] Epitaxial substrate 10 includes a substrate layer 101, a nucleation layer 102, a buffer layer 103 and a barrier layer 104 stacked sequentially from bottom to top;

[0169] Two sets of patterned array regions 30 with a second preset thickness are provided within the barrier layer 104;

[0170] An alloy pre-deposited layer 40 is provided in each of the two sets of patterned array regions 30;

[0171] Active electrode 60 and drain electrode 70 are respectively disposed on the two alloy pre-deposited layers 40 and the barrier layer 104;

[0172] A passivation layer 80 is provided on the barrier layer 104, the source electrode 60 and the drain electrode 70;

[0173] A gate electrode 100 is disposed within the gate trench 9 of the passivation layer 80.

[0174] Further, please see Figure 3 The patterned array region 30 includes a square array region, a circular array region, or a rhombus array region, that is, the shape of the holes forming the array of the patterned array region 30 includes square, circular, or rhombus.

[0175] Further, please see Figure 3 The distance c between the two columns of patterns in the patterned array region 30 is 1-10 μm.

[0176] Further, please see Figure 3 The dimensions of the patterned array region 30 are (5-20)μm×100μm, where 5μm≦a≤20μm, and b is designed according to the device application scenario, for example, it can be 100μm.

[0177] Furthermore, the second preset thickness is 5-20nm, that is, the depth of the patterned array region 30 is 5-20nm.

[0178] Furthermore, the source electrode 60 and the drain electrode 70 include a pre-deposited layer, a contact layer, a catalyst layer, a barrier layer and a cap layer stacked sequentially from bottom to top.

[0179] Preferably, the material of the pre-deposited layer can be Si, Ge, or Si. x Ge y Si x Ti y Si x Ta y Al z or Si x Ti y Al z Where X, Y, and Z represent the atomic ratios of different elements.

[0180] Preferably, the material of the pre-deposited layer is Si. x Ta yAl z The alloy has a thickness of 20nm-100nm, with Si content of 10%-50%, Ta content of 10%-30%, and Al content of 20%-80%.

[0181] Preferably, the material of the contact layer can be Ti, Ta, or Ti x Al y Or Ta x Al y .

[0182] Preferably, the catalyst layer can be made of Al.

[0183] Preferably, the material of the barrier layer can be Ta, Ti, Ni or Mo.

[0184] Preferably, the material of the cap layer can be Au, TiN, TiW, W, TiC, or TaN.

[0185] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0186] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0187] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for preparing GaN-based HEMTs using a local pre-etching ohmic process, characterized in that, include: Select an epitaxial substrate (10), the epitaxial substrate comprising a substrate layer (101), a nucleation layer (102), a buffer layer (103) and a barrier layer (104) stacked sequentially from bottom to top; The active region of the epitaxial substrate (10) is etched from both ends to the buffer layer (103) of a first preset thickness to form an electrically isolated region (20). The first preset thickness refers to the depth etched downward from the upper surface of the buffer layer, and the first preset thickness is less than the thickness of the buffer layer (103). The barrier layer (104) of a second preset thickness is etched to form two sets of patterned array regions (30), the second preset thickness being less than the thickness of the barrier layer (104); An alloy pre-deposited layer (40) is deposited within the two sets of patterned array regions (30), the alloy pre-deposited layer (40) being Si. x Ta y Al z alloy; Ohmic metal (50) is deposited on the source electrode pattern region and the drain electrode pattern region located on the barrier layer (104) and the alloy pre-deposition layer (40) respectively to form the source electrode (60) and the drain electrode (70); A passivation layer (80) is grown on the barrier layer (104), the source electrode (60), and the drain electrode (70); The passivation layer (80) is etched to the surface of the barrier layer (104) to form a gate trench (90); Gate electrode metal is deposited in the gate trench (90) to form a gate electrode (100), which is located between the source electrode (60) and the drain electrode (70).

2. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, Etching the buffer layer (103) from both ends of the active region of the epitaxial substrate (10) to a first predetermined thickness to form an electrically isolated region (20) includes: Photolithographically etched isolation regions on the barrier layer (104); The barrier layer (104) of the isolation region of the epitaxial substrate (10) is dry etched using ICP process to the buffer layer (103) of the first preset thickness to form an electrically isolated region (20); Remove the first photoresist outside the electrically isolated region (20).

3. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, Before etching the barrier layer (104) to a second predetermined thickness to form two sets of patterned array regions (30), the process further includes: Si was prepared using the hot isostatic pressing method of powder metallurgy. x Ta y Al z alloy.

4. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, The barrier layer (104) of a second predetermined thickness is etched to form two sets of patterned array regions (30), including: A first release adhesive is prepared on the barrier layer (104); A second photoresist is prepared on the first release adhesive; The second photoresist in the two array regions is exposed; The second photoresist after exposure is developed to remove the first stripper and the second photoresist in the array area; The barrier layer (104) of the second preset thickness of the array region is etched using an ICP process to form two sets of patterned array regions (30).

5. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, An alloy pre-deposited layer (40) is deposited within the two sets of patterned array regions (30), including: Si was deposited in the two patterned array regions (30) using magnetron sputtering or electron beam evaporation. x Ta y Al z Alloy, to form an alloy pre-deposited layer (40).

6. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, Ohmic metal (50) is deposited on the source electrode pattern region and the drain electrode pattern region located on the barrier layer (104) and the alloy pre-deposition layer (40), respectively, to form the source electrode (60) and the drain electrode (70), including: A second release adhesive is prepared on the barrier layer (104) and the alloy pre-deposited layer (40); A third photoresist is prepared on the second release adhesive; The third photoresist in the source electrode pattern area and the drain electrode pattern area is exposed; The third photoresist after exposure is developed to remove the second and third release adhesives from the source electrode pattern area and the drain electrode pattern area; The ohmic metal (50) is deposited on the barrier layer (104) and the alloy pre-deposition layer (40) in the source electrode pattern region and the drain electrode pattern region using a magnetron sputtering process. The ohmic metal (50) includes a pre-deposition layer, a contact layer, a catalyst layer, a barrier layer and a cap layer stacked sequentially from bottom to top. The alloy pre-deposited layer (40) and the ohmic metal (50) are annealed using a rapid annealing process to sink them to the buffer layer (103) to form the source electrode (60) and the drain electrode (70).

7. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, A passivation layer (80) is grown on the barrier layer (104), the source electrode (60), and the drain electrode (70), comprising: A passivation layer (80) is prepared on the barrier layer (104), the source electrode (60) and the drain electrode (70) using a PECVD process.

8. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, Etching the passivation layer (80) to the surface of the barrier layer (104) to form a gate trench (90) includes: A third release adhesive is prepared on the passivation layer (80); A fourth photoresist is prepared on the third release adhesive; The fourth photoresist in the gate electrode pattern area is exposed; The fourth photoresist after exposure is developed to remove the third stripper and the fourth photoresist within the gate electrode pattern area; The passivation layer (80) of the gate electrode pattern region is dry etched to the surface of the barrier layer (104) using an ICP process to form a gate trench (90).

9. The method for preparing GaN-based HEMTs using a local pre-etching ohmic process according to claim 1, characterized in that, Depositing gate electrode metal within the gate trench (90) to form a gate electrode (100) includes: The gate electrode metal is deposited in the gate trench (90) by magnetron sputtering to form the gate electrode (100).

10. A GaN-based HEMT employing a local pre-etching ohmic process, characterized in that, The GaN-based HEMT is prepared using the preparation method according to any one of claims 1 to 9, comprising: Epitaxial substrate (10), the epitaxial substrate includes a substrate layer (101), a nucleation layer (102), a buffer layer (103) and a barrier layer (104) stacked sequentially from bottom to top; Two sets of patterned array regions (30) with a second preset thickness are provided in the barrier layer (104); An alloy pre-deposited layer (40) is provided in each of the two sets of patterned array regions (30); Active electrodes (60) and drain electrodes (70) are respectively disposed on the two alloy pre-deposited layers (40) and the barrier layer (104); A passivation layer (80) is provided on the barrier layer (104), the source electrode (60) and the drain electrode (70); A gate electrode (100) is disposed in the gate trench (90) of the passivation layer (80).

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