Gallium oxide vertical device and method of making the same

Abstract

The application discloses a gallium oxide vertical device and a preparation method thereof. The gallium oxide vertical device comprises an epitaxial structure, a cathode and an anode matched with the epitaxial structure, the epitaxial structure comprises a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an interlayer and a p-type nitride epitaxial layer which are sequentially stacked, the lightly doped n-type Ga2O3 drift region, the interlayer and the p-type nitride epitaxial layer form a p-i-n structure, the cathode forms an ohmic contact with the heavily doped n-type Ga2O3 substrate, and the anode forms an ohmic contact with the p-type nitride epitaxial layer, wherein the material of the interlayer is an Al-containing compound, and the surface layer region of the lightly doped n-type Ga2O3 drift region close to the interlayer also has Al elements, the Al elements are diffused into the lightly doped n-type Ga2O3 drift region in the bonding process under high pressure.

Description

Technical Field

[0001] This invention relates in particular to a gallium oxide vertical device and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] Currently, power semiconductor devices based on gallium nitride (GaN), a third-generation wide-bandgap semiconductor, have been widely researched and applied. Due to its excellent material properties such as a large bandgap (3.4 eV) and high thermal conductivity, its power semiconductor devices have high breakdown voltage and can be used in environments with high temperature and high radiation. However, the large-scale mass production of GaN-based vertical transistor devices is difficult due to the cost of its self-supporting substrate.

[0003] Gallium oxide has multiple crystal forms, including α, β, γ, δ, and ε. Among them, β-Ga₂O₃ exhibits the strongest thermal stability and is the stable phase for the other four structures at high temperatures. Therefore, β-Ga₂O₃ materials are mainly studied for high-power applications. β-Ga₂O₃ has an ultra-large bandgap (4.8–4.9 eV) and a breakdown field strength of 7–8 MV / cm. Furthermore, gallium oxide provides a large-size self-supporting substrate, making it a promising candidate for large-scale device mass production. However, gallium oxide has low thermal conductivity.

[0004] However, current technologies lack sufficient research on achieving p-type doping with gallium oxide, resulting in the inability to fabricate gallium oxide pn junction diodes; most fabrications have only yielded Schottky diodes. Figure 1 Although there have been reports of using p-type oxides, such as p-NiO and n-Ga2O3, to construct pn heterojunctions ( Figure 2 Commonly used methods include sol-gel and sputtering, but issues remain regarding p-NiO crystal quality and hole concentration, and the material's interface properties need improvement, preventing the full realization of Ga2O3's theoretical advantages. Although there have been reports of Ga2O3 epitaxy on GaN, its different crystal structure and lattice constant prevent the production of high-quality heteroepitaxial films.

[0005] In general, existing technologies have addressed the challenge of achieving p-type Ga2O3 by constructing pn heterojunctions. However, the reported p-type oxide heterojunction structures and fabrication methods all have several limitations. P-type oxides obtained through sputtering or spin-coating suffer from issues with crystal quality and material properties. Mechanical exfoliation of Ga2O3 is only suitable for laboratory fabrication. Furthermore, devices fabricated through high-temperature bonding face numerous challenges in terms of performance and reliability, and the high temperatures reduce process compatibility. Summary of the Invention

[0006] The main objective of this invention is to provide a gallium oxide vertical device and its fabrication method, thereby overcoming the shortcomings of the prior art.

[0007] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0008] A first aspect of this invention provides a gallium oxide vertical device, including an epitaxial structure and a cathode and an anode matched with the epitaxial structure. The epitaxial structure includes a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an insertion layer, and a p-type nitride epitaxial layer stacked sequentially. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. The cathode forms an ohmic contact with the heavily doped n-type Ga2O3 substrate, and the anode forms an ohmic contact with the p-type nitride epitaxial layer. The insertion layer is made of an Al-containing compound, and the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer also contains Al elements, which diffuse into the lightly doped n-type Ga2O3 drift region during high-voltage bonding of the insertion layer.

[0009] A second aspect of this invention provides a method for fabricating a gallium oxide vertical device, comprising:

[0010] A first epitaxial structure is provided, the first epitaxial structure comprising a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region and an insertion layer stacked together, wherein the material of the insertion layer is an Al-containing compound;

[0011] A second epitaxial structure is provided, the second epitaxial structure including a p-type nitride epitaxial layer, and the p-type nitride epitaxial layer is subjected to plasma-activated surface treatment;

[0012] The insertion layer of the first epitaxial structure is directly bonded to the p-type nitride epitaxial layer of the second epitaxial structure. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. During the bonding process, some Al in the insertion layer diffuses to the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer.

[0013] A cathode is formed on the back side of the heavily doped n-type Ga2O3 substrate, and an anode is formed on the surface of the p-type nitride epitaxial layer.

[0014] Compared with the prior art, the advantages of the present invention include:

[0015] This invention achieves a high-quality p-type nitride / high-quality n-type gallium oxide heterojunction material structure and pn heterojunction device by epitaxially growing high-quality p-type nitride and high-quality n-type gallium oxide layers respectively and then using a low-temperature bonding method. The device has strong process compatibility, can realize large-scale device fabrication, and improves the uniformity and reliability of the device.

[0016] This invention can effectively realize gallium oxide pn heterojunction diodes. Whether it is a p-type epitaxial layer or an n-type epitaxial layer, high quality and controllable epitaxy can be obtained, avoiding device uniformity and reliability problems caused by insufficient crystal quality or difficulty in control. The low-temperature bonding process ensures process compatibility. Since the p-type nitride epitaxial layer can be epitaxially grown over a large area on a Si substrate, efficient large-scale device fabrication can be achieved. The method for forming pn heterojunctions is flexible and convenient, and complex device structures can be realized.

[0017] This invention utilizes the diffusion of Al elements into the lightly doped n Ga2O3 drift region during the high-voltage bonding process of the Al2O3 / AlN intercalation layer. This not only improves the bonding interface quality but also increases the carrier concentration, reduces the on-resistance of the device, and further increases the width of the depletion region, thereby improving the device's breakdown voltage performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a conventional Schottky diode structure;

[0019] Figure 2 This is a schematic diagram of a conventional p-NiO / n-Ga2O3 heterojunction structure;

[0020] Figure 3 This is a schematic diagram of the structure of a gallium oxide vertical device provided in a typical embodiment of the present invention;

[0021] Figure 4a , Figure 4b , Figure 4c , Figure 5a , Figure 5b , Figure 6a , Figure 6b , Figure 6c , Figure 6d These are schematic diagrams of an epitaxial intermediate formed during the fabrication of a gallium oxide vertical device in a typical embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of another gallium oxide vertical device provided in a typical embodiment of the present invention. Detailed Implementation

[0023] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate the technical solution, its implementation process, and its principles.

[0024] A first aspect of this invention provides a gallium oxide vertical device, including an epitaxial structure and a cathode and an anode matched with the epitaxial structure. The epitaxial structure includes a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an insertion layer, and a p-type nitride epitaxial layer stacked sequentially. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. The cathode forms an ohmic contact with the heavily doped n-type Ga2O3 substrate, and the anode forms an ohmic contact with the p-type nitride epitaxial layer. The insertion layer is made of an Al-containing compound, and the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer also contains Al elements, which diffuse into the lightly doped n-type Ga2O3 drift region during high-voltage bonding of the insertion layer.

[0025] Furthermore, the insertion layer is an Al2O3 insertion layer or an AlN insertion layer.

[0026] Furthermore, the thickness of the insertion layer is 1 nm to 5 nm.

[0027] Furthermore, the material of the p-type nitride epitaxial layer includes at least one or a combination of two or more of p-GaN, p-AlGaN, and p-InGaN.

[0028] Furthermore, the thickness of the p-type nitride epitaxial layer is 10 nm to 1 μm.

[0029] Furthermore, the p-type impurities within the p-type nitride epitaxial layer are uniformly or gradually distributed.

[0030] Furthermore, the doping concentration of p-type impurities in the p-type nitride epitaxial layer gradually decreases from the side of the p-type nitride epitaxial layer near the insertion layer to the side near the anode.

[0031] Furthermore, a dielectric layer is disposed between the p-type nitride epitaxial layer and the anode. The dielectric layer is made of any one or a combination of two or more of AlN, Al2O3, and BN, and the thickness of the dielectric layer is 1 nm to 10 nm.

[0032] Furthermore, this gallium oxide vertical device can be a diode or a transistor, etc.

[0033] A second aspect of this invention provides a method for fabricating a gallium oxide vertical device, comprising:

[0034] A first epitaxial structure is provided, the first epitaxial structure comprising a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region and an insertion layer stacked together, wherein the material of the insertion layer is an Al-containing compound;

[0035] A second epitaxial structure is provided, the second epitaxial structure including a p-type nitride epitaxial layer, and the p-type nitride epitaxial layer is subjected to plasma-activated surface treatment;

[0036] The insertion layer of the first epitaxial structure is directly bonded to the p-type nitride epitaxial layer of the second epitaxial structure. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. During the bonding process, some Al in the insertion layer diffuses to the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer.

[0037] A cathode is formed on the back side of the heavily doped n-type Ga2O3 substrate, and an anode is formed on the surface of the p-type nitride epitaxial layer.

[0038] In a more specific embodiment, the method for fabricating the gallium oxide vertical device includes:

[0039] A first substrate is provided, a nitride buffer layer is grown on the first substrate, a p-type nitride epitaxial layer is grown on the nitride buffer layer, a first insulating dielectric layer is formed on the p-type nitride epitaxial layer, and a first metal layer is formed on the first insulating dielectric layer.

[0040] A second substrate is provided, a second insulating dielectric layer is formed on the second substrate, and a second metal layer is formed on the second insulating dielectric layer;

[0041] The first metal layer and the second metal layer are bonded together.

[0042] After removing the first substrate and the nitride buffer layer, the remaining portion serves as the second epitaxial structure;

[0043] Furthermore, after directly bonding the insertion layer of the first epitaxial structure to the p-type nitride epitaxial layer of the second epitaxial structure, the portion of the second epitaxial structure other than the p-type nitride epitaxial layer is removed.

[0044] Furthermore, the insertion layer is an Al2O3 insertion layer or an AlN insertion layer.

[0045] Furthermore, the thickness of the insertion layer is 1 nm to 5 nm.

[0046] Furthermore, the preparation method specifically includes: forming a lightly doped n-type Ga2O3 drift region on a heavily doped n-type Ga2O3 substrate, forming an Al layer on the lightly doped n-type Ga2O3 drift region, and oxidizing the Al layer to form an Al2O3 insertion layer.

[0047] Furthermore, the material of the p-type nitride epitaxial layer includes at least one or a combination of two or more of p-GaN, p-AlGaN, and p-InGaN.

[0048] Furthermore, the thickness of the p-type nitride epitaxial layer is 10 nm to 1 μm.

[0049] Furthermore, the p-type impurities within the p-type nitride epitaxial layer are uniformly or gradually distributed.

[0050] Furthermore, the doping concentration of p-type impurities in the p-type nitride epitaxial layer gradually decreases from the side of the p-type nitride epitaxial layer near the insertion layer to the side near the anode.

[0051] Furthermore, the method for fabricating the gallium oxide vertical device further includes: firstly, forming a dielectric layer on the p-type nitride epitaxial layer, and then forming an anode on the dielectric layer. The dielectric layer is made of any one or a combination of two or more of AlN, Al2O3, and BN, and the thickness of the dielectric layer is 1 nm to 10 nm.

[0052] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor epitaxial growth equipment and its process, bonding equipment and its process, metal deposition equipment and its process used in the embodiments of the present invention are all known in the art.

[0053] For a more specific implementation plan, please refer to Figure 3 A gallium oxide vertical device comprises, from bottom to top, a cathode ohmic contact metal (i.e., cathode, the same below), a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an intrinsic Al2O3 insertion layer, a p-type nitride epitaxial layer, and an anode ohmic contact metal (i.e., anode, the same below). The p-type nitride epitaxial layer and the n-type Ga2O3 layer form a pn junction. When a forward voltage is applied to the anode, the depletion region of the pn junction shrinks, generating a forward conduction current, and the device is in the on state. When a reverse voltage is applied to the anode, the depletion region of the pn junction widens, no current is generated, and the device is in the off state.

[0054] Specifically, the thickness of the lightly doped n-type Ga2O3 drift region is 200 nm, the thickness of the p-type nitride epitaxial layer is 10 nm to 1 μm, and the material of the p-type nitride epitaxial layer includes at least one or a combination of two or more of p-GaN, p-AlGaN, and p-InGaN. The thickness of the Al2O3 insertion layer or AlN insertion layer is 1 nm to 5 nm. The cathode ohmic contact metal and the anode ohmic contact metal can be Ti / Au = 50 / 100 nm.

[0055] Specifically, gallium oxide vertical devices may also include junction termination structures such as high-resistivity junction terminations, field plates, and field confinement rings.

[0056] For a more specific implementation plan, please refer to Figure 7 In gallium oxide vertical devices, the intrinsic Al2O3 insertion layer can also be replaced with an AlN insertion layer. The choice between Al2O3 and AlN as the insertion layer depends on the specific device requirements and operating environment.

[0057] Specifically, the Al2O3 / AlN intercalation layer serves as the intrinsic layer in the pin structure formed by the lightly doped n-type Ga2O3 drift region, the intercalation layer, and the p-type nitride epitaxial layer. The Al2O3 / AlN intercalation layer improves the device's breakdown voltage by increasing the width of the depletion region. By providing a non-conductive region, it extends the depth of the depletion region, enabling the device to avoid breakdown and maintain good performance under high reverse voltages. Besides increasing the depletion region width, the Al2O3 layer may also improve the interface quality between p-GaN and n-Ga2O3. The good lattice matching between Al2O3 and both Ga2O3 and GaN helps reduce the interface defect density, further enhancing the device's stability and breakdown voltage. Furthermore, during high-voltage bonding, Al diffusion occurs from the Al2O3 / AlN intercalation layer into the lightly doped n-type Ga2O3 drift region, which is highly beneficial for improving the bonding interface quality.

[0058] Specifically, the fabrication method of this gallium oxide vertical device includes the following steps:

[0059] 1) Using epitaxial techniques such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE), in heavily doped n... + Lightly doped n-growth substrates are grown on Ga2O3 substrates. - Ga2O3 drift region, such as Figure 4a As shown;

[0060] A nitride buffer layer and a high-quality p-type nitride epitaxial layer are grown on substrate one (i.e., the aforementioned first substrate, the same below). Then, an insulating dielectric layer (SiO2, SiN, Al2O3, BN, etc.) is deposited on the surface of the p-type nitride epitaxial layer using dielectric layer deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Finally, a metal (Au, Cu, Al, etc.) is deposited on the insulating dielectric layer using metal deposition techniques such as electron beam evaporation or sputtering. Figure 4b As shown.

[0061] Specifically, the substrate can be made of materials such as Si, sapphire, GaN, BN, or graphene, while the nitride buffer layer can be made of materials such as AlN. The nitride buffer layer can alleviate lattice mismatch and reduce the influence of interface states, thus obtaining a high-quality epitaxial layer. The p-type nitride epitaxial layer can be made of p-GaN, p-AlGaN, or p-InGaN, or a combination thereof. The doping concentration of the p-type nitride epitaxial layer can be uniform or gradually varied. If it is gradually varied, the concentration is increased first and then decreased during epitaxy. The activation of p-type impurities in the p-type nitride epitaxial layer can be performed in multiple stages, such as activation in the epitaxial chamber, activation after bonding, activation after the formation of a heterojunction, or activation after the device fabrication is complete.

[0062] An insulating dielectric layer (SiO2, SiN, Al2O3, BN, etc.) is deposited on the surface of a second substrate (i.e., the second substrate, hereinafter the same) using dielectric layer deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, a metal (Au, Cu, Al, etc.) is deposited on the insulating dielectric layer using metal deposition techniques such as electron beam evaporation or sputtering. Figure 4c As shown, epitaxial growth is performed on substrate 1 and substrate 2 respectively, based on existing epitaxial growth techniques, which can obtain higher quality material layers on suitable substrates.

[0063] 2) Using a low-temperature bonding method, Figure 4b and Figure 4c The metal surfaces of the structure are bonded together as one, such as Figure 5a As shown, the bonding temperature is 350℃.

[0064] The substrate is removed entirely using etching (e.g., deep silicon etching), laser lift-off, or direct lift-off. A high-selectivity CMP (chemical mechanical polishing) process is then used to remove the nitride buffer layer, leaving only the high-quality p-type nitride epitaxial layer. Figure 5b As shown, the CMP (Chemical Mechanical Polishing) grinding and polishing process uses a white polishing pad of 6 kg for 120 min. The polishing solution may contain: H2O = 1:1, NaOH-SiO2 particles, and pH ~10.

[0065] 3) Using an inductively coupled plasma etching machine, low-damage H or N plasma is used to perform plasma activation surface treatment on the surface of the p-type nitride epitaxial layer, such as... Figure 6a As shown, specifically, when performing plasma activation surface treatment on the surface of the p-type nitride epitaxial layer using H plasma, the H2 flow rate is 30 sccm, the RF power is 2W, the ICP power is 300W, the temperature is 25℃, the pressure is 8mTorr, and the DC bias is 10V.

[0066] An Al layer with a thickness of 1–5 nm was deposited on the surface of the lightly doped n Ga2O3 drift region using electron beam deposition, and the Al was oxidized to an Al2O3 insertion layer by ultraviolet ozone treatment.

[0067] The p-type nitride epitaxial layer with activated surface treatment is directly bonded to the Ga2O3 epitaxial structure with Al2O3 intercalation layer on the surface, such as Figure 6b As shown, during high-pressure bonding, the Al2O3 intercalation layer diffuses Al into the drift region of lightly doped n-Ga2O3. The diffusion depth and concentration are affected by the time and pressure of the high-pressure process. Higher pressure and longer time result in deeper diffusion depths, which is highly beneficial for improving the bonding interface quality. Simultaneously, the Al2O3 intercalation layer can also serve as the i-layer in the p-GaN / Al2O3 / n-Ga2O3 pin structure, further increasing the depletion region width and thus improving the device's breakdown voltage. The thickness of the Al2O3 intercalation layer can also indirectly affect the carrier concentration through interface defects or interface charges, increasing the carrier concentration and reducing the device's on-resistance. Therefore, a thinner alumina intercalation layer is preferable, as a thicker alumina layer may shield the electric field, reducing carrier migration and leading to a lower carrier concentration. Of course, an AlN intercalation layer can also replace the Al2O3 intercalation layer.

[0068] It should be noted that the aluminum oxide formed by oxidation generally has directionality, which can alleviate lattice mismatch between materials.

[0069] 4) Remove substrate 2 and the insulating dielectric layer and bonding metal between the p-type nitride epitaxial layer and substrate 2 to obtain the p-type nitride epitaxial layer / Al2O3 insertion layer / n - Ga2O3 drift region / heavily doped n + Epitaxial structures on Ga2O3 substrates, such as Figure 6c As shown.

[0070] Typically, the insulating dielectric layer between the substrate and the p-type nitride epitaxial layer is made of SiN, SiO2, or a combination of both, and can be removed by BOE etching solution.

[0071] 5) By using metal deposition processes such as electron beam evaporation or sputtering, metal is deposited on the surface of the p-type nitride epitaxial layer and the back side of the heavily doped n+Ga2O3 substrate, respectively, and then annealed to form ohmic contacts, a pn heterojunction diode can be obtained.

[0072] This invention achieves a high-quality p-type nitride / high-quality n-type gallium oxide heterojunction material structure and pn heterojunction device by epitaxially growing high-quality p-type nitride and high-quality n-type gallium oxide layers respectively and then using a low-temperature bonding method. The device has strong process compatibility, can realize large-scale device fabrication, and improves the uniformity and reliability of the device.

[0073] This invention can effectively realize gallium oxide pn heterojunction diodes. Whether it is a p-type epitaxial layer or an n-type epitaxial layer, high quality and controllable epitaxy can be obtained, avoiding device uniformity and reliability problems caused by insufficient crystal quality or difficulty in control. The low-temperature bonding process ensures process compatibility. Since the p-type nitride epitaxial layer can be epitaxially grown over a large area on a Si substrate, efficient large-scale device fabrication can be achieved. The method for forming pn heterojunctions is flexible and convenient, and complex device structures can be realized.

[0074] This invention utilizes the diffusion of Al elements into the lightly doped n Ga2O3 drift region during the high-voltage bonding process of the Al2O3 / AlN intercalation layer. This not only improves the bonding interface quality but also increases the carrier concentration, reduces the on-resistance of the device, and further increases the width of the depletion region, thereby improving the device's breakdown voltage performance.

[0075] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A gallium oxide vertical-type device, comprising an epitaxial structure and a cathode and an anode matched with the epitaxial structure, characterized in that: The epitaxial structure includes a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an insertion layer, and a p-type nitride epitaxial layer stacked sequentially. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. The cathode forms an ohmic contact with the heavily doped n-type Ga2O3 substrate, and the anode forms an ohmic contact with the p-type nitride epitaxial layer. The insertion layer is made of an Al compound, and the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer also contains Al elements. The Al elements diffuse into the lightly doped n-type Ga2O3 drift region during the high-voltage bonding process of the insertion layer.

2. The gallium oxide vertical device according to claim 1, characterized in that: The insertion layer is an Al2O3 insertion layer or an AlN insertion layer.

3. The gallium oxide vertical device according to claim 1 or 2, characterized in that: The thickness of the insertion layer is 1 nm to 5 nm.

4. The gallium oxide vertical device according to claim 1, characterized in that: The material of the p-type nitride epitaxial layer includes at least one or a combination of two or more of p-GaN, p-AlGaN, and p-InGaN; Preferably, the thickness of the p-type nitride epitaxial layer is 10 nm to 1 μm; Preferably, the p-type impurities in the p-type nitride epitaxial layer are uniformly distributed or gradually distributed; Preferably, the doping concentration of p-type impurities in the p-type nitride epitaxial layer gradually decreases from the side of the p-type nitride epitaxial layer near the insertion layer to the side near the anode.

5. The gallium oxide vertical device according to claim 1, characterized in that: A dielectric layer is further disposed between the p-type nitride epitaxial layer and the anode. The dielectric layer is made of any one or a combination of two or more of AlN, Al2O3, and BN, and the thickness of the dielectric layer is 1 nm to 10 nm.

6. A method for fabricating a gallium oxide vertical device, characterized in that, include: A first epitaxial structure is provided, the first epitaxial structure comprising a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region and an insertion layer stacked together, wherein the material of the insertion layer is an Al compound. A second epitaxial structure is provided, the second epitaxial structure including a p-type nitride epitaxial layer, and the p-type nitride epitaxial layer is subjected to plasma-activated surface treatment; The insertion layer of the first epitaxial structure is directly bonded to the p-type nitride epitaxial layer of the second epitaxial structure. The lightly doped n-type Ga2O3 drift region, the insertion layer, and the p-type nitride epitaxial layer form a pin structure. During the bonding process, a portion of Al in the insertion layer diffuses to the surface region of the lightly doped n-type Ga2O3 drift region near the insertion layer. A cathode is formed on the back side of the heavily doped n-type Ga2O3 substrate, and an anode is formed on the surface of the p-type nitride epitaxial layer.

7. The method for fabricating a gallium oxide vertical device according to claim 6, characterized in that, include: A first substrate is provided, a nitride buffer layer is grown on the first substrate, a p-type nitride epitaxial layer is grown on the nitride buffer layer, a first insulating dielectric layer is formed on the p-type nitride epitaxial layer, and a first metal layer is formed on the first insulating dielectric layer. A second substrate is provided, a second insulating dielectric layer is formed on the second substrate, and a second metal layer is formed on the second insulating dielectric layer; The first metal layer and the second metal layer are bonded together. After removing the first substrate and the nitride buffer layer, the remaining portion serves as the second epitaxial structure; Furthermore, after directly bonding the insertion layer of the first epitaxial structure to the p-type nitride epitaxial layer of the second epitaxial structure, the portion of the second epitaxial structure other than the p-type nitride epitaxial layer is removed.

8. The method for fabricating a gallium oxide vertical device according to claim 6, characterized in that: The insertion layer is an Al2O3 insertion layer or an AlN insertion layer, preferably, the thickness of the insertion layer is 1 nm to 5 nm; Preferably, the preparation method specifically includes: forming a lightly doped n-type Ga2O3 drift region on a heavily doped n-type Ga2O3 substrate, forming an Al layer on the lightly doped n-type Ga2O3 drift region, and oxidizing the Al layer to form an Al2O3 insertion layer.

9. The method for fabricating a gallium oxide vertical device according to claim 6, characterized in that: The material of the p-type nitride epitaxial layer includes at least one or a combination of two or more of p-GaN, p-AlGaN, and p-InGaN; Preferably, the thickness of the p-type nitride epitaxial layer is 10 nm to 1 μm; Preferably, the p-type impurities in the p-type nitride epitaxial layer are uniformly distributed or gradually distributed; Preferably, the doping concentration of p-type impurities in the p-type nitride epitaxial layer gradually decreases from the side of the p-type nitride epitaxial layer near the insertion layer to the side near the anode.

10. The method for fabricating a gallium oxide vertical device according to claim 6, characterized in that, Also includes: First, a dielectric layer is formed on the p-type nitride epitaxial layer, and then an anode is formed on the dielectric layer. The dielectric layer is made of any one or a combination of two or more of AlN, Al2O3, and BN, and the thickness of the dielectric layer is 1 nm to 10 nm.

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