Semiconductor structure and preparation method thereof

Abstract

The present application relates to a semiconductor structure and a method for preparing the same, wherein the semiconductor structure includes a substrate, a stacked structure, and a field plate structure, wherein a side of the stacked structure away from the substrate is provided with a source, a drain, and a gate located therebetween; the field plate structure is located on a side of the source and the gate away from the stacked structure, and the field plate structure includes a field plate body, a conductive bridge column, and a field plate connector, wherein the field plate body is located between the source and the drain; the field plate connector is located on a surface of the source away from the stacked structure; the conductive bridge column is located between the field plate body and the field plate connector, and the number of the field plate connectors is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected one-to-one with the field plate connectors. The present application increases the breakdown voltage of the semiconductor device and reduces the leakage current of the gate while taking into account the frequency characteristics and stability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] III-V compound semiconductor materials, including semiconductor materials based on gallium nitride, semiconductor materials based on gallium arsenide, and semiconductor materials based on indium phosphide, etc., generally have large differences in their band gap widths. People often use this feature to form various heterojunction structures. This heterojunction structure has a characteristic that quantum potential wells and high-concentration two-dimensional electron gas can be generated near the heterojunction interface. This two-dimensional electron gas is bound in the quantum potential well, realizing the spatial separation of carriers and ionized impurities, reducing the Coulomb force of ionized impurities on carriers, eliminating the influence of ionization scattering centers, and thus greatly improving the carrier mobility. Therefore, semiconductor materials based on III-V compounds have excellent electrical properties.

[0003] High Electron Mobility Transistor (HEMT) based on III-V compounds has the characteristics of high mobility, high carrier concentration, high frequency, high temperature, high voltage and high power. It is widely used in 5G communications, microwave, millimeter wave and radar systems, and is one of the current research hotspots in the field of semiconductor devices.

[0004] However, how to further increase the area of ​​the depletion region of the semiconductor device, increase the breakdown voltage of the device, modulate the distribution of the electric field lines in the depletion region of the barrier layer, reduce the leakage current of the gate, and ensure the frequency characteristics and stability of the semiconductor device has become one of the technical problems that need to be solved urgently in the field of semiconductor technology. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the technical problems in the above-mentioned background technology, so as to increase the breakdown voltage of the semiconductor device, reduce the leakage current of the gate, and take into account the frequency characteristics and stability of the semiconductor device.

[0006] To achieve the above and other objectives, the first aspect of the present application provides a semiconductor structure, comprising:

[0007] substrate;

[0008] a stacked structure located on one side of the substrate, comprising a plurality of semiconductor layers stacked in sequence, wherein a source electrode, a gate electrode, and a drain electrode are provided on a side of the stacked structure away from the substrate, and the gate electrode is located between the source electrode and the drain electrode;

[0009] A field plate structure is located on a side of the source and the gate away from the stacked structure, the field plate structure comprising a field plate body, a conductive bridge column, and a field plate connector. The field plate body is located between the source and the drain; the field plate connector is located on a surface of the source away from the stacked structure; the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body and the other end is connected to the field plate connector.

[0010] There is at least one field plate connector, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence.

[0011] In the semiconductor structure in the above embodiment, after a source, a drain, and a gate located between the source and the drain are provided on a side of a stacked structure located on a substrate away from the substrate, a field plate structure is formed on a side of the source and the gate away from the stacked structure, and the field plate structure is used to increase the area of ​​the depletion region to increase the breakdown voltage of the semiconductor device. At the same time, the field plate structure is used to modulate the distribution of the electric field lines in the depletion region of the barrier layer to reduce the leakage current of the gate. By setting the field plate structure to include a field plate body, a conductive bridge column and a field plate connector, the field plate body is located between the source and the drain, the field plate connector is located on the surface of the source away from the stacked structure, the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body and the other end is connected to the field plate connector, the number of the field plate connector is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence, thereby avoiding the introduction of the field plate structure leading to an increase in the gate-source capacitance Cgs of the semiconductor device, thereby effectively ensuring the frequency characteristics, stability and reliability of the manufactured semiconductor device.

[0012] In one embodiment, the field plate body and the conductive bridge column are integrally formed; or the field plate body, the conductive bridge column and the field plate connector are integrally formed.

[0013] In one embodiment, the length of the field plate connector in the extending direction of the field plate body is greater than the length of the conductive bridge column in the extending direction of the field plate body.

[0014] In one embodiment, the length of the field plate connector in the extension direction of the field plate body is greater than or equal to twice the length of the conductive bridge column in the extension direction of the field plate body, and less than 25 times the length of the conductive bridge column in the extension direction of the field plate body.

[0015] In one embodiment, the orthographic projection of the source electrode on the surface of the stacked structure completely covers the orthographic projection of the field plate contact on the surface of the stacked structure.

[0016] In one embodiment, the orthographic projection of the field plate contact on the surface of the stacked structure is located in a region where the orthographic projection of the source electrode on the surface of the stacked structure is close to 1 / 3 of the gate electrode.

[0017] In one embodiment, a source through hole is provided on the source electrode; the orthographic projection of the field plate connector on the surface of the stacked structure does not overlap with the orthographic projection of the source through hole on the surface of the stacked structure, or the overlapping area is less than 1 / 2 of the area of ​​the orthographic projection of the field plate connector on the surface of the stacked structure.

[0018] In one embodiment, the field plate contact is located on a side of the source through hole close to the gate.

[0019] In one embodiment, the semiconductor structure further includes a source interconnect metal; the source interconnect metal is connected to the source; and the field plate connector is located between the source and the source interconnect metal.

[0020] A second aspect of the present application provides a method for preparing a semiconductor structure, comprising:

[0021] providing a substrate;

[0022] forming a stacked structure comprising a plurality of sequentially stacked semiconductor layers on the substrate, and forming a drain, a source, and a gate on a side of the stacked structure away from the substrate, wherein the gate is located between the source and the drain;

[0023] A field plate structure is formed on a side of the source and the gate away from the stacked structure, and the field plate structure includes a field plate body, a conductive bridge column and a field plate connector, wherein the field plate body is located between the source and the drain; the field plate connector is located on the surface of the source away from the stacked structure; the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body, and the other end of the conductive bridge column is connected to the field plate connector; wherein the number of the field plate connectors is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence.

[0024] In the semiconductor structure preparation method in the above embodiment, after the source, the drain and the gate located between the source and the drain are arranged on the side of the stacked structure located on the substrate away from the substrate, a field plate structure is formed on the side of the source and the gate away from the stacked structure, and the field plate structure is used to increase the area of ​​the depletion region to increase the breakdown voltage of the semiconductor device. At the same time, the field plate structure is used to modulate the distribution of the electric field lines in the depletion region of the barrier layer to reduce the leakage current of the gate. By setting the field plate structure to include a field plate body, a conductive bridge column and a field plate connector, the field plate body is located between the source and the drain, the field plate connector is located on the surface of the source away from the stacked structure, the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body and the other end is connected to the field plate connector, the number of the field plate connector is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence, thereby avoiding the introduction of the field plate structure leading to an increase in the gate-source capacitance Cgs of the semiconductor device, thereby effectively ensuring the frequency characteristics, stability and reliability of the manufactured semiconductor device.

[0025] In one embodiment, the step of forming a field plate structure on a side of the source and the gate away from the stacked structure includes:

[0026] forming a first dielectric material layer, wherein the first dielectric material layer covers the gate, the source, and the drain;

[0027] removing the first dielectric material layer located on the surface of the source electrode, and the remaining first dielectric material layer constitutes a first dielectric layer;

[0028] forming the field plate body and the conductive bridge pillar on a surface of the first dielectric layer located between the source and the drain, away from the substrate, wherein the field plate body and the conductive bridge pillar are formed using the same material in the same process step;

[0029] The field plate contact is formed on the surface of the source.

[0030] In one embodiment, the step of forming a field plate structure on a side of the source and the gate away from the stacked structure includes:

[0031] forming a first dielectric material layer, wherein the first dielectric material layer covers the gate, the source, and the drain;

[0032] removing the first dielectric material layer located on the surface of the source electrode, and the remaining first dielectric material layer constitutes a first dielectric layer;

[0033] forming a second dielectric layer on a surface of the first dielectric layer away from the substrate, wherein the second dielectric layer covers the source electrode, the drain electrode and the first dielectric layer;

[0034] The field plate body, the conductive bridge column and the field plate connector are formed on the surface of the first dielectric layer between the source and the drain away from the substrate. The field plate body, the conductive bridge column and the field plate connector are formed using the same material in the same process step. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0036] Figure 1 Shown is a schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0037] Figure 2 Display as Figure 1 A schematic cross-sectional view of the semiconductor structure along the AA direction provided in the illustrated embodiment;

[0038] Figure 3a Shown is a schematic top view of a semiconductor structure provided in another embodiment of the present application;

[0039] Figure 3b Shown is a schematic top view of a semiconductor structure provided in yet another embodiment of the present application;

[0040] Figure 3c Shown is a schematic top view of a semiconductor structure provided in yet another embodiment of the present application;

[0041] Figure 4 Display as Figure 1 A schematic cross-sectional view of the semiconductor structure along the AA direction provided in the illustrated embodiment;

[0042] Figure 5 Shown is a schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0043] Figure 6 Shown is a schematic cross-sectional view of a structure obtained in step S202 of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0044] Figure 7-8bShown are a schematic cross-sectional view and a schematic top view of a structure obtained in step S204 of a semiconductor structure preparation method provided in an embodiment of the present application; wherein, Figure 8b for Figure 8a Schematic diagram of the cross-sectional structure along the BB direction;

[0045] Figures 9-12 Shown is a schematic diagram of the cross-sectional structure and a schematic diagram of the top view of the structure obtained in step S206 of a semiconductor structure preparation method provided in an embodiment of the present application; wherein, Figure 11b for Figure 11a Schematic diagram of the cross-sectional structure along the AA direction.

[0046] Explanation of the accompanying drawings: 10-substrate, 12-stacked structure, 121-nucleation layer, 122-channel layer, 123-barrier layer, 13-source, 14-drain, 15-gate, 16-first dielectric layer, 161-first dielectric material layer, 17-field plate structure, 171-field plate body, 172-conductive bridge column, 173-field plate connector, 18-source through hole. DETAILED DESCRIPTION

[0047] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] The embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the zones of the device and are not intended to limit the scope of the present application.

[0053] The multilayer structure described in the present application can be formed layer by layer or integrally; wherein two adjacent layers can be in contact or isolated from each other.

[0054] The field plate structure is a common structure in third-generation semiconductors. It increases the area of ​​the depletion region, increasing the device's breakdown voltage. It also modulates the distribution of electric field lines in the barrier layer's depletion region, reducing gate leakage current. While the use of a source field plate can increase the device's breakdown voltage, it also increases the device's gate-source capacitance, Cgs, which can degrade the device's frequency characteristics and even affect its reliability. Therefore, designing a field plate structure that balances device voltage-frequency performance and reliability remains a pressing issue.

[0055] See also Figures 1 to 12 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present application. Although the diagrams only show components related to the present application and are not drawn according to the number, shape, and size of components in actual implementation, the type, quantity, and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complex.

[0056] Please refer to Figure 1-Figure 2In one embodiment of the present application, a semiconductor structure is provided, including a substrate 10, a stacked structure 12 and a field plate structure 17. The stacked structure 12 is located on one side of the substrate 10 and includes multiple semiconductor layers stacked in sequence. A source 13, a drain 14 and a gate 15 are provided on the side of the stacked structure 12 away from the substrate 10. The gate 15 is located between the source 13 and the drain 14. The field plate structure 17 is located on the side of the source 13 and the gate 15 away from the stacked structure 12. The field plate structure 17 includes a field plate body 171, a conductive bridge column 172 and a field plate. Connector 173, the field plate body 171 is located between the source 13 and the drain 14; the field plate connector 173 is located on the surface of the source 13 away from the stacked structure 12; the conductive bridge column 172 is located between the field plate body 171 and the field plate connector 173, one end of the conductive bridge column 172 is connected to the field plate body 171 and the other end is connected to the field plate connector 173; wherein, the number of field plate connectors 173 is at least one, the number of conductive bridge columns 172 is the same as the number of field plate connectors 173, and the conductive bridge columns 172 are connected to the field plate connectors 173 in a one-to-one correspondence.

[0057] For details, please refer to Figure 1 and Figure 2 After a source 13, a drain 14, and a gate 15 located between the source 13 and the drain 14 are provided on a side of a stacked structure 12 located on a substrate 10 away from the substrate 10, a field plate structure 17 is formed on a side of the source 13 and the gate 15 away from the stacked structure 12. The field plate structure 17 is used to increase the area of ​​the depletion region to increase the breakdown voltage of the semiconductor device. At the same time, the field plate structure 17 is used to modulate the distribution of the electric field lines in the depletion region of the barrier layer to reduce the leakage current of the gate 15. By setting up a field plate structure 17 including a field plate body 171, a conductive bridge column 172 and a field plate connector 173, the field plate body 171 is located between the source 13 and the drain 14, the field plate connector 173 is located on the surface of the source 13 away from the stacked structure 12, and the conductive bridge column 172 is located between the field plate body 171 and the field plate connector 173. One end of the conductive bridge column 172 is connected to the field plate body 171 and the other end is connected to the field plate connector 173. There is at least one field plate connector 173, the number of the conductive bridge columns 172 is the same as the number of the field plate connectors 173, and the conductive bridge columns 172 and the field plate connectors 173 are connected one-to-one, thereby avoiding the introduction of the field plate structure 17 leading to an increase in the gate-source capacitance Cgs of the semiconductor device, thereby effectively ensuring the frequency characteristics, stability and reliability of the manufactured semiconductor device.

[0058] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the field plate body 171 and the conductive bridge columns 172 are integrally formed, that is, after the field plate body 171 and the conductive bridge columns 172 are formed, the field plate connectors 173 are formed.

[0059] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the field plate body 171 , the conductive bridge columns 172 and the field plate connectors 173 are integrally formed.

[0060] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the length of each field plate connector 173 in the extension direction OX of the field plate body 171 is greater than the length of the conductive bridge column 172 in the extension direction OX of the field plate body 171. The overall structural design of the field plate can reduce the gate-source capacitance while improving the stability of the field plate itself.

[0061] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the length of the field plate connector 173 along the extension direction OX of the field plate body 171 is greater than or equal to twice the length of the conductive bridge pillar 172 along the extension direction OX of the field plate body 171, and less than 25 times the length of the conductive bridge pillar 172 along the extension direction OX of the field plate body 171. The size of the field plate connector helps to improve the structural stability of the field plate itself while taking into account the frequency and reliability of the semiconductor device.

[0062] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, if the number of field plate connectors 173 and conductive bridge columns 172 is greater than or equal to 3, adjacent conductive bridge columns 172 can be arranged in parallel at equal intervals; the angle between the extension direction of the conductive bridge column 172 and the extension direction OX of the field plate body 171 is greater than zero. Preferably, the extension direction of the conductive bridge column 172 is perpendicular to the extension direction OX of the field plate body 171.

[0063] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the orthographic projection of the source electrode 13 on the surface of the stacked structure 12 completely covers the orthographic projection of the field plate contact 173 on the surface of the stacked structure 12 .

[0064] As an example, please refer to Figure 1 and Figure 2 In one embodiment of the present application, the orthographic projection of the field plate contact 173 on the surface of the stacked structure 12 is located in an area 1 / 3 of the orthographic projection of the source 13 on the surface of the stacked structure 12 close to the gate 15, which is beneficial to reducing industrial costs while fully exerting the role of the field plate.

[0065] As an example, see Figure 3a-3cIn one embodiment of the present application, a source through-hole 18 is provided on the source electrode 13; the orthographic projection of each field plate contact 173 on the surface of the stacked structure 12 does not overlap with the orthographic projection of the source through-hole 18 on the surface of the stacked structure 12, or the overlapping area is less than 1 / 2 of the area of ​​the orthographic projection of the field plate contact 173 on the surface of the stacked structure 12, which can effectively avoid the collapse of the device structure and is conducive to improving the stability of the device.

[0066] As an example, please refer to Figure 3a-3c In one embodiment of the present application, each field plate contact 173 is located on a side of the source through hole 18 close to the gate 15 .

[0067] As an example, please refer to Figure 3a-3c In one embodiment of the present application, the semiconductor structure further includes a source interconnect metal (not shown); the source interconnect metal is connected to the source 13; and the field plate connector 173 is located between the source 13 and the source interconnect metal.

[0068] As an example, please refer to Figure 3a-3c In one embodiment of the present application, the shape of the orthographic projection of each field plate connector 173 on the surface of the stacked structure 12 can be a rectangle (eg Figure 3a As shown), waist shape (as Figure 3b As shown), elliptical (as Figure 3c As shown), at least one of regular shapes or irregular shapes such as circle, polygon, dumbbell, etc.

[0069] As an example, see Figure 4 In one embodiment of the present application, the stacked structure 12 includes a nucleation layer 121, a channel layer 122, and a barrier layer 123 stacked in sequence. The nucleation layer 121 is located between the substrate 10 and the channel layer 122. The channel layer 122 can be a gallium nitride (GaN) channel layer; the barrier layer 123 can be an aluminum gallium nitride (AlGaN) barrier layer. The barrier layer 123 is used to form a heterojunction structure with the channel layer 122, so that the channel layer 122 provides a channel for the movement of the two-dimensional electron gas.

[0070] As an example, please refer to Figure 4 In one embodiment of the present application, a cap layer (not shown) can also be set on the surface of the barrier layer 123 away from the substrate 10. For example, the cap layer can be set to a gallium nitride cap layer. The cap layer can be a passivation layer used to passivate the surface of the barrier layer 123, reduce the gate current and facilitate metal / semiconductor ohmic contact.

[0071] As an example, please refer to Figure 4In one embodiment of the present application, the substrate 10 may be a silicon carbide substrate or a gallium nitride substrate, for example, the substrate may be configured to include at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium or silicon (Si).

[0072] As an example, please refer to Figure 4 In one embodiment of the present application, the stacked structure 12 including a plurality of sequentially stacked semiconductor layers formed on the substrate 10 may include semiconductor material layers based on Group III-V compounds. Group III-V compounds are compounds formed by boron (B), aluminum (Al), gallium (Ga), indium (In) of Group III in the periodic table and nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) of Group V, and mainly include gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride.

[0073] As an example, see Figure 5 In one embodiment of the present application, a method for preparing a semiconductor structure is provided, comprising:

[0074] Step 202: providing a substrate;

[0075] Step 204: forming a stacked structure comprising a plurality of sequentially stacked semiconductor layers on the substrate, and forming a drain, a source, and a gate on a side of the stacked structure away from the substrate, wherein the gate is located between the source and the drain;

[0076] Step 206: A field plate structure is formed on a side of the source and the gate away from the stacked structure, the field plate structure including a field plate body, a conductive bridge column and a field plate connector, the field plate body is located between the source and the drain; the field plate connector is located on the surface of the source away from the stacked structure; the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body, and the other end of the conductive bridge column is connected to the field plate connector; wherein the number of the field plate connectors is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence.

[0077] For details, please refer to Figure 5After forming a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode on a side of a stacked structure located on a substrate away from the substrate, a field plate structure is formed on a side of the source electrode and the gate electrode away from the stacked structure. The field plate structure is used to increase the area of ​​the depletion region to increase the breakdown voltage of the semiconductor device. At the same time, the field plate structure is used to modulate the distribution of electric field lines in the depletion region of the barrier layer to reduce the leakage current of the gate. By setting the field plate structure to include a field plate body, a conductive bridge column and a field plate connector, the field plate body is located between the source and the drain, the field plate connector is located on the surface of the source away from the stacked structure, the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body and the other end is connected to the field plate connector, the number of the field plate connector is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence, thereby avoiding the introduction of the field plate structure leading to an increase in the gate-source capacitance Cgs of the semiconductor device, thereby effectively ensuring the frequency characteristics, stability and reliability of the manufactured semiconductor device.

[0078] As an example, see Figure 5 and Figure 6 In one embodiment of the present application, the substrate 10 provided in step 202 may be a silicon carbide substrate or a gallium nitride substrate, for example, the substrate may be configured to include at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium or silicon (Si).

[0079] As an example, see Figure 5 、 Figure 6-8b In step 204, after forming a stacked structure 12 including multiple semiconductor layers stacked in sequence on one side of the substrate 10, a source 13, a drain 14 and a gate 15 are formed on the side of the stacked structure 12 away from the substrate 10, and the gate 15 is located between the source 13 and the drain 14.

[0080] As an example, see Figure 5 、 Figures 9-12 In step 206, forming the field plate structure 17 on the side of the source 13 and the gate 15 away from the stacked structure 12 may include the following steps:

[0081] Step 2062 : forming a first dielectric material layer 161 , wherein the first dielectric material layer 161 covers the source 13 , the drain 14 and the gate 15 ;

[0082] Step 2064 : removing the first dielectric material layer 161 on the surface of the source electrode 13 , and the remaining first dielectric material layer 161 constitutes the first dielectric layer 16 ;

[0083] Step 2066: Form a field plate body 171 and a conductive bridge column 172 on the surface of the first dielectric layer 16 located between the source 13 and the drain 14 away from the substrate 10. The field plate body 171 and the conductive bridge column 172 are formed using the same material in the same process step; Step 2068: Form a field plate connector 173 on the surface of the source 13.

[0084] As an example, please refer to Figure 5 、 Figures 9-12 In step 2062 , a deposition process may be used to form a first dielectric material layer 161 . The first dielectric material layer 161 covers the source 13 , the drain 14 and the gate 15 .

[0085] As an example, see Figure 9 In one embodiment of the present application, the first dielectric material layer 161 may be formed using one or more of a flowable chemical vapor deposition (FCVD) process, a high-density plasma (HDP) process, and a plasma-enhanced deposition process. In the present application, the HDP process is preferably used to form the first dielectric material layer 161. The first dielectric material layer 161 covers the source 13, the drain 14, and the gate 15. A chemical mechanical polishing process is then used to planarize the upper surface of the first dielectric material layer 161. The first dielectric material layer 161 includes, but is not limited to, a silicon oxide layer.

[0086] As an example, see Figure 10 In one embodiment of the present application, an etching process may be used to remove the first dielectric material layer 161 located on the surface of the source 13 and the surface of the drain 14 , and the remaining first dielectric material layer 161 constitutes the first dielectric layer 16 .

[0087] As an example, in this embodiment, the etching process may include a plasma dry etching process or a wet etching process. The parameters of the dry etching process include: a gas comprising one or more of a fluorocarbon gas, HBr, and Cl2, and a carrier gas, wherein the fluorocarbon gas comprises CF4, CHF3, CH2F2, or CH3F; the carrier gas is an inert gas, such as He, with a gas flow rate of 50 sccm-400 sccm and a pressure of 3 mTorr-8 mTorr. The etching solution used in the wet etching process may be a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0088] As an example, see Figure 12 In one embodiment of the present application, a deposition process may be used to form the field plate connector 173 in step 2068 .

[0089] As an example, please refer to Figure 12In one embodiment of the present application, the field plate connector 173 may be formed by one or more of a fluid chemical vapor deposition process, a high-density plasma deposition process, and a plasma enhanced deposition process.

[0090] As an example, in one embodiment of the present application, the step of forming a field plate structure on a side of the source and the gate away from the stacked structure may further include:

[0091] forming a first dielectric material layer, wherein the first dielectric material layer covers the gate, the source, and the drain;

[0092] removing the first dielectric material layer located on the surface of the source electrode, and the remaining first dielectric material layer constitutes a first dielectric layer;

[0093] The field plate body, the conductive bridge column and the field plate connector are formed on the surface of the first dielectric layer between the source and the drain away from the substrate. The field plate body, the conductive bridge column and the field plate connector are formed using the same material in the same process step.

[0094] As an example, in one embodiment of the present application, the step of forming the field plate body, the conductive bridge column, and the field plate connector may include the following steps:

[0095] forming a patterned mask layer on a surface of the first dielectric layer away from the substrate, wherein the patterned mask layer has an opening pattern, and the opening pattern defines the shape and position of the field plate structure;

[0096] Based on the patterned mask layer on the side of the source and the gate away from the stacked structure

[0097] forming the field plate structure, wherein the field plate structure includes the field plate body, the conductive bridge column, and the field plate connector;

[0098] The patterned mask layer is removed.

[0099] As an example, in one embodiment of the present application, after forming the source, the step of forming a source through hole in the source is further included, and the source through hole is located on a side of each field plate contact away from the gate.

[0100] As an example, see Figure 12 In one embodiment of the present application, the orthographic projection of each field plate connector 173 on the surface of the stacked structure 12 may be in the shape of a waist. In other embodiments of the present application, the orthographic projection of each field plate connector 173 on the surface of the stacked structure 12 may be in the shape of at least one of a regular shape or an irregular shape such as a rectangle, an ellipse, a circle, a polygon, or a dumbbell.

[0101] The specific definition of the method for preparing the semiconductor structure in the above embodiment can be found in the above definition of the semiconductor structure, which will not be repeated here.

[0102] Unless otherwise specified herein, the execution order of the steps in the method for preparing the semiconductor structure in the above-described embodiments is not strictly limited, and the steps may be performed in other orders. Furthermore, at least a portion of the steps in the method may include multiple steps or multiple stages, and these steps or stages do not necessarily need to be completed at the same time, but may be performed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed in rotation or alternation with other steps or at least a portion of the steps or stages in other steps.

[0103] The method for preparing the semiconductor structure in the above embodiment is intended to schematically illustrate the formation principle of the semiconductor structure in the embodiment of the present application, and is not intended to be a specific limitation on the semiconductor structure in the embodiment of the present application. Other preparation methods may also be used to prepare the semiconductor structure in the embodiment of the present application.

[0104] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0105] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0106] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a stacked structure located on one side of the substrate, comprising a plurality of semiconductor layers stacked in sequence, wherein a source electrode, a gate electrode, and a drain electrode are provided on a side of the stacked structure away from the substrate, and the gate electrode is located between the source electrode and the drain electrode; A field plate structure is located on a side of the source and the gate away from the stacked structure, the field plate structure comprising a field plate body, a conductive bridge column, and a field plate connector. The field plate body is located between the source and the drain; the field plate connector is located on a surface of the source away from the stacked structure; the conductive bridge column is located between the field plate body and the field plate connector, one end of the conductive bridge column is connected to the field plate body and the other end is connected to the field plate connector. The number of the field plate connectors is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence; A source through hole is provided on the source electrode; The orthographic projection of the field plate connector on the surface of the stacked structure does not overlap with the orthographic projection of the source through hole on the surface of the stacked structure, or the overlapping area is less than 1 / 2 of the area of ​​the orthographic projection of the field plate connector on the surface of the stacked structure.

2. The semiconductor structure according to claim 1, wherein: The field plate body and the conductive bridge column are integrally formed; or The field plate body, the conductive bridge column and the field plate connector are integrally formed.

3. The semiconductor structure according to claim 1, wherein: The length of the field plate connector in the extending direction of the field plate body is greater than the length of the conductive bridge column in the extending direction of the field plate body.

4. The semiconductor structure according to claim 3, wherein: The length of the field plate connector in the extending direction of the field plate body is greater than or equal to twice the length of the conductive bridge column in the extending direction of the field plate body, and less than 25 times the length of the conductive bridge column in the extending direction of the field plate body.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The orthographic projection of the source electrode on the surface of the stacked structure completely covers the orthographic projection of the field plate connector on the surface of the stacked structure.

6. The semiconductor structure according to claim 5, wherein: The orthographic projection of the field plate contact on the surface of the stacked structure is located in a region where the orthographic projection of the source electrode on the surface of the stacked structure is close to 1 / 3 of the gate electrode.

7. The semiconductor structure according to claim 1, wherein: Each field plate connector is located on a side of the source through hole close to the gate.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Also included is the source interconnect metal; The source interconnection metal is connected to the source; The field plate contact is located between the source and the source interconnect metal.

9. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure comprising a plurality of sequentially stacked semiconductor layers on the substrate, and forming a drain, a source, and a gate on a side of the stacked structure away from the substrate, wherein the gate is located between the source and the drain; A field plate structure is formed on the side of the source and the gate away from the stacked structure, the field plate structure comprising a field plate body, a conductive bridge column and a field plate connector, the field plate body being located between the source and the drain; the field plate connector being located on the surface of the source away from the stacked structure; the conductive bridge column being located between the field plate body and the field plate connector, one end of the conductive bridge column being connected to the field plate body, and the other end of the conductive bridge column being connected to the field plate connector; wherein the number of the field plate connectors is at least one, the number of the conductive bridge columns is the same as the number of the field plate connectors, and the conductive bridge columns are connected to the field plate connectors in a one-to-one correspondence; a source through hole is provided on the source; the orthographic projection of the field plate connector on the surface of the stacked structure has no overlap with the orthographic projection of the source through hole on the surface of the stacked structure, or the overlapping area is less than 1 / 2 of the area of ​​the orthographic projection of the field plate connector on the surface of the stacked structure.

10. The method according to claim 9, characterized in that The step of forming a field plate structure on a side of the source and the gate away from the stacked structure comprises: forming a first dielectric material layer, wherein the first dielectric material layer covers the gate, the source, and the drain; removing the first dielectric material layer located on the surface of the source electrode, and the remaining first dielectric material layer constitutes a first dielectric layer; forming the field plate body and the conductive bridge pillar on a surface of the first dielectric layer located between the source and the drain, away from the substrate, wherein the field plate body and the conductive bridge pillar are formed using the same material in the same process step; The field plate contact is formed on the surface of the source.

11. The method according to claim 9, characterized in that The step of forming a field plate structure on a side of the source and the gate away from the stacked structure comprises: forming a first dielectric material layer, wherein the first dielectric material layer covers the gate, the source, and the drain; removing the first dielectric material layer located on the surface of the source electrode, and the remaining first dielectric material layer constitutes a first dielectric layer; The field plate body, the conductive bridge column and the field plate connector are formed on the surface of the first dielectric layer between the source and the drain away from the substrate. The field plate body, the conductive bridge column and the field plate connector are formed using the same material in the same process step.

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