A semiconductor device and a method of fabricating the same

Abstract

Embodiments of the present application disclose a semiconductor device and a preparation method thereof. The semiconductor device comprises an active region and a passive region surrounding the active region; the semiconductor device further comprises: a substrate; at least two gates on one side of the substrate and located in the active region, the at least two gates comprising a first gate and a second gate; at least one gate connection structure on one side of the substrate and located in the passive region, the gate connection structure being in contact with the first gate and the second gate respectively; and the gate connection structure and the gate in contact with the gate connection structure being integrally arranged. By using the above technical scheme, the stability of the gate structure and the stability of the performance can be ensured while the power and frequency characteristics are taken into account; the industrial cost can be greatly reduced when different frequency and power designs are met; and the semiconductor device has a simple structure and simple process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, has strong spontaneous and piezoelectric polarization effects, and features a large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity. It has significant advantages in the application fields of manufacturing high-frequency, high-voltage, and high-temperature resistant high-power electronic devices.

[0003] Currently, 5G communication places high demands on the bandwidth and operating frequency of semiconductor chips. The gate structure design and manufacturing process are closely related to the frequency characteristics of semiconductor chips, and the gate structure directly affects the operating frequency. Therefore, research on gate design is of paramount importance in the semiconductor chip manufacturing process.

[0004] Therefore, how to further improve the reliability of semiconductor gates, so as to achieve stable performance of semiconductor chips and enable large-scale commercial production, has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a semiconductor device and a method for fabricating the same, which further improves the reliability of the semiconductor gate and is beneficial to improving the working stability of the semiconductor chip. It can be used in fields such as radio frequency microwave, power electronics, etc.

[0006] In a first aspect, embodiments of the present invention provide a semiconductor device, including an active region and a passive region surrounding the active region; the semiconductor device further includes:

[0007] Substrate;

[0008] At least two gates located on one side of the substrate and in the active region, wherein the at least two gates include a first gate and a second gate;

[0009] At least one gate connection structure is located on one side of the substrate and in the passive region, the gate connection structure being electrically connected to the first gate and the second gate respectively; the gate connection structure and the gate connected thereto are integrally disposed.

[0010] Optionally, the semiconductor device further includes a first electrode and a second electrode; the second electrode includes at least a second electrode A and a second electrode B;

[0011] Along a first direction, the second electrode A, the first gate, the first electrode, the second gate, and the second electrode B are sequentially arranged; the first direction is parallel to the plane where the substrate is located.

[0012] Optionally, the gate connection structure includes a first connection portion, a second connection portion, and a third connection portion;

[0013] The first connection portion extends along the second direction and is connected to the first gate; the second direction intersects the first direction and is parallel to the plane containing the substrate;

[0014] The third connection portion extends along the second direction and is connected to the second gate;

[0015] The second connecting portion extends along the first direction and is connected to the first connecting portion and the third connecting portion, respectively;

[0016] The first connection portion extends wider in the first direction than the first gate extends wider in the first direction;

[0017] The extension width of the third connection portion in the first direction is greater than the extension width of the second gate in the first direction;

[0018] The extension width of the second connecting portion in the two directions is greater than the extension width of the first connecting portion and the third connecting portion in the first direction.

[0019] Optionally, in the same gate connection structure, the distance between the boundary of the first connection portion away from the third connection portion and the boundary of the third connection portion away from the first connection portion is L1;

[0020] The distance between the second electrode A and the second electrode B is L2;

[0021] Where L1 < L2.

[0022] Optionally, the distance L3 between the boundary of the second connection portion near the active region and the active region satisfies 10μm≤L3≤100μm.

[0023] Optionally, the corners of the second connecting portion may include chamfers or rounded corners.

[0024] Optionally, the first gate and the second gate are symmetrical about a first axis of symmetry;

[0025] The gate connection structure is symmetrical about the second axis of symmetry, and the second axis of symmetry is the same as the first axis of symmetry.

[0026] Optionally, the semiconductor device further includes a gate bonding disk located in the passive region and on the side of the gate connection structure away from the active region, the gate bonding disk being electrically connected to the gate connection structure via a via.

[0027] Optionally, an opening is formed in the gate connection structure, and the minimum distance L4 between the opening and the boundary of the gate connection structure satisfies L4≥1μm;

[0028] The opening is filled with bonding metal, and the gate bonding pad is electrically connected to the bonding metal through the via.

[0029] Secondly, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in the first aspect, comprising:

[0030] Provide substrate;

[0031] At least two gates are formed on one side of the substrate and in the active region, wherein the at least two gates include a first gate and a second gate;

[0032] At least one gate connection structure is formed on one side of the substrate and in the passive region, the gate connection structure being electrically connected to the first gate and the second gate respectively; the gate connection structure and the gate connected thereto are integrally disposed.

[0033] The semiconductor device provided in this invention, by adding a gate connection structure and electrically connecting the gate connection structure to two gate contacts respectively, increases the gate end area and the contact area between the gate and its underlying film layer. This reduces the contact resistance of the gate metal while increasing the adhesion between the gate metal and the substrate, thus improving gate stability. Simultaneously, the gate connection structure can serve as a bridge between the gate and external devices. On one hand, it reduces the process difficulty of directly connecting the gate to external devices, lowers the packaging difficulty of the semiconductor device, and improves packaging efficiency. On the other hand, since the gate connection structure is located in the passive region, connecting it to external devices avoids affecting the normal operation of the active region, ensuring normal semiconductor operation. Furthermore, the power and frequency of the semiconductor device can be adjusted through the gate connection structure. On the one hand, it can significantly reduce industrial costs when meeting different frequency and power designs; on the other hand, it can ensure gate structure stability and performance stability while balancing power and frequency characteristics. Furthermore, since the gate connection structure is disposed in the same layer as the gate and is made of the same material, adding the gate connection structure will not increase the number of film layers in the semiconductor device, thus ensuring the simplicity of the semiconductor device structure. Moreover, the gate connection structure and the gate can be fabricated in the same process, so adding the gate connection structure will not increase the fabrication process of the semiconductor device, thus ensuring the simplicity of the semiconductor device fabrication process. Attached Figure Description

[0034] Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0035] Figure 2 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 3 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0037] Figure 4 A top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0038] Figure 5 A top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0039] Figure 6 This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present invention;

[0040] Figure 7 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0042] Example

[0043] This invention provides a semiconductor device that can be used in fields such as radio frequency microwaves and power electronics. Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. (See diagram below.) Figure 1 and Figure 2 As shown, the semiconductor device includes an active region 10 and a passive region 20 surrounding the active region 10; the semiconductor device also includes: a substrate 21; at least two gates 30 located on one side of the substrate 21 and in the active region 10, the at least two gates 30 including a first gate 31G and a second gate 32G; at least one gate connection structure 40 located on one side of the substrate 21 and in the passive region 20, the gate connection structure 40 being electrically connected to the first gate 31G and the second gate 32G respectively; the gate connection structure 40 and the gates connected thereto are integrally disposed.

[0044] For example, such as Figure 1 and Figure 2 As shown, Figure 1 and Figure 2 The following explanation uses only one gate connection structure 40 as an example. The semiconductor device includes an active region 10 and a passive region 20 surrounding the active region 10. The active region 10 contains a two-dimensional electron gas, electrons, or holes, and is the active working region of the semiconductor chip. The passive region 20 refers to the region outside the active region that participates in the device's operation but whose operating state is not affected by external circuitry. At least two gates 30 are disposed on the active region 10 on one side of the substrate 21. These at least two gates 30 include a first gate 31G and a second gate 32G. Furthermore, at least one gate connection structure 40 is disposed on the passive region 20 on one side of the substrate 21. The gate connection structure 40 is electrically connected to the first gate 31G and the second gate 32G, respectively. The gate connection structure 40 and the gates it contacts are disposed in the same layer and made of the same material. By adding the gate connection structure 40, the contact area between the gate end metal and the underlying film layer is increased, reducing the gate contact resistance while increasing the adhesion between the gate metal and the underlying film layer. This optimizes gate performance and prevents localized detachment of the gate metal during fabrication and testing, thereby improving the stability of the semiconductor device. Meanwhile, due to the small gate width of the gate 30, the gate connection structure 40 can be used as a bridge between the gate 30 and external devices. Connecting the gate 30 to external devices reduces the manufacturing complexity of directly connecting the gate 30 to the external devices, lowers the packaging difficulty of the semiconductor device, and improves packaging efficiency. Furthermore, since the gate connection structure 40 is located in the passive region 20, connecting it to external devices avoids affecting the normal operation of the active region 10, ensuring the normal operation of the semiconductor. Moreover, by adding the gate connection structure 40, the power and frequency of the semiconductor device can be adjusted. This significantly reduces industrial costs when meeting different frequency and power designs, and ensures gate structure and performance stability while balancing power and frequency characteristics.

[0045] Furthermore, the gate connection structure 40 and the gate 30 are on the same layer and made of the same material and are integrally formed. Adding the gate connection structure will not increase the number of film layers in the semiconductor device, thus ensuring the simplicity of the semiconductor device structure. Moreover, the gate connection structure 40 and the gate 30 can be fabricated in the same process, ensuring the simplicity of the fabrication process of the gate connection structure 40. Adding the gate connection structure 40 will not increase the fabrication process of the semiconductor device, thus ensuring the simplicity of the semiconductor device fabrication process.

[0046] It needs to be explained that, Figure 1 and Figure 2 This only shows that a gate connection structure 40 is set in the passive region 20 on one side of the active region 10. Multiple gate connection structures 40 can also be set in the passive region 20 on the other side of the active region 10, which will not be elaborated here.

[0047] Optionally, the substrate 21 may be formed from one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or other materials suitable for growing gallium nitride.

[0048] Optionally, the semiconductor device may further include a multilayer semiconductor layer located between the film layer containing the substrate 21 and the film layer containing the gate 30. The multilayer semiconductor layer may include, for example, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The specific structure of the multilayer semiconductor layer is not limited in this embodiment of the invention. Furthermore, a two-dimensional electron gas may be formed between the channel layer and the barrier layer to modulate the electrical characteristics of the semiconductor device.

[0049] In summary, the semiconductor device provided by the embodiments of the present invention, by adding a gate connection structure and electrically connecting the gate connection structure to two gate contacts respectively, can increase the gate end area and the contact area between the gate and its underlying film layer, reduce the contact resistance of the gate metal, increase the adhesion between the gate metal and the substrate, and improve gate stability. Simultaneously, the gate connection structure can serve as a bridge between the gate and external devices. On the one hand, it can reduce the process difficulty when directly connecting the gate to external devices, reduce the packaging difficulty of the semiconductor device, and improve packaging efficiency. On the other hand, since the gate connection structure is located in the passive region, connecting it to external devices can avoid affecting the normal operation of the active region, ensuring the normal operation of the semiconductor. Furthermore, the power and frequency of the semiconductor device can be adjusted through the gate connection structure. On the one hand, it can greatly reduce industrial costs when meeting different frequency and power designs; on the other hand, it can ensure gate structure stability and performance stability while taking into account power and frequency characteristics. Furthermore, since the gate connection structure is disposed in the same layer as the gate and is made of the same material, adding the gate connection structure will not increase the number of film layers in the semiconductor device, thus ensuring the simplicity of the semiconductor device structure. Moreover, the gate connection structure and the gate can be fabricated in the same process, so adding the gate connection structure will not increase the fabrication process of the semiconductor device, thus ensuring the simplicity of the semiconductor device fabrication process.

[0050] Continue to refer to Figure 1 and Figure 2 Optionally, the semiconductor device further includes a first electrode 33 and a second electrode 34; the second electrode 34 includes at least a second A electrode 341 and a second B electrode 342; along a first direction (as shown by the X direction in the figure), the second A electrode 341, the first gate 31G, the first electrode 33, the second gate 32G and the second B electrode 342 are arranged sequentially; the first direction is parallel to the plane where the substrate 21 is located.

[0051] For example, the semiconductor device structure further includes a first electrode 33 and a second electrode 34. The second electrode 34 includes at least a second A electrode 341 and a second B electrode 342. The first electrode 33 includes a source or a drain, and the second electrode 34 includes a drain or a source. The second A electrode 341 and the second B electrode 342 of the second electrode 34 are both sources or both drains. Specifically, the second A electrode 341, the first gate 31G, and the first electrode 33 constitute a source-gate-drain structure, and the first electrode 33, the second gate 32G, and the second B electrode 342 constitute a source-gate-drain structure, with the first electrode 33 serving as a common electrode. Specifically, as... Figure 1 As shown, the first electrode 33 can be set as the source, the second electrode 34 as the drain, and the gate 30 is located between the first electrode 33 and the second electrode 34. One feasible embodiment arranges the source, first gate 31G, drain, second gate 32G, and source along the X direction and extending along the Y direction, with the drain being the common drain; or, as shown... Figure 2 As shown, the first electrode 33 is set as the source, the second electrode 34 is set as the drain, and the gate 30 is located between the first electrode 33 and the second electrode 34. One feasible arrangement is that the drain, the first gate 31G, the source, the second gate 32G and the drain are arranged along the X direction in the figure and extend along the Y direction in the figure, and the source is the common source.

[0052] Considering practical manufacturing processes, sources are typically positioned at the beginning and end of the active region 10 along the X-direction. This corresponds to the source, first gate 31G, drain, second gate 32G, and source arranged sequentially along the X-direction in the semiconductor device provided in this embodiment of the invention. The drain is a common drain. The gate connection structure 40 is electrically connected to the first gate 31G and the second gate 32G, respectively. This ensures gate structure stability and performance stability while balancing power and frequency characteristics; it also significantly reduces industrial costs when meeting different frequency and power designs.

[0053] Based on the above embodiments, Figure 3 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. (See diagram below.) Figure 3As shown, taking a gate connection structure 40 as an example, optionally, the gate connection structure 40 includes a first connection portion 41, a second connection portion 42, and a third connection portion 43 (divided by the dashed line in the figure); the first connection portion 41 extends along the second direction (as shown by the Y direction in the figure) and is connected to the first gate 31G; the second direction (as shown by the Y direction in the figure) intersects with the first direction (as shown by the X direction in the figure) and is parallel to the plane of the substrate; the third connection portion 43 extends along the second direction and is connected to the second gate 32G; the second connection portion 42 extends along the second direction and is connected to the second gate 32G; the second connection portion 42 extends along the second direction and is connected to the second gate 32G; the third connection portion 43 ... The first connection portion 41 extends in a first direction and is connected to the first connection portion 41 and the third connection portion 43 respectively. The extension width of the first connection portion 41 in the first direction is greater than the extension width D1 of the first gate 31G in the first direction (as shown in the X direction in the figure). The extension width of the third connection portion 43 in the first direction is greater than the extension width D2 of the second gate 32G in the first direction. The extension width of the second connection portion 42 in the second direction (as shown in the Y direction in the figure) is greater than the extension widths of the first connection portion 41 and the third connection portion 43 in the first direction.

[0054] For example, continue to refer to... Figure 3 The first direction is the X direction in the figure, and the second direction is the Y direction in the figure. The X direction intersects the Y direction and is parallel to the plane where the substrate 21 is located. The gate connection structure 40 includes a first connection portion 41, a second connection portion 42, and a third connection portion 43 (the first connection portion 41 extends in the Y direction and is connected to the first gate 31G, and the first connection portion 41 extends by a width D at any position in the X direction). 41 All of these extension widths are greater than the first gate 31G's extension width D1 in the X direction. For example, the first connection portion 41 can extend towards the first electrode 341 of the second electrode 34 compared to the first gate 31G. The first electrode 341 includes a source or drain. This facilitates the penetration of the developing solution from the end of the first gate 31G to the middle, significantly reducing the difficulty of development and correcting the gate shape distortion at the corner positions of the source and drain ends caused by light diffraction. This ensures that the shape of the gate end at the corner positions of the source and drain ends is the same as or only slightly different from the shape of the middle part of the gate. At the same time, it increases the contact area between the gate end metal and the underlying film layer, increasing the adhesion between the gate metal and the underlying film layer, preventing local detachment of the gate metal during preparation and testing, and reducing the gate metal contact resistance. Similarly, the third connection portion 43 extends in the Y direction and is connected to the second gate 32G, and the second connection portion 42 extends in the X direction and is connected to the first connection portion 41 and the third connection portion 43 respectively. The extension width D1 of the third connection portion 43 at any position in the X direction is... 43All of these extension widths are greater than the Y-direction extension width D2 of the second gate 32G. For example, the third connection portion 42, compared to the second gate 32G, can extend towards the second electrode 342 of the second electrode 34. The second electrode 342 includes the source or drain side. This facilitates the penetration of the developing solution from the end of the second gate 32G to the middle, significantly reducing the development difficulty and correcting the gate shape distortion at the corner positions of the source and drain ends caused by light diffraction. This ensures that the shape of the gate end at the corner positions of the source and drain ends is the same as or only slightly different from the shape of the middle part of the gate. At the same time, it increases the contact area between the gate end metal and the underlying film layer, increasing the adhesion between the gate metal and the underlying film layer. This can prevent local detachment of the gate metal during preparation and testing, while reducing the gate metal contact resistance. Furthermore, the extension width D2 of the second connection portion 42 at any position in the Y-direction can be... 42 Both are greater than the extension width D2 of the first connection portion 41 and the third connection portion 43 in the X direction, further increasing the contact area between the gate end metal and its lower film layer, increasing the adhesion between the gate metal and the substrate, preventing local detachment of the gate metal during the preparation and testing process, and further increasing the gate end area to further improve the structural stability and performance stability of the gate.

[0055] It should be noted that the gate connection structure 40 is integrally formed with the gate 31G on the same layer and made of the same material. The first connection portion 41, the second connection portion 42 and the third connection portion 43 are integrally formed. For ease of description, the shape of the gate connection structure 40 is divided by dashed lines in the figure. In reality, there are no regional boundaries.

[0056] Based on the above embodiments, continue to refer to Figure 3 In the same gate connection structure 40, the distance between the boundary P1 of the first connection portion 41 away from the third connection portion 43 and the boundary P2 of the third connection portion 43 away from the first connection portion 41 is L1; the distance between the second electrode A 341 and the second electrode B 342 is L2; ​​where L1 < L2.

[0057] For example, such as Figure 3As shown, in the same gate connection structure 40 of the passive region 20, the distance between the boundary P1 of the first connection portion 41 away from the third connection portion 43 and the boundary P2 of the third connection portion 43 away from the first connection portion 41 is L1. This can also be understood as the extension width of the second connection portion 42 at any position in the X direction being L1. In the active region 10, between the second electrode 341 and the second electrode 342 of the second electrode 34, the distance between the boundary P3 of the second electrode 341 near the second electrode 342 and the boundary P4 of the second electrode 342 near the second electrode 341 is set to L2. Ensuring L1 < L2 during semiconductor structure fabrication effectively controls the size of the semiconductor structure and allows the gate connection structure 40 to meet the design requirements for different power and frequency variations, thereby further improving the stability and reliability of the chip. The actual distances L1 and L2 are not limited here; only this relationship needs to be satisfied according to actual production requirements.

[0058] Based on the above embodiments, continue to refer to Figure 3 The distance L3 between the boundary of the second connecting portion 42 near the active region 20 and the active region 10 satisfies 10μm≤L3≤100μm.

[0059] like Figure 3 As shown, the distance L3 between the boundary of the second connection portion 42 near the active region 20 and the active region 10 at any position in the Y direction satisfies 10μm≤L3≤100μm. If the distance between the second connection portion 42 and the active region 10 is too far, the gate resistance will increase, affecting the device performance; if the distance is too close, the device reliability will deteriorate. By reasonably setting the distance between the second connection portion 42 and the active region 10, both the gate resistance and the reliability of the semiconductor device can be taken into account, ensuring good performance of the semiconductor device.

[0060] Preferably, the distance L3 between the boundary of the second connection portion 42 near the active region 20 and the active region 10 can be set between 20-50μm, which can effectively reduce the gate resistance and improve the stability and reliability of the semiconductor device.

[0061] Based on the above embodiments, the stability of the gate can be effectively improved by cleverly designing the shape of the gate connection structure. (Continue referring to...) Figure 2 and Figure 3 Optionally, the corners of the second connecting portion 42 may include chamfers or rounded corners.

[0062] Specifically, the corners of the second connecting portion 42 near the first connecting portion 41 and the corners near the third connecting portion 43 can be set to rounded corners, such as... Figure 3As shown; alternatively, the corners of the second connecting portion 42 near the first connecting portion 41 and the corners near the third connecting portion 43 can be chamfered, such as... Figure 2 As shown, the second connecting portion 42 is further configured with rounded corners near the first connecting portion 41 and chamfered corners near the third connecting portion 43 (not shown in the figure). This embodiment of the invention does not limit the specific shape of the corners of the second connecting portion 42. By reasonably setting the shape of the corners of the second connecting portion 42, the contact area between the gate metal and the substrate is effectively increased while effectively controlling the contact resistance of the gate metal, thereby improving gate stability.

[0063] Based on the above embodiments, continue to refer to Figure 3 The first gate 31G and the second gate 32G are symmetrical about the first axis of symmetry (as shown by Lp in the figure); the gate connection structure 40 is symmetrical about the second axis of symmetry (not shown in the figure), and the second axis of symmetry and the first axis of symmetry are the same axis of symmetry.

[0064] For example, in the manufacturing process, the gate connection structure 40 can be configured with an axisymmetric structure, which can reduce the difficulty of the manufacturing process and is beneficial to the performance stability of the semiconductor device. Specifically, along the Y direction in the figure, in the same unit cell structure group, a reference axis of symmetry Lp is set, and the first gate 31G and the second gate 32G are symmetrical about the reference axis of symmetry Lp. The gate connection structure 40 is also symmetrical about the reference axis of symmetry Lp. Through this structural configuration, the manufacturing process difficulty is effectively reduced, the production efficiency is improved, and the structural performance of the device is stabilized.

[0065] Figure 4 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 4 As shown, the semiconductor device also includes a gate bonding disk 50 located in the passive region 20 and on the side of the gate connection structure 40 away from the active region 10. The gate bonding disk 50 is electrically connected to the gate connection structure 40 through a via (not shown in the figure).

[0066] For example, electrical connection devices need to be introduced during the packaging process of a semiconductor device gate structure. Figure 4 As shown, in this embodiment of the invention, a gate bonding disk 50 is disposed in the passive region 20 and on the side of the gate connection structure 40 away from the active region 10. The gate bonding disk 50 is then bonded to an external device. Specifically, since the gate bonding disk 50 and the gate connection structure 40 are not on the same layer, the gate bonding disk 50 and the gate connection structure 40 are electrically connected through vias to form a conductive path.

[0067] Based on the above embodiments, Figure 5 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 5As shown, in order to further increase the connection strength between the gate bonding disk 50 and the gate connection structure 40, an opening 60 is formed in the gate connection structure 40, and the minimum distance L4 between the opening 60 and the boundary of the gate connection structure 40 satisfies L4≥1μm; the opening 60 is filled with bonding metal, and the gate bonding disk 50 and the bonding metal are electrically connected through vias.

[0068] For example, such as Figure 5 As shown, the minimum distance L4 between the opening 60 and the boundary of the gate connection structure 40 satisfies L4≥1μm. While ensuring the opening is as large as possible, it is also smaller than the boundary of the gate connection structure 40 to avoid through-holes. The shape of the opening 60 can be circular, rectangular, etc., and is not limited here. Furthermore, the opening 60 is filled with bonding metal, and the gate bonding disk 50 is electrically connected to the bonding metal through vias to form a conductive path. The bonding metal filling the opening 60 and the gate metal are made of different materials and use different fabrication processes.

[0069] Figure 6 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present invention. Figure 6 As shown, the semiconductor device further includes a multilayer semiconductor layer 22. Specifically, the multilayer semiconductor layer 22 provided in this embodiment of the invention may include a nucleation layer 221 located on a substrate 21; a buffer layer 222 located on the side of the nucleation layer 221 away from the substrate 21; a channel layer 223 located on the side of the buffer layer 222 away from the nucleation layer 221; and a barrier layer 224 located on the side of the channel layer 223 away from the buffer layer 222. The barrier layer 224 and the channel layer 223 form a heterojunction structure, and a 2DEG is formed at the heterojunction interface.

[0070] For example, the materials of nucleation layer 221 and buffer layer 222 can be nitrides, specifically GaN, AlN, or other nitrides. Nucleation layer 221 and buffer layer 222 can be used to match the material of substrate 21 and epitaxial channel layer 223. The material of channel layer 223 can be GaN or other semiconductor materials, such as InAlN. Barrier layer 224 is located above channel layer 223. The material of barrier layer 224 can be any semiconductor material capable of forming a heterojunction structure with channel layer 223, including gallium-based compound semiconductor materials or nitride semiconductor materials, such as InxAlyGazN1-xyz, where 0≤x≤1, 0≤y≤1, and 0≤z≤1. Optionally, channel layer 223 and barrier layer 224 form a semiconductor heterojunction structure, forming a high-concentration two-dimensional electron gas at the interface between channel layer 223 and barrier layer 224.

[0071] It should be understood that the embodiments of the present invention improve the output power of semiconductor devices from the perspective of semiconductor device structure design. Semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors.

[0072] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in the above embodiments. Figure 7 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the preparation method includes:

[0073] S110 provides a substrate.

[0074] Specifically, the substrate material can be Si, SiC, gallium nitride, or sapphire, or other materials suitable for gallium nitride growth. The substrate fabrication methods can include atmospheric pressure chemical vapor deposition (CVD), sub-atmospheric pressure CVD, organometallic chemical vapor deposition (OMC), low-pressure CVD, high-density plasma chemical vapor deposition (HDPD), ultra-high vacuum CVD, plasma-enhanced CVD, catalytic CVD, hybrid physical-chemical vapor deposition (HPVD), rapid thermochemical vapor deposition (RTC), vapor phase epitaxy, pulsed laser deposition (PLD), atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), sputtering, or evaporation.

[0075] S120. At least two gates are formed on one side of the substrate and in the active region, the at least two gates including a first gate and a second gate.

[0076] S130. At least one gate connection structure is prepared on one side of the substrate and in the passive region, the gate connection structure being electrically connected to the first gate and the second gate respectively; the gate connection structure and the gate connected thereto are integrally disposed.

[0077] Specifically, in combination Figure 3 As shown, at least two gates 30 are fabricated on one side of the substrate 21 and in the active region 10, arranged along the X direction in the figure. The at least two gates 30 include a first gate 31G and a second gate 32G. Simultaneously, at least one gate connection structure is fabricated in the passive region 20 using the same process and materials. Taking the fabrication of a gate connection structure 40 in the passive region 20 as an example, when fabricating the gate, the same process and materials are used to simultaneously fabricate the gate connection structure 40, which is electrically connected to the first gate 31G and the second gate contact 32G respectively. By adding the gate connection structure 40, the contact area between the gate end metal and its underlying film layer is increased, reducing the gate contact resistance and increasing the adhesion between the gate metal and its underlying film layer. This optimizes the gate performance and also prevents local detachment of the gate metal during fabrication and testing, thereby improving the stability of the semiconductor device. Meanwhile, due to the small gate width of the gate 30, the gate connection structure 40 can be used as a bridge between the gate 30 and external devices. Connecting the gate 30 to external devices reduces the manufacturing complexity of directly connecting the gate 30 to the external devices, lowers the packaging difficulty of the semiconductor device, and improves packaging efficiency. Furthermore, since the gate connection structure 40 is located in the passive region 20, connecting it to external devices avoids affecting the normal operation of the active region 10, ensuring the normal operation of the semiconductor. Moreover, by adding the gate connection structure 40, the power and frequency of the semiconductor device can be adjusted. This significantly reduces industrial costs when meeting different frequency and power designs, and ensures gate structure and performance stability while balancing power and frequency characteristics.

[0078] Furthermore, since the gate connection structure 40 and the gate 30 are disposed in the same layer and made of the same material, adding the gate connection structure will not increase the number of film layers in the semiconductor device, thus ensuring the simplicity of the semiconductor device structure. Moreover, the gate connection structure 40 and the gate 30 can be fabricated in the same process, ensuring the simplicity of the fabrication process of the gate connection structure 40. Adding the gate connection structure 40 will not increase the fabrication process of the semiconductor device, thus ensuring the simplicity of the semiconductor device fabrication process.

[0079] Optionally, the semiconductor device provided in this embodiment of the invention may further include multiple semiconductor layers. Correspondingly, the fabrication method further includes fabricating multiple semiconductor layers on one side of a substrate. Specifically, the multiple semiconductor layers may be III-V compound semiconductor materials, and 2DEG is formed in the multiple semiconductor layers.

[0080] In summary, the semiconductor device fabrication method provided by this invention, by adding a gate connection structure and electrically connecting the gate connection structure to two gate contacts respectively, increases the gate end area and the contact area between the gate and its underlying film layer. This reduces the contact resistance of the gate metal while increasing the adhesion between the gate metal and the substrate, thereby improving gate stability. Simultaneously, the gate connection structure can serve as a bridge between the gate and external devices. On one hand, it reduces the process difficulty of directly connecting the gate to external devices, lowers the packaging difficulty of the semiconductor device, and improves packaging efficiency. On the other hand, since the gate connection structure is located in the passive region, connecting it to external devices avoids affecting the normal operation of the active region, ensuring normal semiconductor operation. Furthermore, the power and frequency of the semiconductor device can be adjusted through the gate connection structure. On the one hand, it can significantly reduce industrial costs when meeting different frequency and power designs; on the other hand, it can ensure gate structure stability and performance stability while balancing power and frequency characteristics. Furthermore, since the gate connection structure is disposed in the same layer as the gate and is made of the same material, adding the gate connection structure will not increase the number of film layers in the semiconductor device, thus ensuring the simplicity of the semiconductor device structure. Moreover, the gate connection structure and the gate can be fabricated in the same process, so adding the gate connection structure will not increase the fabrication process of the semiconductor device, thus ensuring the simplicity of the semiconductor device fabrication process.

[0081] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises an active region and a passive region surrounding the active region; the semiconductor device further comprises: a substrate; at least two gates located on one side of the substrate and in the active region, the at least two gates comprising a first gate and a second gate; at least one gate connection structure located on one side of the substrate and in the passive region, the gate connection structure being in contact with the first gate and the second gate respectively; the gate connection structure and the gates in contact with it are integrally arranged in the same layer and of the same material; the semiconductor device further comprises a first electrode and a second electrode; the second electrode comprises at least a second alpha electrode and a second beta electrode; in a first direction, the second alpha electrode, the first gate, the first electrode, the second gate and the second beta electrode are arranged in sequence; the first direction is parallel to the plane in which the substrate is located; the gate connection structure comprises a first connection part, a second connection part and a third connection part; the first connection part extends in a second direction and is connected with the first gate; the second direction intersects the first direction and is parallel to the plane in which the substrate is located; the third connection part extends in the second direction and is connected with the second gate; the second connection part extends in the first direction and is connected with the first connection part and the third connection part respectively; in the same gate connection structure, the distance between the boundary on the side of the first connection part away from the third connection part and the boundary on the side of the third connection part away from the first connection part is L1; the distance between the second alpha electrode and the second beta electrode is L2; wherein, L1 < L2; the semiconductor device further comprises a gate bonding pad located in the passive region and on the side of the gate connection structure away from the active region, the gate bonding pad being electrically connected with the gate connection structure through a via.

2. The semiconductor device according to claim 1, wherein: the extension width of the first connection part in the first direction is greater than the extension width of the first gate in the first direction; the extension width of the third connection part in the first direction is greater than the extension width of the second gate in the first direction; the extension width of the second connection part in the second direction is greater than the extension width of the first connection part and the third connection part in the first direction.

3. The semiconductor device of claim 2, wherein, the distance L3 between the boundary on the side of the second connection part close to the active region and the active region satisfies 10 μm ≤ L3 ≤ 100 μm.

4. The semiconductor device of claim 2, wherein the corner of the second connection part comprises a chamfered corner or a circular arc corner.

5. The semiconductor device of claim 1, wherein the first gate and the second gate are symmetrical about a first symmetry axis; the gate connection structure is symmetrical about a second symmetry axis, and the second symmetry axis is the same as the first symmetry axis.

6. The semiconductor device of claim 1, wherein an opening is formed in the gate connection structure, and the minimum distance L4 between the opening and the boundary of the gate connection structure satisfies L4 ≥ 1 μm; the opening is filled with a bonding connection metal, and the gate bonding pad is electrically connected with the bonding connection metal through the via.

7. A method for producing a semiconductor device according to any one of claims 1 to 6, characterized by, comprises: providing a substrate; At least two gates are prepared on one side of the substrate and in the active region, the at least two gates comprising a first gate and a second gate; At least one gate connecting structure is prepared on one side of the substrate and in the passive region, the gate connecting structure being in contact with the first gate and the second gate respectively; the gate connecting structure and the gates in contact therewith are integrally arranged in the same layer and of the same material.

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