A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes an active region and a passive region. It further includes a source, a gate, and a drain located on one side of a substrate, with the gate positioned between the source and drain. The gate includes a first end portion and a middle portion, with the middle portion, source, and drain all located in the active region, and the first end portion located in the passive region. The first end portion includes a first sub-end portion and a second sub-end portion. Along a first direction, the extension width of the first sub-end portion is greater than the extension width of the middle portion, and the extension width of the second sub-end portion is greater than the extension width of the first sub-end portion. The first direction is parallel to the direction from the source to the drain. By increasing the extension width of the gate end portion, the contact area between the gate end metal and the substrate is increased, improving the device packaging efficiency, ensuring gate structure stability and performance stability, and further enhancing the operational stability and reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, has strong spontaneous and piezoelectric polarization effects, and features a large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity. It has significant advantages in the application fields of manufacturing high-frequency, high-voltage, and high-temperature resistant high-power electronic devices.

[0003] Currently, 5G communication places high demands on the bandwidth and operating frequency of semiconductor devices. The gate structure design and manufacturing process are closely related to the frequency characteristics of semiconductor devices, and the gate structure directly affects the operating frequency. Therefore, research on gate design is of paramount importance in the semiconductor device manufacturing process.

[0004] Therefore, how to further improve the reliability of semiconductor gates, so as to achieve stable performance of semiconductor devices and enable large-scale commercial production, has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a semiconductor device and a method for fabricating the same, further improving the reliability of the semiconductor gate, achieving stable performance of the semiconductor device, and meeting the requirements of large-scale commercial production.

[0006] In a first aspect, embodiments of the present invention provide a semiconductor device, including an active region and a passive region surrounding the active region; the semiconductor device further includes:

[0007] Substrate;

[0008] A source, a gate, and a drain are located on one side of the substrate, with the gate located between the source and the drain;

[0009] The gate includes a first end portion and a middle portion, wherein the middle portion, the source, and the drain are all located in the active region, and the first end portion is located in the passive region;

[0010] The first end portion includes a first sub-end portion and a second sub-end portion; along a first direction, the extension width of the first sub-end portion is greater than the extension width of the middle portion, and the extension width of the second sub-end portion is greater than the extension width of the first sub-end portion; the first direction is parallel to the direction from the source to the drain.

[0011] Optionally, the first sub-end bends toward the source side and / or the drain side;

[0012] The second sub-end bends toward the source side and / or the drain side.

[0013] Optionally, the distance between the bending endpoint of the first sub-end and the boundary of the active region is W1, where 2μm≤W1≤10μm;

[0014] The distance between the bending endpoint of the second sub-terminal and the boundary of the active region is W2, where 10μm≤W2≤50μm.

[0015] Optionally, the edge contour line of the first sub-end near at least one side of the source and / or the drain includes a first curve, and the centers of the arcs corresponding to any two points in the first curve are located on the same side of the first curve.

[0016] The edge profile of the second sub-end near at least one side of the source and / or the drain includes a second curve, wherein the centers of the arcs containing any two points in the second curve are located on the same side of the second curve.

[0017] Optionally, the first curve includes a first point and a second point, wherein the second point is located on the side of the first point closer to the passive region;

[0018] The radius of curvature corresponding to the second point is greater than the radius of curvature corresponding to the first point.

[0019] Optionally, the edge contour line of the first sub-end near at least one side of the source and / or the drain further includes a third curve that is smoothly connected to the first curve, the third curve being located on the side of the first curve near the passive region;

[0020] The centers of the arcs containing any two points in the first curve and any two points in the third curve are located on different sides of the edge contour line.

[0021] Optionally, the first curve includes a first curve start point and a first curve end point, the second curve includes a second curve start point and a second curve end point, and the third curve includes a third curve start point and a third curve end point.

[0022] The termination point of the first curve coincides with the starting point of the third curve;

[0023] When the bending directions of the first sub-end and the second sub-end are the same, the termination point of the third curve coincides with the starting point of the second curve; when the bending directions of the first sub-end and the second sub-end are different, the extension direction of the line connecting the termination point of the third curve and the starting point of the second curve is parallel to the first direction.

[0024] The starting point of the first curve is the connection point between the middle part and the first sub-end point, and the starting point of the second curve is the connection point between the first sub-end point and the second sub-end point.

[0025] Optionally, the gate further includes a second end portion, wherein the first end portion, the intermediate portion, and the second end portion are sequentially disposed along a second direction, and the second end portion is located in the passive region; the second direction intersects with the first direction;

[0026] The second end portion includes a third sub-end portion; along the first direction, the extension width of the third sub-end portion is greater than the extension width of the middle portion.

[0027] Optionally, the second end further includes a fourth sub-end, the fourth sub-end being located on the side of the third sub-end away from the active region, and the fourth sub-end being in contact with the third sub-end;

[0028] Along the first direction, the extension width of the fourth sub-end is greater than the extension width of the third sub-end.

[0029] Optionally, along the first direction, the extension width of the first sub-end is L1, the extension width of the second sub-end is L2, the extension width of the third sub-end is L3, the extension width of the fourth sub-end is L4, and the extension width of the middle part is D.

[0030] Where, 1.2*D≤L1≤30*D;

[0031] 2.4*D≤L2≤60*D;

[0032] 1.2*D≤L3≤30*D;

[0033] 2.4*D≤L4≤60*D.

[0034] In a second aspect, embodiments of the present invention provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in the first aspect, comprising:

[0035] Provide substrate;

[0036] A source, a gate, and a drain are fabricated on one side of the substrate, with the gate located between the source and the drain;

[0037] The gate includes a first end portion and a middle portion, wherein the middle portion, the source, and the drain are all located in the active region, and the first end portion is located in the passive region;

[0038] The first end portion includes a first sub-end portion and a second sub-end portion; along a first direction, the extension width of the first sub-end portion is greater than the extension width of the middle portion, and the extension width of the second sub-end portion is greater than the extension width of the first end portion; the first direction is parallel to the direction from the source to the drain.

[0039] This invention provides a semiconductor device in which the gate sequentially comprises a first end and a middle portion. The middle portion, source, and drain are all located in an active region, while the first end is located in a passive region. The first end in the passive region further comprises a first sub-end and a second sub-end. The first sub-end's extension width in the source-to-drain direction is greater than the middle portion's extension width in the same direction, and the second sub-end's extension width in the same direction is greater than the first end's extension width in the same direction. This structural design facilitates the penetration of the developing solution from the first sub-end to the middle, significantly reducing the development difficulty and correcting the gate shape distortion at the source and drain corners caused by light diffraction, ensuring that the gate shape at the source and drain corners is the same as or only slightly different from the middle portion. Simultaneously, it increases the contact area between the gate end metal and the substrate, increasing the adhesion between the gate metal and the substrate, preventing localized detachment of the gate metal during fabrication and testing, and reducing the gate metal contact resistance. The increased gate end area facilitates interconnection between device gate metals, improving device packaging efficiency. This gate structure design ensures gate structure stability and performance stability, further improving the working stability and reliability of semiconductor devices, and can be used in fields such as radio frequency microwave and power electronics. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0041] Figure 2 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0042] Figure 3 yes Figure 2 A magnified structural diagram of the cc region;

[0043] Figure 4 This is a partial top view of a gate structure provided in an embodiment of the present invention;

[0044] Figure 5 This is a partial top view of another gate structure provided in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0047] Figure 8 This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 9 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0050] This invention provides a semiconductor device that can be used in fields such as radio frequency microwaves and power electronics. Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention. Figure 1 and Figure 2 As shown, semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa; semiconductor device 20 also includes:

[0051] Substrate 21;

[0052] The source 23, gate 24 and drain 25 are located on one side of the substrate 21, with the gate 24 located between the source 23 and the drain 25;

[0053] Gate 24 includes a first end 24a and a middle part 241. The middle part 241, source 23 and drain 25 are all located in the active region aa, and the first end 24a is located in the passive region bb.

[0054] The first end portion 24a includes a first sub-end portion 242a and a second sub-end portion 243a; along a first direction (as shown by the X direction in the figure), the extension width of the first sub-end portion 242a is greater than the extension width of the middle portion 241, and the extension width of the second sub-end portion 243a is greater than the extension width of the first sub-end portion 242a; the first direction is parallel to the direction from the source 23 to the drain 25.

[0055] For example, such as Figure 1 and Figure 2As shown, the source 23, gate 24, and drain 25 are arranged along a first direction (the X direction shown in the figure) and extend along the Y direction shown in the figure. The gate 24 is located between the source 23 and the drain 25. In the figure, the X direction is parallel to the direction from the source 23 to the drain 25, and the Y direction intersects the X direction. The semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa. The gate 24 sequentially includes a first end 24a and a middle portion 241. The middle portion 241, the source 23, and the drain 25 are all located in the active region aa. The first end 24a is located in the passive region bb. The first end 24a includes a first sub-end 242a and a second sub-end 243a, both located within the passive region bb. The active region aa contains a two-dimensional electron gas, electrons, or holes and is the active working region of the semiconductor chip. The passive region bb refers to the region outside the active region that participates in the operation of the device, but whose operating state is not affected by external circuits.

[0056] like Figure 1 and Figure 2 As shown, the first sub-end 242a located in the passive region bb has a greater extension width in the X direction than the middle part 241 in the X direction. This larger extension width of the first sub-end 242a facilitates the penetration of the developer from the first sub-end 242a to the middle part 241, reducing the photolithography development difficulty of the gate 24. It can correct the gate shape distortion at the corner positions of the source and drain caused by light diffraction, significantly reducing the development difficulty and ensuring that the gate shape at the corner positions of the source and drain is the same as or only slightly different from the shape of the middle part 241. This ensures the structural and performance stability of the gate 24 and further avoids the impact of gate deformation on the power and frequency of the semiconductor device, ensuring the performance stability of the semiconductor device.

[0057] Furthermore, such as Figure 1 and Figure 2 As shown, the second sub-end 243a located in the passive region bb has a greater extension width in the X direction than the first sub-end 242a in the X direction, and is also greater than the middle portion 241 in the X direction. This structural design increases the contact area between the gate end metal and the substrate by increasing the extension width of the gate end, thereby increasing the adhesion between the gate metal and the substrate. This can prevent local detachment of the gate metal during fabrication and testing, and reduce the contact resistance of the gate metal. At the same time, the increased gate end area facilitates interconnection between the gate metals of the device, improves the device packaging efficiency, and further improves the performance stability of the semiconductor device.

[0058] Optionally, the substrate 21 may be made of one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or other materials suitable for growing gallium nitride.

[0059] In summary, the semiconductor device provided in this embodiment of the invention comprises a first end portion and a middle portion in sequence as a gate, wherein the middle portion, the source, and the drain are all located in an active region, and the first end portion is located in a passive region. Furthermore, the first end portion located in the passive region comprises a first sub-end portion and a second sub-end portion, wherein the extension width of the first sub-end portion in the direction from the source to the drain is greater than the extension width of the middle portion in the direction from the source to the drain, and the extension width of the second sub-end portion in the direction from the source to the drain is greater than the extension width of the first end portion in the direction from the source to the drain. This structural design facilitates the penetration of the developing solution from the first sub-end towards the center, significantly reducing the difficulty of development and correcting the gate shape distortion at the source and drain corners caused by light diffraction. This ensures that the gate shape at the source and drain corners is the same as or only slightly different from the shape of the middle section. Simultaneously, it increases the contact area between the gate end metal and the substrate, enhancing adhesion and preventing localized detachment of the gate metal during fabrication and testing, while also reducing contact resistance. Furthermore, the addition of the second sub-end further increases the gate end area, facilitating interconnection between device gate metals and improving device packaging efficiency. This gate structure design ensures gate structure and performance stability, further improving the operational stability and reliability of semiconductor devices, and can be used in fields such as radio frequency microwaves and power electronics.

[0060] Optional, continue to refer to Figure 1 and Figure 2 The first sub-end 242a bends toward the source 23 side and / or the drain 25 side; the second sub-end 243a bends toward the source 23 side and / or the drain 25 side.

[0061] For example, continue to refer to Figure 1 and Figure 2The first sub-end 242a and the second sub-end 243a extend to the passive region bb. The first sub-end 242a can extend and bend in the Y direction in the source 23 direction or in the drain 25 direction (not shown in the figure), or can extend and bend in both the source 23 direction and the drain 25 direction at the same time (not shown in the figure). The second sub-end 243a connected to the first sub-end 242a can extend and bend in the source 23 direction (not shown in the figure), or in the drain 25 direction, or can extend and bend in both the source 23 direction and the drain 25 direction at the same time (not shown in the figure). In this embodiment of the invention, there is no limitation on how the width of the first sub-end 242a and the second sub-end 243a extending into the passive region is increased. It is only necessary to ensure that the extension width of the first sub-end 242a and the second sub-end 243a located at least in the passive region bb is greater than the extension width of the middle part 241, and the extension width of the second sub-end 243a is greater than the extension width of the first sub-end 242a. This can correct the gate corresponding to the corner position at both ends of the source and drain, and increase the contact area between the gate end metal and the substrate.

[0062] Figure 3 yes Figure 2 A magnified structural diagram of the cc region. Figure 3 The explanation will focus on the first end 24a located within the passive region bb, including the first sub-end 242a and the second sub-end 243a. (In conjunction with...) Figure 2 and Figure 3 As shown, optionally, the distance between the bending endpoint C of the first sub-end 242a and the boundary of the active region aa is W1, 2μm≤W1≤10μm;

[0063] The distance between the bending endpoint D of the second sub-end 243a and the boundary of the active region aa is W2, 10μm≤W2≤50μm.

[0064] For example, in combination Figure 2 and Figure 3 As shown, the distance W1 between the bending endpoint C of the first sub-end 242a and the boundary of the active region aa is set to satisfy 2μm≤W1≤10μm. By reasonably setting the distance W1 between the bending endpoint C of the first sub-end 242a and the boundary of the active region aa, it can be ensured that the first sub-end 242a of the gate does not occupy too much substrate area, and at the same time, it will not increase the capacitance between the first sub-end 242a of the gate and the active region aa, the source 23 or the drain 25.

[0065] Furthermore, the distance between the bending endpoint D of the second sub-end 243a and the boundary of the active region aa is set to W2, satisfying 10μm≤W2≤50μm. By reasonably setting the distance W2 between the bending endpoint D of the second sub-end 243a and the boundary of the active region aa, the distance between the second sub-end 243a of the gate and the source 23 or drain 25 of the active region aa is controlled. On the one hand, the capacitance between the second sub-end 243a and the active region aa, the source 23 or drain 25 is controlled, thereby reducing the power loss of the device. On the other hand, the second sub-end 243a of the gate is prevented from occupying too much substrate area.

[0066] Based on the above embodiments, combined with Figure 2 and Figure 3 As shown, the edge contour line of the first sub-end 242a near at least one side of the source 23 and / or drain 25 includes a first curve 242a1, and the center of the arc corresponding to any two points in the first curve 242a1 is located on the same side of the first curve 242a1.

[0067] The edge profile of the second sub-end 243a near at least one side of the source 23 and / or drain 25 includes a second curve 243a1, wherein the centers of the arcs containing any two points in the second curve 243a1 are located on the same side of the second curve 243a1.

[0068] For example, in combination Figure 2 and Figure 3 As shown, the first sub-end 242a bends towards the source 23, and the edge contour line of the first sub-end 242a near the source 23 includes a first curve 242a1; the second sub-end 243a bends towards the drain 25, and the edge contour line of the second sub-end 243a near the drain 25 includes a second curve 243a1. Figure 3 As shown, the center of the arc corresponding to any two points in the first curve 242a1 is located on the same side of the first curve 242a1. This structure can reduce the electric field spike between the gate and the source. The center of the arc corresponding to any two points in the second curve 243a1 is located on the same side of the second curve 243a1. This structure can reduce the electric field spike between the gate and the drain, further ensuring the stability of the semiconductor device performance.

[0069] It should be noted that this embodiment only takes the edge contour line of the first sub-end 242a near the source 23 as including the first curve 242a1 and the edge contour line of the second sub-end 243a near the drain 25 as including the second curve 243a1 as an example. It can be understood that the edge contour line of the first sub-end 242a near the drain 25 can also be set to include the first curve 242a1, or the edge contour lines near both the source 23 and the drain 25 can both include the first curve 242a1; similarly, the edge contour line of the second sub-end 243a near the source 23 can also be set to include the second curve 243a1, or the edge contour lines near both the source 23 and the drain 25 can both include the second curve 243a1. This embodiment of the invention does not limit this.

[0070] Optional, Figure 4 This is a partial top view of a gate structure provided in an embodiment of the present invention, as shown in the figure. Figure 4 As shown, the first curve 242a1 includes a first point A and a second point B. The second point B is located on the side of the first point A that is close to the passive region bb. The radius of curvature R2 corresponding to the second point B is greater than the radius of curvature R1 corresponding to the first point A.

[0071] For example, Figure 4 Let's take the first point as the starting point A of the first curve and the second point as the ending point B of the first curve as an example. Figure 4 As shown, the starting point A of the first curve is the boundary between the active region aa and the passive region bb. The radius of curvature R2 corresponding to the second point B is greater than the radius of curvature R1 corresponding to the first point A. Thus, along the direction from the active region aa to the passive region bb, the distance between the first curve 2341 and the chamfer of the opposite source electrode 23 gradually increases, further optimizing the electric field between the gate electrode 24 and the source electrode 23, and further ensuring the stability of the semiconductor device performance.

[0072] Optional, Figure 5 This is a partial top view schematic diagram of another gate structure provided in an embodiment of the present invention. (See diagram below.) Figure 5 As shown, the edge contour line of the first sub-end 242a near at least one side of the source 23 and / or drain 25 also includes a third curve 242a2 that is smoothly connected to the first curve 242a1. The third curve 242a2 is located on the side of the first curve 242a1 near the passive region bb. The centers of the arcs containing any two points in the first curve 242a1 and any two points in the third curve 242a2 are located on different sides of the edge contour line.

[0073] For example, Figure 5The following description focuses on the second end 24b located within the passive region bb, which includes a first sub-end 242a and a second sub-end 243a. The first sub-end 242a bends towards the source 23, and its edge contour near the source 23 includes a first curve 242a1 and a third curve 242a2. The second sub-end 243a bends towards the drain 25, and its edge contour near the drain 25 includes a second curve 243a1. Figure 5 As shown, the third curve 242a2 is located on the side of the first curve 242a1 near the passive region bb. The first curve 242a1 is smoothly connected to the third curve 242a2, thereby ensuring that no electric field spike will be generated on the side of the second sub-end 243a near the source 23 due to the sharp corner, which further improves the stability of the semiconductor's electrical performance; at the same time, it can also avoid stress concentration and ensure the stability of the semiconductor device's mechanical performance.

[0074] Furthermore, the centers of the arcs containing any two points in the first curve 242a1 and any two points in the third curve 242a2 are located on different sides of the edge contour line, which further ensures that the distance between the first curve 2341 and the chamfer of the opposite source electrode 23 gradually increases, optimizes the electric field between the gate electrode 24 and the source electrode 23, and improves the stability of semiconductor device performance.

[0075] It should be noted that this embodiment only takes the edge contour line of the first sub-end 242a near the source 23 as including the first curve 242a1 and the third curve 242a2, and the edge contour line of the second sub-end 243a near the drain 25 as including the second curve 243a1 as an example. It can be understood that the edge contour line of the first sub-end 242a near the drain 25 can also be set to include the first curve 242a1 and the third curve 242a2, or the edge contour lines of both the source 23 and the drain 25 can include the first curve 242a1 and the third curve 242a2. This embodiment of the invention does not limit this.

[0076] Optional, continue to refer to Figure 3 and Figure 5The first curve 242a1 includes a starting point A and a ending point B; the second curve 243a1 includes a starting point E and a ending point D; and the third curve 242a2 includes a starting point B and a ending point C. The ending point B of the first curve coincides with the starting point B of the third curve. When the bending directions of the first sub-end 242a and the second sub-end 243a are the same, the ending point C of the third curve coincides with the starting point E of the second curve (not shown in the figure). When the bending directions of the first sub-end 242a and the second sub-end 243a are different, the extension direction of the line connecting the ending point C of the third curve and the starting point E of the second curve is parallel to the second direction (as shown by the Y direction in the figure). The starting point A of the first curve is the connection point between the middle part 241 and the first sub-end 242a, and the starting point E of the second curve is the connection point between the first sub-end 242a and the second sub-end 243a.

[0077] For example, such as Figure 3 As shown, the termination point of the first curve 242a1 coincides with the starting point of the third curve, both being point B. The starting point A of the first curve 242a1 is the connection point between the middle part 241 and the first sub-end 242a. The starting point E of the second curve 243a1 is set as the connection point between the first sub-end 242a and the second sub-end 243a. The extension direction of the line connecting the termination point C of the third curve and the starting point E of the second curve is parallel to the second direction (as shown by the Y direction in the figure), which is used to distinguish the first sub-end 242a and the second sub-end 243a, and to further rationally set the structure of the first sub-end 242a and the second sub-end 243a.

[0078] It should be noted that the embodiments of the present invention only take the different bending directions of the first sub-end 242a and the second sub-end 243a as an example. When the bending directions of the first sub-end 242a and the second sub-end 243a are the same, the termination point C of the third curve coincides with the starting point E of the second curve, forming the edge contour line of at least one side of the image source electrode 23 and / or the drain electrode 25. This will not be described in detail here.

[0079] As a feasible implementation method. Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 6 As shown, optionally, the gate 24 also includes a second end 24b. Along the second direction (as shown by the Y direction in the figure), the first end 24a, the middle part 241 and the second end 24b are arranged sequentially, and the second end 24b is located in the passive region bb; the second direction intersects with the first direction (as shown by the X direction in the figure);

[0080] The second end portion 24b includes a third sub-end portion 242b; along the first direction, the extension width of the third sub-end portion 242b is greater than the extension width of the middle portion 241.

[0081] For example, such as Figure 6 As shown in the figure, along the Y direction, the gate 24 includes a first end 24a, a middle portion 241, and a second end 24b, which are sequentially arranged. Both the first end 24a and the second end 24b are located in the passive region bb. The second end 24b includes a third sub-end 242b, and the extension width of the third sub-end 242b in the X direction is greater than the extension width of the middle portion 241. The shapes of the first end 24a and the second end 24b can be the same or different; this embodiment of the invention does not limit this. Furthermore, the third sub-end 242b can be bent towards the source 23 and / or towards the drain 25. Preferably, as shown... Figure 6 As shown, the third sub-end 242b bends towards the source 23. By setting the second end 24b to extend to the gate end of the passive region bb, the width of the gate at the corner positions at both ends of the source and drain is adjusted, correcting the gate shape distortion at the corner positions at both ends of the source and drain caused by light diffraction, improving gate stability, and avoiding the impact of gate deformation on the power and frequency of the semiconductor device. At the same time, the first end 24a and the second end 24b at both ends of the gate increase the contact area between the gate end metal and the substrate, increasing the adhesion between the gate metal and the substrate, which can prevent local detachment of the gate metal during the fabrication and testing process and reduce the gate metal contact resistance. In addition, the increased gate end area facilitates the interconnection between the gate metals of the device, improves the device packaging efficiency, and further improves the performance stability of the semiconductor device.

[0082] Based on the above embodiments, Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 7 As shown, optionally, the second end 24b also includes a fourth sub-end 243b, which is located on the side of the third sub-end away from the active region aa, and the fourth sub-end 243b is in contact with the third sub-end 242b.

[0083] Along the first direction (as shown by the X direction in the figure), the extension width of the fourth sub-end 243b is greater than the extension width of the third sub-end 242b.

[0084] For example, such as Figure 7As shown, similar to the first end portion 24a provided in the above embodiment, the second end portion 24b includes a third sub-end portion 242b and a fourth sub-end portion 243b. The extension width of the third sub-end portion 242b in the X direction is greater than the extension width of the middle portion 241, and the extension width of the fourth sub-end portion 243b in the X direction is greater than the extension width of the third sub-end portion 242b. The shapes of the first end portion 24a and the second end portion 24b can be the same or different; this embodiment of the invention does not limit this. By further configuring the second end 24b, including the third sub-end 242b and the fourth sub-end 243b, and further configuring the second end 24b to extend to the gate end of the passive region bb, the width of the gate corresponding to the corner positions at both ends of the source and drain is adjusted. This corrects the gate shape distortion at the corner positions at both ends of the source and drain caused by light diffraction, improves gate stability, and avoids the impact of gate deformation on the power and frequency of the semiconductor device. At the same time, the first end 24a and the second end 24b at both ends of the gate increase the contact area between the gate end metal and the substrate, increasing the adhesion between the gate metal and the substrate. This can prevent local detachment of the gate metal during the fabrication and testing process and reduce the contact resistance of the gate metal. In addition, the increased gate end area facilitates the interconnection between the gate metals of the device, improves the device packaging efficiency, and further improves the performance stability of the semiconductor device.

[0085] Based on the above embodiments, combined with Figure 3 , Figure 6 and Figure 7 Optionally, along the first direction, the extension width of the first sub-end 242a is L1, the extension width of the second sub-end 243a is L2, the extension width of the third sub-end 242b is L3, the extension width of the fourth sub-end 243b is L4, and the extension width of the middle part 241 is D.

[0086] Wherein, 1.2*D≤L1≤30*D; 2.4*D≤L2≤60*D;

[0087] 1.2*D≤L3≤30*D; 2.4*D≤L4≤60*D.

[0088] For example, the gate 24 includes a first end 24a and a second end 24b for illustration. Figure 7As shown, the extension width of the first sub-end 241 extending to the passive bb region is set to L1, satisfying 1.2*D≤L1≤30*D, and the extension width of the third sub-end 242b extending to the passive bb region is set to satisfy 1.2*D≤L3≤30*D. By reasonably setting the extension widths of the first sub-end 242a and the third sub-end 242b extending to the passive bb region, it can be ensured that the first sub-end 242a extending to the passive bb region can moderately correct the gate 24 at the corner positions of the source and drain ends, making up for or completely eliminating the problem of gate width reduction caused by light diffraction; at the same time, it will not cause over-correction, and will not cause the problem of gate 24 at the corner positions of the source and drain ends to widen due to over-correction, ensuring that the gate width of the gate 24 in the active region aa is consistent or basically consistent.

[0089] Furthermore, setting the extension width of the second sub-end 243a extending to the passive bb region to be greater than L1, and satisfying 2.4*D≤L2≤60*D with the extension width D of the middle part, and setting the extension width of the fourth sub-end 243b extending to the passive bb region to be greater than L3, and satisfying 2.4*D≤L4≤60*D with the extension width D of the middle part, can ensure a larger contact area between the gate and the substrate, increase the adhesion between the gate metal and the substrate, and prevent the gate bar from falling off; at the same time, it will not occupy too much substrate area or affect the device integration efficiency; it can ensure strong adhesion between the gate 24 and the substrate, and further ensure the structural stability and performance stability of the semiconductor device.

[0090] Where L1 can be equal to 1.2*D, 1.5*D, 2*D, 3*D, 3.5*D, 5*D, 10*D, 15*D or 30*D, L2 can be equal to 2.4*D, 3*D, 3.5*D, 5*D, 10*D, 15*D, 30*D or 60*D, and L2 > L1; L3 can be equal to 1.2*D, 1.5*D, 2*D, 3*D, 3.5*D, 5*D, 10*D, 15*D or 30*D, and L4 can be equal to 2.4*D, 3*D, 3.5*D, 5*D, 10*D, 15*D, 30*D or 60*D, and L4 > L3. In this embodiment of the invention, specific values ​​are not enumerated, and the specific correspondence between the extension width of the first end 24a extending to the passive bb region and the extension width of the second end 24b is not limited. It is only necessary to ensure the structural stability and performance stability of the gate 24, and further ensure the performance stability of the semiconductor device.

[0091] Optional, Figure 8 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present invention. Figure 8As shown, based on the above embodiments, the semiconductor device 20 provided in this embodiment of the invention further includes a field plate structure 26 located on the side of the gate 24 away from the substrate 21, and the field plate structure 26 and the gate 24 form a parallel plate capacitor.

[0092] For example, since at least the first end and / or the second end located within the passive region bb are in the second direction (e.g. Figure 7 The extension width on the gate 24 is greater than the extension width of the middle part in the second direction, thus increasing the overall area of ​​the gate 24. Since the gate 24 and the field plate structure 26 located on the gate 24 form a planar capacitor, the gate 24 serves as a capacitor substrate of the planar capacitor. Increasing the area of ​​the gate 24 can increase the capacitance of the planar capacitor, increase the control range of the gate capacitor, and further optimize the performance of the semiconductor device.

[0093] Further reference Figure 8 As shown, the semiconductor device 20 provided in this embodiment of the invention may further include a protective layer 27, which is located on the side of the field plate structure 26 away from the substrate 21 and is used to encapsulate and protect the semiconductor device 20.

[0094] Further reference Figure 8 As shown, the semiconductor device 20 provided in this embodiment of the invention may further include a multilayer semiconductor layer 22. The multilayer semiconductor layer 22 may include a nucleation layer 221 located on the substrate 10; a buffer layer 222 located on the side of the nucleation layer 221 away from the substrate 21; a channel layer 223 located on the side of the buffer layer 222 away from the nucleation layer 221; and a barrier layer 224 located on the side of the channel layer 223 away from the buffer layer 222. The barrier layer 224 and the channel layer 223 form a heterojunction structure, and a 2DEG is formed at the heterojunction interface.

[0095] For example, the materials of nucleation layer 221 and buffer layer 222 can be nitrides, specifically GaN, AlN, or other nitrides. Nucleation layer 221 and buffer layer 222 can be used to match the material of the substrate 10 and the epitaxial channel layer 223. The material of channel layer 223 can be GaN or other semiconductor materials, such as InAlN. Barrier layer 224 is located above channel layer 223. The material of barrier layer 224 can be any semiconductor material capable of forming a heterojunction structure with channel layer 223, including gallium-based compound semiconductor materials or nitride semiconductor materials.

[0096] The gallium nitride radio frequency device formed using the semiconductor device structure of the present invention can improve the power and frequency of the gallium nitride radio frequency device while maintaining the stability of the semiconductor device performance, thus making it more suitable for the high-frequency 5G communication field.

[0097] It should be understood that the embodiments of the present invention improve the output power of semiconductor devices from the perspective of semiconductor device structure design. The semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors.

[0098] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in the above embodiments. Figure 9 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes:

[0099] S110 provides a substrate.

[0100] For example, the substrate material can be Si, SiC, gallium nitride, or sapphire, or other materials suitable for growing gallium nitride. The substrate can be prepared by methods such as atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, organometallic chemical vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0101] S120, the gate includes a first end and a middle part, the middle part, the source and the drain are all located in the active region, and the first end is located in the passive region; the first end includes a first sub-end and a second sub-end; along the first direction, the extension width of the first sub-end is greater than the extension width of the middle part, and the extension width of the second sub-end is greater than the extension width of the first end; the first direction is parallel to the direction from the source to the drain.

[0102] Specifically, such as Figure 1 and Figure 2 As shown, the source 23, gate 24, and drain 25 are arranged along a first direction (the X direction shown in the figure) and extend along the Y direction shown in the figure. The gate 24 is located between the source 23 and the drain 25. In the figure, the X direction is parallel to the direction from the source 23 to the drain 25, and the Y direction intersects the X direction. The semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa. The gate 24 includes a first end 24a and a middle part 241. The middle part 241, the source 23, and the drain 25 are all located in the active region aa. The first end 24a is located in the passive region bb. The first end 24a includes a first sub-end 242a and a second sub-end 243a, both located within the passive region bb. The active region aa contains a two-dimensional electron gas, electrons, or holes and is the active working region of the semiconductor chip. The passive region bb refers to the region outside the active region that participates in the operation of the device, but whose operating state is not affected by external circuits.

[0103] like Figure 1 and Figure 2As shown, the first sub-end 242a located in the passive region bb has a greater extension width in the X direction than the middle part 241 in the X direction. This larger extension width of the first sub-end 242a facilitates the penetration of the developing solution from the first sub-end 242a to the middle part 241, reducing the photolithography development difficulty of the gate 24. It can correct the gate shape distortion at the corner positions of the source and drain ends caused by light diffraction, significantly reducing the development difficulty and ensuring that the gate shape at the corner positions of the source and drain ends is the same as or only slightly different from the shape of the middle part 241. This ensures the structural and performance stability of the gate 24 and further avoids the impact of gate deformation on the power and frequency of the semiconductor device, ensuring the performance stability of the semiconductor device.

[0104] Furthermore, such as Figure 1 and Figure 2 As shown, the extension width of the second sub-end 243a located in the passive region bb in the X direction is greater than that of the first sub-end 242a in the X direction, and also greater than that of the middle part 241 in the X direction. This structural design increases the contact area between the gate end metal and the substrate by increasing the extension width of the gate end, thereby increasing the adhesion between the gate metal and the substrate. This can prevent local detachment of the gate metal during the fabrication and testing process and reduce the contact resistance of the gate metal. At the same time, the increased gate end area facilitates the interconnection between the gate metals of the device, improves the device packaging efficiency, and further improves the performance stability of the semiconductor device.

[0105] Optionally, the semiconductor device provided in this embodiment of the invention may further include multiple semiconductor layers. Correspondingly, the fabrication method further includes fabricating multiple semiconductor layers on one side of a substrate. Specifically, the multiple semiconductor layers may be III-V compound semiconductor materials, and 2DEG is formed in the multiple semiconductor layers.

[0106] In summary, the semiconductor device fabrication method provided by the embodiments of the present invention involves fabricating a first end of the gate extending into a passive region. The first end in the passive region includes a first sub-end and a second sub-end. The extension width of the first and second sub-ends in the source-to-drain direction is greater than the extension width of the middle portion in the source-to-drain direction, and the extension width of the second sub-end is greater than the extension width of the first sub-end. This ensures that the first end of the gate in the passive region has a relatively large extension width. This larger extension width facilitates the penetration of the developing solution from the end to the middle portion, correcting the gate shape distortion at the source and drain corners caused by light diffraction, significantly reducing the difficulty of development, ensuring that the gate shape at the source and drain corners is the same as or only slightly different from the shape of the middle portion, guaranteeing gate structure stability and performance stability. Furthermore, it avoids the impact of gate deformation on the power and frequency of the semiconductor device, ensuring stable semiconductor device performance, and can be used in fields such as radio frequency microwaves and power electronics.

[0107] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes an active region and a passive region surrounding the active region; the semiconductor device further includes: Substrate; A source, a gate, and a drain are located on one side of the substrate, with the gate located between the source and the drain; The gate includes a first end portion and a middle portion, wherein the middle portion, the source, and the drain are all located in the active region, and the first end portion is located in the passive region; The first end portion includes a first sub-end portion and a second sub-end portion; along a first direction, the extension width of the first sub-end portion is greater than the extension width of the middle portion, and the extension width of the second sub-end portion is greater than the extension width of the first sub-end portion; the first direction is parallel to the direction from the source to the drain. The first sub-end bends toward the source side and / or the drain side; The second sub-end bends toward the source side and / or the drain side, and along the first direction, the bent portion of the first sub-end and the bent portion of the second sub-end are located on different sides of the first end; The first sub-end is provided to correct the gate shape distortion at the corner positions of the source and drain ends; the second sub-end is provided to increase the end area of ​​the gate, thereby improving the packaging efficiency of the semiconductor device.

2. The semiconductor device according to claim 1, characterized in that, The distance between the bending endpoint of the first sub-end and the boundary of the active region is W1, where 2μm≤W1≤10μm; The distance between the bending endpoint of the second sub-end and the boundary of the active region is W2, where 10μm≤W2≤50μm.

3. The semiconductor device according to claim 1, characterized in that, The edge contour line of the first sub-end near at least one side of the source and / or the drain includes a first curve, and the centers of the arcs corresponding to any two points in the first curve are located on the same side of the first curve. The edge profile of the second sub-end near at least one side of the source and / or the drain includes a second curve, wherein the centers of the arcs containing any two points in the second curve are located on the same side of the second curve.

4. The semiconductor device according to claim 3, characterized in that, The first curve includes a first point and a second point, with the second point located on the side of the first point closer to the passive region; The radius of curvature corresponding to the second point is greater than the radius of curvature corresponding to the first point.

5. The semiconductor device according to claim 3, characterized in that, The edge contour line of the first sub-end near at least one side of the source and / or the drain also includes a third curve that is smoothly connected to the first curve, and the third curve is located on the side of the first curve near the passive region. The centers of the arcs containing any two points in the first curve and any two points in the third curve are located on different sides of the edge contour line.

6. The semiconductor device according to claim 5, characterized in that, The first curve includes a first curve start point and a first curve end point; the second curve includes a second curve start point and a second curve end point; and the third curve includes a third curve start point and a third curve end point. The termination point of the first curve coincides with the starting point of the third curve; When the bending directions of the first sub-end and the second sub-end are the same, the termination point of the third curve coincides with the starting point of the second curve; when the bending directions of the first sub-end and the second sub-end are different, the extension direction of the line connecting the termination point of the third curve and the starting point of the second curve is parallel to the first direction. The starting point of the first curve is the connection point between the middle part and the first sub-end point, and the starting point of the second curve is the connection point between the first sub-end point and the second sub-end point.

7. The semiconductor device according to claim 1, characterized in that, The gate further includes a second end portion. Along a second direction, the first end portion, the middle portion, and the second end portion are sequentially arranged, and the second end portion is located in the passive region. The second direction intersects with the first direction. The second end portion includes a third sub-end portion; along the first direction, the extension width of the third sub-end portion is greater than the extension width of the middle portion.

8. The semiconductor device according to claim 7, characterized in that, The second end also includes a fourth sub-end, which is located on the side of the third sub-end away from the active region, and the fourth sub-end is in contact with the third sub-end; Along the first direction, the extension width of the fourth sub-end is greater than the extension width of the third sub-end.

9. The semiconductor device according to claim 8, characterized in that, Along the first direction, the extension width of the first sub-end is L1, the extension width of the second sub-end is L2, the extension width of the third sub-end is L3, the extension width of the fourth sub-end is L4, and the extension width of the middle part is D. Where, 1.2*D≤L1≤30*D; 2.4*D≤L2≤60*D; 1.2*D≤L3≤30*D; 2.4*D≤L4≤60*D.

10. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-9, characterized in that, include: Provide substrate; A source, a gate, and a drain are fabricated on one side of the substrate, with the gate located between the source and the drain; The gate includes a first end portion and a middle portion, wherein the middle portion, the source, and the drain are all located in the active region, and the first end portion is located in the passive region; The first end portion includes a first sub-end portion and a second sub-end portion; along a first direction, the extension width of the first sub-end portion is greater than the extension width of the middle portion, and the extension width of the second sub-end portion is greater than the extension width of the first end portion; the first direction is parallel to the direction from the source to the drain.

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