Amplifier input offset compensation

Abstract

The present disclosure relates to amplifier input offset compensation. Various examples relate to amplifier circuits and methods for operating amplifier circuits. An amplifier circuit can include a first amplifier stage. The first amplifier stage includes a first amplifier, a first feedback resistor, a second amplifier, a second feedback resistor, and a gain resistor. A first current source can be electrically coupled to provide a first current across the gain resistor in a first direction. A second current source can be electrically coupled to provide a second current across the gain resistor in a second direction opposite the first direction.

Description

[0001] Claiming priority

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 132,257, filed December 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This document generally, but not limited to, relates to amplifier circuits, and particularly, but not limited to, amplifier circuits with input offset compensation. Background Technology

[0004] Amplifier circuits are typically used to amplify signals that include a direct current (DC) or time-varying voltage offset component. An amplifier circuit receiving an input with an offset amplifies the complete input signal, including the input offset and the signal of interest. This can have several negative effects, including limiting the gain of the amplifier circuit. For example, because the input offset is also amplified, the total output of the amplifier circuit may exceed the power rail with a lower gain than might be obtained when measuring the signal of interest alone. The dynamic range of the circuit may also be affected, for example, requiring a higher resolution analog-to-digital converter (ADC). Attached Figure Description

[0005] In the accompanying drawings, which are not necessarily drawn to scale, similar numbers may describe similar parts in different views. Similar numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0006] Figure 1 This is a diagram illustrating an example of an amplifier circuit with input offset compensation.

[0007] Figure 2 This is a diagram showing an example arrangement of an amplifier circuit, and an example sensor capable of providing an input signal with an input signal offset voltage.

[0008] Figure 3 It shows a circuit including feedback control. Figure 1 A diagram showing the layout of the amplifier circuit.

[0009] Figure 4 This is a diagram illustrating an example of an instrumentation amplifier circuit, including an amplifier circuit as the first amplifier stage.

[0010] Figure 5 This is a diagram illustrating an example of an amplifier circuit that uses a current digital-to-analog converter (DAC) to implement current sources for generating currents I1 and I2.

[0011] Figure 6This is a diagram illustrating an example of an amplifier circuit with input offset compensation.

[0012] Figure 7 This is a flowchart illustrating an example of a process flow that can be performed using an amplifier circuit to perform offset compensation.

[0013] Figure 8 This is a flowchart illustrating an example of a process flow that can be performed using an amplifier circuit to perform offset compensation.

[0014] Figure 9 This is a block diagram illustrating a computing device hardware architecture in which a set of instructions or a sequence of instructions can be executed to enable the machine to perform any of the methods discussed herein. Detailed Implementation

[0015] The various examples described herein pertain to circuits and methods for input offset compensation in amplifier arrangements. An example amplifier circuit stage includes a first amplifier and a second amplifier. The first amplifier is in a negative feedback arrangement, with a first feedback resistor electrically coupled between the first amplifier output and the first amplifier inverting input. The second amplifier is also in a negative feedback arrangement, with a second feedback resistor electrically coupled between the second amplifier output and the second amplifier inverting input. Input signals are received at the non-inverting inputs of both the first and second amplifiers. The amplifier circuit also includes a gain resistor electrically coupled between the first and second feedback resistors.

[0016] A first current source and a second current source are electrically coupled to provide a first current and a second current across a gain resistor, wherein the first current and the second current are in opposite directions and can have approximately equal magnitudes. The magnitudes of the first and second currents, as described herein, can be selected to modify the gain of the input signal offset, such as the offset voltage. In some examples, the magnitudes of the first and second currents are chosen to produce a sensor offset gain of one or one unit. In this way, the amplifier circuit can amplify the input signal offset voltage by a factor of two while simultaneously amplifying the signal of interest through the closed-loop gain of the amplifier circuit. In another example, the magnitudes of the first and second currents are chosen so that the input signal output is zero. In this way, the contribution of the input signal offset to the amplifier circuit may be approximately zero.

[0017] Figure 1This diagram illustrates an example of an amplifier circuit 100 with input offset compensation. The amplifier circuit 100 includes a first amplifier 102 and a second amplifier 104. Each amplifier 102, 104 is a differential amplifier, including a respective inverting input (indicated by "-"), a respective non-inverting input (indicated by "+"), and a respective output. An input signal is provided to the amplifier circuit 100 via the non-inverting input (VIN1) of amplifier 102 and the non-inverting input (VIN2) of amplifier 104. The input signal may be the difference between VIN1 and VIN2. The output of the amplifier circuit 100 lies between the output (VO1) of amplifier 102 and the output (VO2) of amplifier 104.

[0018] exist Figure 1 In the example arrangement, amplifier 102 is provided with a negative feedback path, which includes a first feedback resistor R electrically coupled between the output of amplifier 102 and the inverting input of amplifier 102. F1 Amplifier 104 is similarly arranged with a negative feedback path, which includes a second feedback resistor R electrically coupled between the output of amplifier 104 and the inverting input of amplifier 104. F2 In some examples, the first feedback resistor R F1 Second feedback resistor R F2 They have the same value. Gain resistor R G Electrically coupled to the first feedback resistor R F1 With the second feedback resistor R F2 between.

[0019] Amplifier circuit 100 also includes a first current source 106A and a second current source 106B. The first current source 106A provides a first current I1 to the gain resistor R. G The second current source 106B provides a second current I2 to the gain resistor R. G As shown in the figure, the first current I1 and the second current I2 are provided in opposite directions. In this example, the first current I1 flows from the first feedback resistor R. F1 Flow through gain resistor R G And flows to the second feedback resistor R F2 Current sources 106A and 106B can be or include any suitable type of current source, including, for example, a current digital-to-analog converter (DAC) or any other suitable circuitry for generating current.

[0020] The amplitudes of currents I1 and I2 can be selected based on the input signal offset (e.g., input signal offset voltage). In some examples, the amplitudes of currents I1 and I2 are selected to produce a unit or one input offset gain. That is, the input signal offset can be amplified by a factor of two, while the signal of interest can be amplified by the closed-loop gain of amplifier circuit 100. For example, the feedback arrangement of amplifier circuit 100 may cause a voltage VIN1 to appear in the feedback resistor R. F1 and gain resistor R G Between node 108, and voltage VIN2 appears at gain resistor R. G and feedback resistor R F2 Therefore, in order to generate an input signal offset gain of 1, when providing input signal offset across inputs VIN1 and VIN2, the magnitudes of currents I1 and I2 can be selected to set the output voltages VO1 and VO2 to be equal to the inputs VIN1 and VIN2. This is given by the following equation [1]:

[0021]

[0022] In equation [1], Voffset is the input signal offset voltage, given by the following equation [2]:

[0023] Voffset = VIN1 - VIN2 [2]

[0024] Consider an example input signal with a DC input signal offset voltage of 50mV, a signal of interest of 5mV, and a closed-loop gain of 3(3). Set the currents I1 and I2 to be equal to 50mV divided by the gain resistor R. G Outputs can be provided at VO1 and VO2, with an output offset signal voltage of 50mV and a target signal of 15mV.

[0025] In some examples, the magnitudes of currents I1 and I2 are chosen to result in zero input signal offset gain. That is, the input signal offset can be completely or substantially canceled out by the output signals at VO1 and VO2. In some examples, when the input signal offset exists at inputs VIN1 and VIN2, zero input signal offset gain can be achieved by selecting the magnitudes of currents I1 and I2 to drive VO1 and VO2 to a common voltage. In some examples, the common voltage is given by the following equation [3]:

[0026]

[0027] The conditions of formula [3] can be achieved by setting the magnitudes of currents I1 and I2, as shown in the following formula [4]:

[0028]

[0029] In equation [4], the symbol R G / / R F Indicates with R F Parallel R G It can also be given by equation [5]:

[0030]

[0031] In equation [4], Gain is the gain of amplifier circuit 100, given by the following equation [6]:

[0032]

[0033] In some examples, amplifier circuit 100 is implemented via a feedback path between the input signal (VIN1-VIN2) and one or more current sources 106A, 106B that generate currents I1, I2. In this way, current sources 106A, 106B can be configured to change currents I1, I2 to match the input signal offset voltage. For example, if the input signal has a variable offset voltage, the feedback path can cause current sources 106A, 106B to change currents I1, I2 such that the output (VO1-VO2) of the amplifier circuit matches the input signal offset voltage. For example, if amplifier circuit 100 is configured to apply unity gain to the offset, current sources 106A, 106B can change currents I1, I2 according to equation [1]. If amplifier circuit 100 is configured to apply zero gain to the offset, current sources 106A, 106B can change currents I1, I2 according to equation [4].

[0034] Furthermore, in some examples, the magnitudes of currents I1 and I2 are based on a reference voltage. This reference voltage can be generated by any suitable circuit. In some examples, a bandgap voltage reference circuit is used to generate the reference voltage. In another example, the reference voltage is a power supply reference, for example, based on the power supply voltage of amplifier circuit 100.

[0035] Figure 2 This diagram illustrates an example arrangement of amplifier circuit 100, showing example sensors 212A and 212B that can provide input signals with input signal offset voltages to amplifier circuit 100. Sensors 212A and 212B provide sensor output signals at SO1 and SO2, respectively. The sensor output signals generated by sensors 212A and 212B can be provided to amplifier circuit 100. For example, SO1 can be electrically coupled to VIN1 and SO2 can be electrically coupled to VIN2. Amplifier circuit 100 can alternatively be coupled to one of sensors 212A and 212B.

[0036] Figure 2This includes a breakout window 202A displaying an example sensor output signal 222A that can be provided by SO1 and SO2 of sensor 212A. In the breakout window 202A, the horizontal axis represents time, and the vertical axis represents the sensor output signal, illustrated as SO1-SO2. As shown, the sensor output signal 222A of the example sensor 212A includes a DC voltage offset indicated by line 220A. The sensor output signal 222A can be provided as an input signal voltage to amplifier circuit 100, for example at VIN1, VIN2. Examples of sensors that produce a DC input signal offset voltage include, for example, strain gauge sensors, pressure sensors, resistance bridge sensors, etc.

[0037] Figure 2 It also includes a breakout window 202B displaying an example sensor output signal 222B that can be provided by SO1, SO2 of sensor 212B. In the breakout window 202B, the horizontal axis represents time and the vertical axis represents the sensor output signal, illustrated as SO1-SO2. As shown, the sensor output signal 222B of the example sensor 212B includes a changing voltage offset indicated by curve 220B. The sensor output signal 222B can be provided as an input signal voltage to amplifier circuit 100, for example at VIN1, VIN2. Examples of sensors that produce a changing input signal offset voltage include, for example, sensors that measure bioelectrical potential parameters, such as electrocardiogram (EKG) sensors, electromyography (EMG) sensors, electroencephalography (EEG) sensors, electromagnetic flowmeters, etc.

[0038] Figure 3 This is a diagram showing the arrangement of the amplifier circuit 100, including the feedback control circuit 302. The feedback control circuit 302 receives indications from the output of the amplifier circuit 100. Figure 3 In one example, the feedback control circuit 302 receives indications of the output of amplifier 100 at outputs VO1 and VO2. In other examples, the feedback control circuit 302 receives indications of the output of amplifier circuit 100 from other parts of amplifier circuit 100, such as from nodes 108 and 110. This can serve as a supplement to or alternative to receiving feedback from outputs VO1 and VO2.

[0039] Feedback control circuit 302 provides one or more control signals to current sources 106A and 106B. The control signals instruct current sources 106A and 106B to modify currents I1 and I2 to provide the desired offset compensation to the amplifier circuit. In some examples, feedback control circuit 302 is programmed to modify currents I1 and I2 to produce an offset gain of 1 or 1. For example, when an input signal offset is provided across inputs VIN1 and VIN2, feedback control circuit 302 is configured to modify currents I1 and I2 such that output voltages VO1 and VO2 are equal to inputs VIN1 and VIN2. In other examples, feedback control circuit is configured to modify currents I1 and I2 to produce zero offset gain, for example, by driving VO1 and VO2 to a common voltage when an input signal offset exists across inputs VIN1 and VIN2.

[0040] Figure 4 This is a diagram illustrating an example of an instrumentation amplifier circuit 400, including an amplifier circuit 100 as a first amplifier stage. Figure 4 In this example, the outputs VO1 and VO2 of amplifier circuit 100 are provided to a second stage 404, which includes a second-stage amplifier 402, resistors R1 and R2. A first example of resistor R1 is electrically coupled between VO1 and the inverting input of amplifier 402. A second example of resistor R1 is electrically coupled between VO2 and the non-inverting input of amplifier 402. A first example of resistor R2 is electrically coupled between the non-inverting input of amplifier 402 and the reference voltage VREF. A second example of resistor R2 is electrically coupled between the output VOO of amplifier 402 and the inverting input of amplifier 402. The output of the second stage 404 is between VOO and VREF.

[0041] The gain of the first stage is given by the above formula [6]. The closed-loop gain of the output stage 404 can be determined by resistors R1 and R2, for example, as given by the following equation [7]:

[0042]

[0043] In some examples, R1 can be equal to R2, such that the gain of the second stage 404, including amplifier 402, is 1. Figure 4 In the examples, current sources 106A and 106B can be configured to provide currents I1 and I2 to set the offset gain to, for example, uniform or zero, as described herein. In the example where the offset gain of amplifier circuit 100 is set to 1, the contribution of the offset to the output signal VOO can be equal to the offset multiplied by the gain given by equation [7]. In the example where the offset gain of amplifier circuit 100 is zero, the offset may not contribute to VOO. Figure 5This diagram illustrates an example of an amplifier circuit 100, where a current DAC 510 is used to implement current sources for generating currents I1 and I2. The current DAC 510 receives a digital code input (CODE) and a reference voltage (VREF). In response to the digital code input (CODE) and the reference voltage (VREF), the current DAC 510 generates one or more currents I1, I2. In some examples, the digital code and / or reference voltage may be based on a feedback signal indicating an offset voltage from the input signal. For example, the current DAC 510 is used to implement... Figure 3 One example of the feedback circuit 302. In some examples, the reference voltage VREF is provided by a bandgap reference, supply voltage, etc.

[0044] Figure 6 This diagram illustrates an example of an amplifier circuit 600 with input offset compensation. Amplifier circuit 600 has amplifiers 602 and 604, each with its own inverting input (indicated by "-"), its own non-inverting input (indicated by "+"), and its own output. The input signal is provided to amplifier circuit 600 via the non-inverting input (VIN1) of amplifier 602 and the non-inverting input (VIN2) of amplifier 604. The input signal may be the difference between VIN1 and VIN2. The output of amplifier circuit 600 lies between the output (VO1) of amplifier 602 and the output (VO2) of amplifier 604.

[0045] exist Figure 6 In the example arrangement, amplifier 602 is provided with a negative feedback path, which includes a first feedback resistor R electrically coupled between the output of amplifier 602 and the inverting input of amplifier 602. F1 Amplifier 604 is similarly arranged with a negative feedback path, which includes a second feedback resistor R electrically coupled between the output of amplifier 604 and the inverting input of amplifier 604. F2 In some examples, the first feedback resistor R F1 Second feedback resistor R F2 They have the same value. Gain resistor R G Electrically coupled to the first feedback resistor R F1 With the second feedback resistor R F2 between.

[0046] Amplifier circuit 600 also includes a gain resistor R G The first current source 606A provides the first current I1 and the gain resistor R G A second current source 606B provides the second current I2. In the example amplifier circuit 600, the feedback paths of amplifiers 602 and 604 also include their respective compensation resistors R. C1 R C2 (Resistance R)C1 and R C2 They can have the same value and can usually be called R. C In some examples, amplifier circuit 600 is configured to generate unity gain for the input signal offset voltage. In some examples, amplifier circuit 600 (or its control circuitry) can scan currents I1, I2 only if an input signal offset voltage is present at the input. The currents I1, I2 that result in unity gain for the input offset voltage can be selected.

[0047] In other examples, amplifier circuit 600 is configured to generate zero gain of input signal offset voltage by setting the amplitudes of currents I1 and I2 according to the following equation [8]:

[0048]

[0049] In example amplifier circuit 600, if R C The value is much greater than that of the gain resistor R. G Then the dependence of offset compensation on circuit gain can be reduced. For example, it can be seen from formula [8] that if R C The value is much greater than that of the gain resistor R. G For a given input signal offset, the amplitudes of currents I1 and I2 may be relatively constant, without considering circuit gain.

[0050] Figure 7 This is a flowchart illustrating an example of a processing flow 700 that can be performed using an amplifier circuit, such as one of the amplifier circuits 100, 400, and 600 described herein, to perform offset compensation. In operation 702, a first current in the first direction is supplied to the gain resistor R. G The first current can be indicated by I1 and can be provided by current source 106A, 606A, or current DAC 510. In operation 704, a second current in a second direction opposite to the first direction is provided to the gain resistor R. G The second current can be indicated by I2 and can be provided by current sources 106B, 606B, and / or current DAC 510. The first current I1 and the second current I2 can be selected to mitigate input offset, for example, by producing a unity or zero offset gain as described herein. In various examples, the first current I1 is provided simultaneously with the current I2.

[0051] Figure 8This is a flowchart illustrating an example of a processing flow 800 that can be performed using amplifier circuitry, such as one of the amplifier circuits 100, 400, and 600 described herein, to perform offset compensation. For example, process flow 800 can be performed using feedback control circuitry 302 and / or a feedback signal provided to current DAC 510. In operation 802, a first current in a first direction is provided to the gain resistor R. G The first current can be indicated by I1 and can be provided by current source 106A, 606A, or current DAC 510. In operation 804, a second current in a second direction opposite to the first direction is provided to the gain resistor R. G The second current can be indicated by I2 and can be provided by current sources 106B, 606B and / or current DAC 510.

[0052] In operation 806, it is determined whether the offset of the input signal has changed. Operation 806 can be performed, for example, by feedback control circuitry 302, current DAC 510, or any other suitable component. Changes in the input signal offset can be detected in any suitable manner. In some examples, feedback signals indicating the input signals (e.g., VIN1, VIN2, and / or the differences between them) are provided. In other examples, feedback signals indicating the output voltages (e.g., VO1, VO2, and / or the differences between them) are provided. In other examples, additionally or alternatively, feedback signals indicating the state of nodes 108, 608 and 110, 610 are provided.

[0053] If the offset of the input signal does not change, the first and second currents are maintained in operations 802 and 804. If the offset of the input signal changes in operation 806, the first and / or second currents are then modified in operation 808. For example, the first and second currents can be modified to maintain a desired gain (e.g., uniform or zero) against the offset of the input signal. The modified first and second currents can be provided at operations 802 and 804.

[0054] Figure 9 This is a block diagram illustrating a computing device hardware architecture 900, in which an instruction set or sequence of instructions can be executed to cause a machine to perform any of the methods discussed herein. For example, architecture 900 may describe one or more processors or other computing devices that can be used to implement control circuitry to execute process flows 700 and 800 described herein. In other examples, an architecture such as architecture 900 may receive the output of one or more amplifier circuits (such as amplifier circuits 100, 400, and 600 described herein) and perform various processes based on the received signals.

[0055] Architecture 900 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, Architecture 900 can operate as a server or client machine in a server-client network environment, or it can act as a peer machine in a peer-to-peer (or distributed) network environment. Architecture 900 can be implemented in embedded systems, personal computers (PCs), tablet PCs, hybrid tablets, set-top boxes (STBs), personal digital assistants (PDAs), mobile phones, network devices, network routers, network switches, bridges, or any machine capable of executing instructions (sequential or otherwise) that specify the operations to be performed by the machine.

[0056] Example architecture 900 includes a processor unit 902, which includes at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both, a processor core, or a compute node). Architecture 900 may also include main memory 904 and static memory 906, which communicate with each other via link 908 (e.g., a bus). Architecture 900 may also include a video display unit 910, an input device 912 (e.g., a keyboard), and a UI navigation device 914 (e.g., a mouse). In some examples, the video display unit 910, the input device 912, and the UI navigation device 914 are integrated into a touchscreen display. Architecture 900 may additionally include a storage device 916 (e.g., a drive unit), a signal generation device 918 (e.g., a speaker), a network interface device 920, and one or more sensors (not shown), such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors.

[0057] In some examples, processor unit 902 or another suitable hardware component may support hardware interrupts. In response to a hardware interrupt, processor unit 902 may suspend its processing and perform an ISR, for example, as described herein.

[0058] Storage device 916 includes machine-readable medium 922 on which one or more sets of data structures and instructions 924 (e.g., software) are stored, which embody or are used by any one or more methods or functions described herein. Instructions 924 may also reside wholly or at least partially in main memory 904, static memory 906, and / or during execution by architecture 900 in processor unit 902, which also constitute machine-readable medium.

[0059] Executable instructions and machine storage media

[0060] Various memories (i.e., the memories of 904, 906, and / or processor unit 902) and / or storage device 916 may store one or more sets of instructions and data structures (e.g., instructions 924) that embody or are used by any one or more methods or functions described herein. These instructions, when executed by processor unit 902, cause various operations to implement the disclosed examples.

[0061] As used herein, the terms “machine storage medium,” “device storage medium,” and “computer storage medium” (collectively, “machine storage medium”) have the same meaning and are used interchangeably. These terms refer to single or multiple storage devices and / or media that store executable instructions and / or data (e.g., centralized or distributed databases, and / or associated caches and servers), as well as cloud-based storage systems or networks that include multiple storage devices or equipment. Therefore, these terms should be considered to include, but are not limited to, solid-state memory and optical and magnetic media, including memory internal or external to the processor. Specific examples of machine storage media, computer storage media, and / or device storage media include non-volatile memory, such as semiconductor storage devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), field-programmable gate arrays (FPGAs), and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The terms “machine storage medium,” “computer storage medium,” and “device storage medium” explicitly exclude carrier waves, modulated data signals, and other such media, at least some of which are included under the term “signal medium” discussed below.

[0062] signal medium

[0063] The terms "signal medium" or "transmission medium" should be understood to include any form of modulated data signal, carrier wave, etc. The term "modulated data signal" refers to a signal whose one or more characteristics are set or changed in such a way as to encode information in the signal.

[0064] Computer-readable media

[0065] The terms “machine-readable medium,” “computer-readable medium,” and “device-readable medium” have the same meaning and are used interchangeably in this disclosure. These terms are defined to include machine storage media and signal media. Therefore, these terms include storage devices / media and carrier / modulated data signals.

[0066] Instruction 924 can also transmit or receive over communication network 926 using a transmission medium via network interface device 920 using any of a variety of well-known transmission protocols (e.g., Hypertext Transfer Protocol (HTTP)). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, mobile phone networks, common legacy telephone service (POTS) networks, and wireless data networks (e.g., Wi-Fi, 3G, 4G Long Term Evolution (LTE) / LTE-A, 5G, or WiMAX networks).

[0067] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples that provide only those elements shown or described. Furthermore, the inventors also contemplate examples of any combination or arrangement (or one or more aspects thereof) of those elements shown or described, or with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0068] In the event of any inconsistency between the usage in this document and any other document incorporated by reference, the usage in this document shall prevail.

[0069] In this document, the terms “a” or “some” are common in patent documents and are used to include one or more, independent of any other instances or uses of “at least one” or “one or more.” In this document, unless otherwise stated, the term “or” is used to refer to a non-exclusive “or,” for example, “A or B” includes “A but not B,” “B but not A,” and “A and B.” In this document, the terms “comprising” and “wherein” are used as simple equivalents of the corresponding terms “comprising” and “wherein.” Furthermore, in the following claims, the terms “comprising” and “including” are open-ended, meaning a system, apparatus, article, composition, formulation, or process that includes elements other than those listed after such terms. A claim is still considered to fall within the scope of that claim. Additionally, in the appended claims, terms such as “first,” “second,” and “third” are used merely as labels and do not impose numerical requirements on their objects.

[0070] Unless the context otherwise indicates, geometric terms such as “parallel,” “perpendicular,” “circular,” or “square” are not intended to require absolute mathematical precision. Instead, such geometric terms allow for variation due to manufacturing or equivalent functions. For example, if an element is described as “circular” or “approximately circular,” then that description still includes a component that is not exactly circular (e.g., a slightly elongated ellipse or polygonal component).

[0071] The term "circuit" can include dedicated hardware circuits, general-purpose microprocessors, digital signal processors, or other processor circuits, and can be structurally ranged from general-purpose circuits to dedicated circuits, such as those using firmware or software.

[0072] Any one or more of the techniques (e.g., methods) discussed herein can be executed on the machine. In various embodiments, the machine can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine can operate as a server machine, a client machine, or both in a server-client network environment. In one example, the machine can act as a peer-to-peer (P2P) (or other distributed) network environment. The machine can be a personal computer (PC), tablet, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify the actions the machine should take. Furthermore, although only one machine is shown, the term "machine" should also be considered to include any collection of machines that individually or jointly execute a set (or more sets) of instructions to perform any one or more methods discussed herein, such as cloud computing, Software as a Service (SaaS), and other computer cluster configurations.

[0073] As described herein, examples may include logic or multiple components or mechanisms, or those operable by them. A circuit set is a collection of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuit set members can be flexible with time and the variability of the underlying hardware. A circuit set includes members that can perform a specified operation individually or in combination during operation. In the examples, the hardware of the circuit set can be invariably designed to perform a specific operation (e.g., hardwired). In one example, the hardware of the circuit set may include physically connected components (e.g., execution units, transistors, simple circuits, etc.) and a computer-readable medium that encodes instructions for a specific operation through physical modifications (e.g., magnetism, electricity, movable placement of particles with invariant mass, etc.). When the physical components are connected, the basic electrical characteristics of the hardware components change, for example, from an insulator to a conductor, and vice versa. Instructions can enable embedded hardware (e.g., execution units or loading mechanisms) to create members of the circuit set in the hardware through variable connections to perform portions of a specific operation during operation. Thus, when the device is running, the computer-readable medium is communicatively coupled to other components of the circuit set members. In one example, any physical component can be used in more than one member of more than one circuit group. For example, in operation, an execution unit can be used in a first circuit of a first circuit group at one point in time and reused by a second circuit in the first circuit group or by a third circuit in a second circuit group at a different time.

[0074] Specific implementations of the systems and methods described herein may involve the use of a machine (e.g., a computer system) that may include a hardware processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), main memory, and static memory, some or all of which may communicate with each other via interconnect (e.g., a bus). The machine may also include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In one example, the display unit, input device, and UI navigation device may be a touchscreen display. The machine may additionally include storage devices (e.g., a drive unit), signal generating devices (e.g., a speaker), network interface devices, and one or more sensors, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine may include an output controller, such as a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0075] Storage devices may include machine-readable media on which one or more sets of data structures or instructions (e.g., software) are stored, which embody or be used by any or more of the techniques or functions described herein. During machine execution of the instructions, the instructions may also reside wholly or at least partially in main memory, static memory, or a hardware processor. In one example, one or any combination of a hardware processor, main memory, static memory, or storage device may constitute a machine-readable medium.

[0076] While machine-readable media may include a single medium, the term “machine-readable media” may include a single medium or multiple media configured to store one or more instructions (e.g., a centralized or distributed database, and / or associated caches and servers).

[0077] The term "machine-readable medium" can include any medium capable of storing, encoding, or carrying machine-executable instructions and causing the machine to perform any one or more of the techniques disclosed herein, or a data structure capable of storing, encoding, or carrying data used by or associated with such instructions. Examples of non-limiting machine-readable media can include solid-state memory as well as optical and magnetic media. In one example, a collection of machine-readable media includes machine-readable media having multiple particles with invariant (e.g., rest) masses. Therefore, mass machine-readable media are not transiently propagating signals. Specific examples of mass machine-readable media can include: non-volatile memory, such as semiconductor storage devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0078] Instructions can be further transmitted or received via a network interface device using a communication network through a transmission medium, utilizing any of a variety of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks can include Local Area Networks (LANs), Wide Area Networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), ordinary old-style telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard series). The IEEE 902.16 standard series is called This includes standards such as the IEEE 902.15.4 series and peer-to-peer (P2P) networks. In one example, a network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to a communication network. In one example, a network interface device may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be understood to include any intangible medium capable of storing, encoding, or carrying machine-executable instructions, and includes digital or analog communication signals or other intangible media that facilitate such software communication.

[0079] The method examples described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of this method may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video disks), magnetic tapes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0080] Example 1 is an amplifier circuit for compensating for input signal voltage offset. The amplifier circuit includes: a first amplifier stage, comprising: a first amplifier including a first inverting input, a first non-inverting input, and a first output; a first feedback resistor electrically coupled between the inverting input of the first amplifier and the output of the first amplifier; a second amplifier including a second inverting input, a second non-inverting input, and a second output; a second feedback resistor electrically coupled between the second inverting input of the second amplifier and the second output of the second amplifier; a gain resistor electrically coupled between the first feedback resistor and the second feedback resistor; a first current source electrically coupled to provide a first current across the gain resistor; and a second current source electrically coupled to provide a second current across the gain resistor, the second current having a direction opposite to the first current.

[0081] In Example 2, the essence of Example 1 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

[0082] In Example 3, the essence of any one or more of Examples 1–2 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

[0083] In Example 4, the subject matter of any one or more of Examples 1–3 optionally includes: a current-to-analog converter having a voltage reference input and a digital code input, the current-to-analog converter being electrically coupled to provide a first current across the gain resistor in response to the voltage reference input and the digital code input.

[0084] In Example 5, the subject of Example 4 optionally includes: a bandgap voltage reference circuit electrically coupled to provide a voltage reference signal to the voltage reference input.

[0085] In Example 6, the subject of any one or more of Examples 1–5 optionally includes: the input signal voltage offset is variable, wherein the first current source is a variable current source configured to change the first current at least in part based on the input signal voltage.

[0086] In Example 7, the subject matter of any one or more of Examples 1–6 optionally includes: a compensation resistor electrically coupled between the first current source and the gain resistor.

[0087] In Example 8, the subject of any one or more of Examples 1–7 optionally includes: a second amplifier stage electrically coupled to the first output and the second output, the second amplifier stage including a second amplifier stage output.

[0088] Example 9 is a method for operating an amplifier circuit to mitigate input signal voltage offset, the amplifier circuit including a first amplifier, a second amplifier, a first feedback resistor electrically coupled between an inverting input of the first amplifier and an output of the first amplifier, a second feedback resistor electrically coupled between an inverting input of the second amplifier and an output of the second amplifier, and a gain resistor electrically coupled between the first feedback resistor and the second feedback resistor, the method comprising: providing a first current across the gain resistor in a first direction; and providing a second current across the gain resistor in a second direction opposite to the first direction.

[0089] In Example 10, the main idea of ​​Example 9 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

[0090] The essence of any one or more of Examples 11, 9–10 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

[0091] In Example 12, the subject matter of any one or more of Examples 9–11 optionally includes: providing a digital code to a current-to-analog converter; and in response to the digital code, providing a first current by the current-to-analog converter.

[0092] In Example 13, the main idea of ​​Example 12 optionally includes: providing a reference voltage to the current digital-to-analog converter.

[0093] In Example 14, the main idea of ​​Example 13 optionally includes: generating the reference voltage using a bandgap voltage reference circuit.

[0094] The essence of any one or more of Examples 15, 9–14 optionally includes: the input signal voltage offset is variable, and also includes changing the first current based at least in part on the input signal voltage offset.

[0095] Example 16 is an amplifier circuit for compensating for input signal voltage offset, comprising: a first amplifier; a second amplifier; a first feedback resistor electrically coupled between the inverting input of the first amplifier and the output of the first amplifier; a second feedback resistor electrically coupled between the inverting input of the second amplifier and the output of the second amplifier; and a gain resistor electrically coupled between the first feedback resistor and the second feedback resistor; a component for providing a first current across the gain resistor in a first direction; and a component for providing a second current across the gain resistor in a second direction opposite to the first direction.

[0096] In Example 17, the essence of Example 16 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

[0097] The essence of any one or more of Examples 18, 16–17 optionally includes: the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

[0098] The subject of any one or more of Examples 19, 16–18 optionally includes: the component for providing a first current across the gain resistor includes a bandgap voltage reference circuit.

[0099] The essence of any one or more of Examples 20, 16–19 optionally includes: the input signal voltage offset is variable, and also includes a component for changing the first current based at least in part on the input signal voltage offset.

[0100] The above description is intended to be illustrative and not restrictive. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art after reading the above description. The abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. It is understood that this submission is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be combined together to simplify this disclosure. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated in the detailed description as examples or embodiments, each claim being an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents conferred by those claims.

Claims

1. An amplifier circuit for compensating for input signal voltage offset, the amplifier circuit comprising: The first amplifier stage includes: The first amplifier includes a first inverting input, a first non-inverting input, and a first output; The first feedback resistor is electrically coupled between the first inverting input and the first output; The second amplifier includes a second inverting input, a second non-inverting input, and a second output; The second feedback resistor is electrically coupled between the second inverting input of the second amplifier and the second output of the second amplifier. A gain resistor is electrically coupled between the first feedback resistor and the second feedback resistor; A first current source, electrically coupled to provide a first current across the gain resistor; and A second current source, electrically coupled to provide a second current across the gain resistor, the second current having a direction opposite to the first current; and A first compensation resistor electrically coupled between the first current source and the gain resistor, and / or a second compensation resistor electrically coupled between the second current source and the gain resistor.

2. The amplifier circuit of claim 1, wherein the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

3. The amplifier circuit of claim 1, wherein the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

4. The amplifier circuit of claim 1, wherein the first current source comprises a current digital-to-analog converter having a voltage reference input and a digital code input, the current digital-to-analog converter being electrically coupled to provide a first current across the gain resistor in response to the voltage reference input and the digital code input.

5. The amplifier circuit of claim 4 further includes a bandgap voltage reference circuit electrically coupled to provide a voltage reference signal to the voltage reference input.

6. The amplifier circuit of claim 1, wherein the input signal voltage offset is variable, and wherein the first current source is a variable current source configured to change the first current at least in part based on the input signal voltage.

7. The amplifier circuit of claim 1 further includes a second amplifier stage electrically coupled to the first output and the second output, the second amplifier stage including a second amplifier stage output.

8. A method for operating an amplifier circuit to mitigate input signal voltage offset, the amplifier circuit including a first amplifier, a second amplifier, a first feedback resistor electrically coupled between an inverting input of the first amplifier and an output of the first amplifier, a second feedback resistor electrically coupled between an inverting input of the second amplifier and an output of the second amplifier, and a gain resistor electrically coupled between the first feedback resistor and the second feedback resistor, the method comprising: A first current source is used to provide a first current across the gain resistor in a first direction; and A second current source is used to provide a second current across the gain resistor in a second direction opposite to the first direction. The amplifier circuit includes a first compensation resistor electrically coupled between the first current source and the gain resistor and / or a second compensation resistor electrically coupled between the second current source and the gain resistor.

9. The method of claim 8, wherein the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

10. The method of claim 8, wherein the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

11. The method of claim 8, further comprising: Provide digital codes to the current-to-analog converter of the first current source; and In response to the digital code, a first current is provided by the current-to-analog converter.

12. The method of claim 11, further comprising providing a reference voltage to the current-to-analog converter.

13. The method of claim 12, further comprising generating the reference voltage using a bandgap voltage reference circuit.

14. The method of claim 8, wherein the input signal voltage offset is variable, and the method further comprises changing the first current at least in part based on the input signal voltage offset.

15. An amplifier circuit for compensating for input signal voltage offset, comprising: First amplifier; Second amplifier; A first feedback resistor electrically coupled between the inverting input of the first amplifier and the output of the first amplifier; A second feedback resistor electrically coupled between the inverting input of the second amplifier and the output of the second amplifier, and a gain resistor electrically coupled between the first feedback resistor and the second feedback resistor; A first component for providing a first current across the gain resistor in a first direction; A second component for providing a second current across the gain resistor in a second direction opposite to the first direction; and A first compensation resistor electrically coupled between the first component and the gain resistor, and / or a second compensation resistor electrically coupled between the second component and the gain resistor.

16. The amplifier circuit of claim 15, wherein the magnitude of the first current is equal to the input signal voltage offset divided by the gain resistor.

17. The amplifier circuit of claim 15, wherein the magnitude of the first current is equal to the input signal voltage offset divided by an amount based on the gain resistor, the first feedback resistor, and the second feedback resistor.

18. The amplifier circuit of claim 15, wherein the component for providing a first current across the gain resistor includes a bandgap voltage reference circuit.

19. The amplifier circuit of claim 15, wherein the input signal voltage offset is variable, and the amplifier circuit further includes a component for changing the first current at least in part based on the input signal voltage offset.

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