Power-on reset circuit

Abstract

The present invention discloses a power-on reset circuit, which includes a main POR unit, a POR module, and a level conversion module; the power supply terminal of the main POR unit is electrically connected to the main voltage source; the POR module includes at least one sub-POR unit, and the power supply terminal of the sub-POR unit is electrically connected to a sub-voltage source; the input terminal of the level conversion module is electrically connected to the output terminal of the sub-POR unit, and the level conversion module is used to convert the signal at its input terminal into a signal in the voltage domain corresponding to the main voltage source and output it at its output terminal; when the output signal of the sub-POR unit is in the first state, the output terminal of the level conversion module is used to enable the main POR unit; when the output signal of the sub-POR unit is in the second state, the output terminal of the level conversion module is used to disable the main POR unit. The present invention is not affected by the power-on time and power-on sequence of the voltage sources in multiple voltage domains, and can provide accurate and stable power-on reset / release signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of power-on reset circuits, and particularly relates to a power-on reset circuit. Background Art

[0002] In analog-digital hybrid chips and SoC (System on Chip) chips, a power-on reset circuit POR (Power-On-Reset) is used to generate important initialization signals. During the power-on startup process of the chip, the initial states of all internal registers are in an uncertain state. Especially for registers used for reading and writing, if they are directly operated without reset initialization, incorrect data will be read. Therefore, a reset signal needs to be applied to all internal registers to make them enter a preset initial state. Considering that the power supply network has different propagation and establishment paths inside the circuit, an uncertain register output voltage value will be generated. Therefore, the Reset signal is usually released after the power supply voltage is stable, and the POR circuit monitors the power supply voltage.

[0003] The existing power-on reset circuit is as Figure 1 shown, and is composed of transistors M1 to M5, resistors R1 and R2, capacitor C, and two inverters INV1 and INV2. The voltage to be monitored is VDD, which is also used as the power supply voltage of the power-on reset circuit. In Figure 1 the shown circuit, resistor R1 and capacitor C form a delay circuit to filter out the glitches on the voltage VDD to be monitored; transistors M1, M2, M3, M4, and resistor R2 form a level detection circuit; the two inverters INV1 and INV2 play a shaping role on the POR output waveform. The working process of the power-on reset circuit is as follows: During the power-on startup process, the power supply voltage VDD rises from 0V to the target operating voltage. Due to the existence of resistor R1 and capacitor C, the voltage of node node1 rises slowly following the VDD voltage. When the node voltage V(node1) is greater than the threshold V of NMOS transistor M1 th,M1 , M1 turns on, and current flows through resistor R2, and the voltage of node node2 rises accordingly. Until the node voltage V(node2)>V thn,M2 + V dsn,M3 , the voltage of node node3 starts to drop until it is lower than the threshold of inverter INV1 and its logic level flips. In this way, a positive voltage pulse will be generated at node node3. After being shaped by two inverters, a positive voltage pulse waveform por in the VDD voltage domain is obtained. For details, see Figure 2The output signal por is used to control the reset or release of the target circuit. When the output signal por is at a high level, the target circuit is in a reset state; at the falling edge of the output signal por, the target circuit is released, and then, during the period when the output signal por is at a low level (i.e., during t1), the target circuit enters the working state. In addition, the NMOS transistor M5 plays a hysteresis role, and the final determination of the stable voltage threshold at which the detection voltage VDD arrives is determined by the resistive voltage division of the PMOS transistor M4 and the NMOS transistors M2 and M3.

[0004] With the development of integrated circuits and the continuous improvement of chip complexity and integration, mixed-signal chips and SoC chips usually have multiple power supply voltage domains (N≥2). Referring to Figure 3 , in an application scenario taking an ADC (Analog-to-Digital Converter) chip as an example, in addition to being powered by an external analog power supply Vcc and a digital interface power supply Vdrive (where the digital interface power supply Vdrive powers the digital interface I / O), the chip also integrates two linear regulators LDO (i.e., the illustrated ALDO and DLDO) internally to generate a digital power supply voltage dvdd and an analog power supply voltage avdd for the low voltage domain to power the digital circuit and the analog circuit respectively. In actual applications, the POR circuit needs to meet the following functions: until the four voltages of the chip power supply Vcc, the digital interface power supply Vdrive, the digital power dvdd, and the analog power avdd all reach stability, then release the global reset signal of the chip to initialize all registers. If the existing POR circuit shown in Figure 1 is adopted, on the one hand, only monitoring the voltage of one power supply domain requires predicting which power supply voltage domain is the last stable power supply voltage value, which limits the power-on sequence of the multiple voltage domains of the chip. And in a complex SoC design, different power-on times will result in different power-on sequences of the power supply voltage domains, and a single existing POR circuit is difficult to handle the intricate power-on situations. On the other hand, if a POR circuit is placed on each power supply voltage domain respectively, the multiple POR signals are not synchronized, which will lead to unstable power-on reset and affect the normal operation of the SoC. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the defect of unstable power-on reset in a multi-voltage domain circuit in the prior art and provide a power-on reset circuit.

[0006] The present invention solves the above technical problem through the following technical solutions:

[0007] The present invention provides a power-on reset circuit, including a main POR unit, a POR module, and a level conversion module;

[0008] The power supply terminal of the main POR unit is electrically connected to the main voltage source;

[0009] The POR module includes at least one secondary POR unit, and the power supply terminal of the secondary POR unit is electrically connected to a secondary voltage source;

[0010] The input terminal of the level conversion module is electrically connected to the output terminal of the secondary POR unit. The level conversion module is used to convert the signal at its input terminal to a signal in the voltage domain corresponding to the main voltage source and output it at its output terminal;

[0011] When the output signal of the secondary POR unit is in the first state, the output terminal of the level conversion module is used to enable the main POR unit; when the output signal of the secondary POR unit is in the second state, the output terminal of the level conversion module is used to disable the main POR unit;

[0012] The output terminal of the main POR unit serves as the output terminal of the power-on reset circuit.

[0013] Preferably, the main POR unit includes a switch module, and the output terminal of the level conversion module is used to control the conduction or disconnection of the switch module to enable or disable the main POR unit.

[0014] Preferably, the POR module includes n secondary POR units, the level conversion module includes n level conversion units, the switch module includes n switch units, and the n switch units are connected in series;

[0015] The power supply terminal of the i-th secondary POR unit is correspondingly electrically connected to the i-th secondary voltage source;

[0016] The output terminal of the i-th secondary POR unit is electrically connected to the input terminal of the i-th level conversion unit;

[0017] The output terminal of the i-th level conversion unit is used to control the conduction or disconnection of the i-th switch unit; i ∈ [1, n], and n is a positive integer greater than or equal to 2;

[0018] The voltages of any two secondary voltage sources are not equal.

[0019] Preferably, the level conversion unit includes a first conversion PMOS transistor, a second conversion PMOS transistor, a first conversion NMOS transistor, a second conversion NMOS transistor, a third conversion NMOS transistor, and a fourth conversion NMOS transistor;

[0020] The source electrodes of the first conversion PMOS transistor and the second conversion PMOS transistor are electrically connected to the main voltage source. The gate electrode of the first conversion PMOS transistor serves as the input terminal of the level conversion unit and is electrically connected to the gate electrode of the second conversion NMOS transistor. The drain electrode of the first conversion PMOS transistor is electrically connected to the drain electrode of the first conversion NMOS transistor, the gate electrode of the second conversion PMOS transistor, and the gate electrode of the fourth conversion NMOS transistor;

[0021] The source of the first conversion NMOS transistor is electrically connected to the drain of the second conversion NMOS transistor. The gates of the first conversion NMOS transistor and the third conversion NMOS transistor are electrically connected to the main voltage source, and the source of the second conversion NMOS transistor is grounded.

[0022] The drain of the second conversion PMOS transistor serves as the output terminal of the level conversion unit and is electrically connected to the drain of the third conversion NMOS transistor. The source of the third conversion NMOS transistor is electrically connected to the drain of the fourth conversion NMOS transistor, and the source of the fourth conversion NMOS transistor is grounded.

[0023] Preferably, the first conversion PMOS transistor, the first conversion NMOS transistor, and the second conversion NMOS transistor are thick gate transistors.

[0024] Preferably, the switch unit includes a switch NMOS transistor.

[0025] The main POR unit includes a first resistor, a second resistor, a capacitor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first inverter, and a second inverter. The fourth MOS transistor is a PMOS transistor, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fifth MOS transistor are NMOS transistors.

[0026] One end of the first resistor, the drain of the first MOS transistor, and the source of the fourth MOS transistor are electrically connected to the main voltage source.

[0027] The other end of the first resistor and one end of the capacitor are electrically connected to the gate of the first MOS transistor, and the other end of the capacitor is grounded.

[0028] The source of the first MOS transistor, one end of the second resistor, and the gates of the second MOS transistor and the third MOS transistor are electrically connected, and the other end of the second resistor is grounded.

[0029] The drain of the fourth MOS transistor, the input terminal of the first inverter, and the drain of the second MOS transistor are electrically connected.

[0030] The source of the second MOS transistor, the drain of the third MOS transistor, and the drain of the fifth MOS transistor are electrically connected.

[0031] The source of the third MOS transistor is electrically connected to the drain of the first switch NMOS transistor.

[0032] The source of the j-th switch NMOS transistor is electrically connected to the drain of the (j + 1)-th switch NMOS transistor, where j ∈ [1, n - 1]. The source of the n-th switch NMOS transistor is grounded.

[0033] The source of the fifth MOS transistor is grounded. The gate of the fifth MOS transistor, the output terminal of the first inverter, and the input terminal of the second inverter are electrically connected. The output terminal of the second inverter serves as the output terminal of the main POR unit.

[0034] The gate of the i-th switching NMOS transistor is electrically connected to the output terminal of the i-th level conversion unit, where i ∈ [1, n].

[0035] Preferably, the POR module includes n sub-POR units, and the level conversion module includes n input terminals and one output terminal.

[0036] The output terminal of the i-th sub-POR unit is electrically connected to the i-th input terminal of the level conversion module; i ∈ [1, n], and n is a positive integer greater than or equal to 2.

[0037] The voltages of any two sub-voltage sources are not equal.

[0038] Preferably, the level conversion module includes n input PMOS transistors, n input NMOS transistors, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first PMOS transistor.

[0039] The gate of the i-th input PMOS transistor serves as the i-th input terminal of the level conversion module and is electrically connected to the gate of the i-th input NMOS transistor, where i ∈ [1, n].

[0040] The sources of the n input PMOS transistors are all electrically connected to the main voltage source, and the drains of the n input PMOS transistors are electrically connected to the drain of the first NMOS transistor, the gate of the first PMOS transistor, and the gate of the third NMOS transistor.

[0041] The gates of the first NMOS transistor and the second NMOS transistor are electrically connected to the main voltage source. The source of the first NMOS transistor is electrically connected to the drain of the first input NMOS transistor. The source of the i-th input NMOS transistor is electrically connected to the drain of the (i + 1)-th input NMOS transistor. The source of the n-th input NMOS transistor is grounded.

[0042] The source of the first PMOS transistor is electrically connected to the main voltage source. The drain of the first PMOS transistor serves as the output terminal of the level conversion module and is electrically connected to the drain of the second NMOS transistor.

[0043] The source of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded.

[0044] Preferably, the switching unit includes a switching NMOS transistor.

[0045] The main POR unit includes a first resistor, a second resistor, a capacitor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first inverter, and a second inverter; the fourth MOS transistor is a PMOS transistor, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fifth MOS transistor are NMOS transistors;

[0046] One end of the first resistor, the drain of the first MOS transistor, and the source of the fourth MOS transistor are electrically connected to the main voltage source;

[0047] The other end of the first resistor and one end of the capacitor are electrically connected to the gate of the first MOS transistor, and the other end of the capacitor is grounded;

[0048] The source of the first MOS transistor, one end of the second resistor, the gate of the second MOS transistor, and the gate of the third MOS transistor are electrically connected, and the other end of the second resistor is grounded;

[0049] The drain of the fourth MOS transistor, the input terminal of the first inverter, and the drain of the second MOS transistor are electrically connected;

[0050] The source of the second MOS transistor, the drain of the third MOS transistor, and the drain of the fifth MOS transistor are electrically connected;

[0051] The source of the third MOS transistor is electrically connected to the drain of the switch NMOS transistor;

[0052] The source of the switch NMOS transistor is grounded;

[0053] The source of the fifth MOS transistor is grounded. The gate of the fifth MOS transistor, the output terminal of the first inverter, and the input terminal of the second inverter are electrically connected, and the output terminal of the second inverter serves as the output terminal of the main POR unit;

[0054] The gate of the switch NMOS transistor is electrically connected to the output terminal of the level conversion module.

[0055] Preferably, the voltage of the main voltage source is less than the voltage of the secondary voltage source.

[0056] Preferably, the secondary POR unit includes an eleventh resistor, a twelfth resistor, a first capacitor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, an eleventh inverter, and a twelfth inverter; the fourteenth MOS transistor M14 is a PMOS transistor, and the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the fifteenth MOS transistor are NMOS transistors;

[0057] One end of the eleventh resistor, the drain of the eleventh MOS transistor, and the source of the fourteenth MOS transistor are electrically connected to the secondary voltage source;

[0058] The gate of the fourteenth MOS transistor is grounded; the other end of the eleventh resistor and one end of the first capacitor are electrically connected to the gate of the eleventh MOS transistor, and the other end of the first capacitor is grounded; the source of the eleventh MOS transistor, one end of the twelfth resistor, and the gate of the twelfth MOS transistor are electrically connected to the gate of the thirteenth MOS transistor, and the other end of the twelfth resistor is grounded; the drain of the fourteenth MOS transistor, the input end of the eleventh inverter are electrically connected to the drain of the twelfth MOS transistor; the source of the twelfth MOS transistor, the drain of the thirteenth MOS transistor are electrically connected to the drain of the fifteenth MOS transistor; the source of the thirteenth MOS transistor and the source of the fifteenth MOS transistor are grounded, the gate of the fifteenth MOS transistor, the output end of the eleventh inverter are electrically connected to the input end of the twelfth inverter, the output end of the twelfth inverter is electrically connected to the input end of the thirteenth inverter, and the output end of the thirteenth inverter serves as the output end of the secondary POR unit.

[0059] The positive and progressive effects of the present invention are as follows: The present invention is not affected by the power-on time and power-on sequence of the voltage sources in multiple voltage domains, and can provide accurate and stable power-on reset / release signals. Description of the Drawings

[0060] Figure 1 It is a schematic structural diagram of a power-on reset circuit in the prior art.

[0061] Figure 2 It is a signal waveform diagram of a power-on reset circuit in the prior art.

[0062] Figure 3 It is a schematic partial structural diagram of a multi-power voltage domain chip in the prior art.

[0063] Figure 4 It is a schematic diagram of the power-on reset circuit of Embodiment 1 of the present invention.

[0064] Figure 5 It is a schematic circuit diagram of the power-on reset circuit of Embodiment 1 of the present invention.

[0065] Figure 6 It is a schematic structural diagram of the first secondary POR unit of the power-on reset circuit of Embodiment 1 of the present invention.

[0066] Figure 7 It is a timing diagram of the signal of the first secondary POR unit of the power-on reset circuit of Embodiment 1 of the present invention.

[0067] Figure 8 It is a schematic structural diagram of the first level conversion unit of the power-on reset circuit of Embodiment 1 of the present invention.

[0068] Figure 9 It is a timing diagram of a power-on situation of the power-on reset circuit of Embodiment 1 of the present invention.

[0069] Figure 10 Schematic diagram of the power-on reset circuit according to Embodiment 2 of the present invention.

[0070] Figure 11 Schematic diagram of the level conversion module of the power-on reset circuit according to Embodiment 2 of the present invention. Detailed implementation manners

[0071] The present invention will be further described below by way of embodiments, but the present invention is not limited to the scope of the described embodiments.

[0072] Embodiment 1

[0073] This embodiment provides a power-on reset circuit. Refer to Figure 4 , the power-on reset circuit includes a main POR unit 1, a POR module 2, and a level conversion module 3. The power supply terminal of the main POR unit 1 is electrically connected to the main voltage source; the POR module 2 includes at least one sub-POR unit, and the power supply terminal of the sub-POR unit is electrically connected to a sub-voltage source; the input terminal of the level conversion module 3 is electrically connected to the output terminal of the sub-POR unit, and the level conversion module 3 is used to convert the signal at its input terminal to a signal in the voltage domain corresponding to the main voltage source and output it at its output terminal; when the output signal of the sub-POR unit is in the first state, the output terminal of the level conversion module 3 is used to turn on the main POR unit 1; when the output signal of the sub-POR unit is in the second state, the output terminal of the level conversion module 3 is used to turn off the main POR unit 1; the output terminal of the main POR unit 1 serves as the output terminal of the power-on reset circuit.

[0074] Specifically, the main POR unit 1 includes a switch module, and the output terminal of the level conversion module 3 is used to control the conduction or disconnection of the switch module to control the turning on or off of the main POR unit 1.

[0075] As an optional implementation manner, refer to Figure 5 , the POR module 2 includes two sub-POR units, namely a first sub-POR unit 201 and a second sub-POR unit 202. The level conversion module 3 includes two level conversion units, namely a first level conversion unit 301 and a second level conversion unit 302. The switch module 4 includes two switch units, and the two switch units are connected in series. Refer to Figure 5 , these two switch units are respectively the sixth MOS transistor M6 and the seventh MOS transistor M7.

[0076] The power supply terminal of the first sub-POR unit 201 is electrically connected to the first sub-voltage source VCC1, and the power supply terminal of the second sub-POR unit 202 is electrically connected to the second sub-voltage source VCC2, wherein the voltage of the first sub-voltage source VCC1 is not equal to the voltage of the second sub-voltage source VCC2, and both are greater than the voltage of the main voltage source VDD.

[0077] The output terminal prob_vcc1 of the first sub-POR unit 201 is electrically connected to the input terminal of the first level conversion unit 301, and the output terminal prob_vcc2 of the second sub-POR unit 202 is electrically connected to the input terminal of the second level conversion unit 302.

[0078] In an alternative embodiment, the structure of the first sub-POR unit 201 is as Figure 6 shown. The first sub-POR unit 201 includes an eleventh resistor R11, a twelfth resistor R12, a first capacitor C1, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, an eleventh inverter INV11, and a twelfth inverter INV12. The fourteenth MOS transistor M14 is a PMOS transistor, and the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, and the fifteenth MOS transistor M15 are NMOS transistors.

[0079] One end of the eleventh resistor R11, the drain of the eleventh MOS transistor M11, and the source of the fourteenth MOS transistor M14 are electrically connected to the first sub-voltage source VCC1; the gate of the fourteenth MOS transistor M14 is grounded; the other end of the eleventh resistor R11 and one end of the first capacitor C1 are electrically connected to the gate of the eleventh MOS transistor M11, and the other end of the first capacitor C1 is grounded; the source of the eleventh MOS transistor M11, one end of the twelfth resistor R12, and the gates of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are electrically connected; the other end of the twelfth resistor R12 is grounded; the drain of the fourteenth MOS transistor M14 and the input terminal of the eleventh inverter INV11 are electrically connected to the drain of the twelfth MOS transistor M12; the source of the twelfth MOS transistor M12 and the drain of the thirteenth MOS transistor M13 are electrically connected to the drain of the fifteenth MOS transistor M15; the source of the thirteenth MOS transistor M13 and the source of the fifteenth MOS transistor M15 are grounded, the gate of the fifteenth MOS transistor M15 and the output terminal of the eleventh inverter INV11 are electrically connected to the input terminal of the twelfth inverter INV12, and the output terminal prob_vcc1 of the thirteenth inverter INV13 serves as the output terminal of the first sub-POR unit 201.

[0080] Referring to Figure 7 , during the process of the voltage of the first sub-voltage source VCC1 rising, a positive voltage pulse is generated at the node por1. Correspondingly, during t2, prob_vcc1 outputs a high level, which indicates that the first sub-voltage source VCC1 has been successfully powered on.

[0081] The structure of the second POR unit 202 is the same as that of the first POR unit 201, and the second POR unit 202 operates in the voltage domain corresponding to the second voltage source VCC2.

[0082] Referring to Figure 8 , the first level conversion unit 301 includes a first conversion PMOS transistor PM1, a second conversion PMOS transistor PM2, a first conversion NMOS transistor NM1, a second conversion NMOS transistor NM2, a third conversion NMOS transistor NM3, and a fourth conversion NMOS transistor NM4.

[0083] The sources of the first conversion PMOS transistor PM1 and the second conversion PMOS transistor PM2 are electrically connected to the main voltage source VDD. The gate of the first conversion PMOS transistor PM1 serves as the input terminal of the first level conversion unit 301 and is electrically connected to the gate of the second conversion NMOS transistor NM2. The drain of the first conversion PMOS transistor PM1 is electrically connected to the drain of the first conversion NMOS transistor NM1, the gate of the second conversion PMOS transistor PM2, and the gate of the fourth conversion NMOS transistor NM4. The source of the first conversion NMOS transistor NM1 is electrically connected to the drain of the second conversion NMOS transistor NM2. The gates of the first conversion NMOS transistor NM1 and the third conversion NMOS transistor NM3 are electrically connected to the main voltage source VDD, and the source of the second conversion NMOS transistor NM2 is grounded. The drain of the second conversion PMOS transistor PM2 serves as the output terminal of the first level conversion unit 301 and is electrically connected to the drain of the third conversion NMOS transistor NM3. The source of the third conversion NMOS transistor NM3 is electrically connected to the drain of the fourth conversion NMOS transistor NM4, and the source of the fourth conversion NMOS transistor NM4 is grounded.

[0084] The structure of the second level conversion unit 302 is similar to that of the first level conversion unit 301 and will not be elaborated here.

[0085] To improve the breakdown voltage performance, as an optional implementation manner, the transistors used in the first stage of the level conversion unit are thick-gate transistors. Taking Figure 8 the shown structure as an example, the first conversion PMOS transistor PM1, the first conversion NMOS transistor NM1, and the second conversion NMOS transistor NM2 are thick-gate transistors.

[0086] In an optional implementation manner, the main POR unit 1 includes a first resistor R1, a second resistor R2, a capacitor C, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first inverter INV1, a second inverter INV2, a first switch NMOS transistor M6, and a second switch NMOS transistor M7. The fourth MOS transistor M4 is a PMOS transistor, and the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fifth MOS transistor M5 are NMOS transistors.

[0087] One end of the first resistor R1, the drain of the first MOS transistor M1, and the source of the fourth MOS transistor M4 are electrically connected to the main voltage source VDD; the other end of the first resistor R1 and one end of the capacitor C are electrically connected to the gate of the first MOS transistor M1, and the other end of the capacitor C is grounded; the source of the first MOS transistor M1, one end of the second resistor R2, the gate of the second MOS transistor M2, and the gate of the third MOS transistor M3 are electrically connected, and the other end of the second resistor R2 is grounded; the drain of the fourth MOS transistor M4, the input terminal of the first inverter INV1, and the drain of the second MOS transistor M2 are electrically connected; the source of the second MOS transistor M2, the drain of the third MOS transistor M3, and the drain of the fifth MOS transistor M5 are electrically connected; the source of the third MOS transistor M3 is electrically connected to the drain of the first switching NMOS transistor M6; the source of the first switching NMOS transistor M6 is electrically connected to the drain of the second switching NMOS transistor M7, and the source of the second switching NMOS transistor M7 is grounded; the source of the fifth MOS transistor M5 is grounded, the gate of the fifth MOS transistor M5, the output terminal of the first inverter INV1, and the input terminal of the second inverter INV2 are electrically connected, and the output terminal of the second inverter INV2 serves as the output terminal por of the main POR unit 1; the gate of the first switching NMOS transistor M6 is electrically connected to the output terminal vcc1_ok of the first level conversion unit 301, and the gate of the second switching NMOS transistor M7 is electrically connected to the output terminal vcc2_ok of the second level conversion unit 302.

[0088] On the one hand, according to Figure 5 the power-on reset circuit shown, local structures can be reasonably omitted, thereby obtaining a power-on reset circuit applicable to a circuit having two voltage domains (the voltage domain corresponding to the main voltage source and the voltage domain corresponding to a secondary voltage source).

[0089] On the other hand, the structure of the power-on reset circuit of this embodiment can also be extended to applications having n secondary voltage sources, that is, the target circuit controlled by the power-on reset circuit has n + 1 voltage domains, where n is a positive integer greater than or equal to 2. As a general expression, VCCi represents the i-th secondary voltage source (i ∈ [1, n]). Then the main POR unit 1 includes the first resistor R1, the second resistor R2, the capacitor C, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the first inverter INV1, the second inverter INV2, and n switching NMOS transistors. The fourth MOS transistor M4 is a PMOS transistor, and the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fifth MOS transistor M5 are NMOS transistors.

[0090] One end of the first resistor R1, the drain of the first MOS transistor M1, and the source of the fourth MOS transistor M4 are electrically connected to the main voltage source VDD; the other end of the first resistor R1 and one end of the capacitor C are electrically connected to the gate of the first MOS transistor M1, and the other end of the capacitor C is grounded; the source of the first MOS transistor M1, one end of the second resistor R2, the gate of the second MOS transistor M2, and the gate of the third MOS transistor M3 are electrically connected, and the other end of the second resistor R2 is grounded; the drain of the fourth MOS transistor M4, the input end of the first inverter INV1, and the drain of the second MOS transistor M2 are electrically connected; the source of the second MOS transistor M2, the drain of the third MOS transistor M3, and the drain of the fifth MOS transistor M5 are electrically connected; the source of the third MOS transistor M3 is electrically connected to the drain of the first switching NMOS transistor; the source of the jth switching NMOS transistor is electrically connected to the drain of the (j + 1)th switching NMOS transistor, where j ∈ [1, n - 1], and the source of the nth switching NMOS transistor is grounded; the source of the fifth MOS transistor M5 is grounded, the gate of the fifth MOS transistor M5, and the output end of the first inverter INV1 are electrically connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 serves as the output end of the main POR unit 1; the gate of the ith switching NMOS transistor is electrically connected to the output end of the ith level conversion unit, where i ∈ [1, n].

[0091] Correspondingly, the POR module 2 includes n sub-POR units, and the level conversion module 3 includes n level conversion units. The power supply terminal of the ith sub-POR unit is correspondingly electrically connected to the ith sub-voltage source; the output end of the ith sub-POR unit is electrically connected to the input end of the ith level conversion unit; the output end of the ith level conversion unit is used to control the conduction or disconnection of the ith switching NMOS transistor, where i ∈ [1, n].

[0092] In specific implementation, the rated voltages of each sub-voltage source are not equal, and are all greater than the rated voltage of the main voltage source, that is, VCCi > VDD (i ∈ [1, n]).

[0093] After the chip is powered on, the power-on reset circuit of this embodiment starts to work. The ith sub-POR unit monitors the voltage of the ith sub-voltage source VCCi and outputs the POR signal porb_vcci of the corresponding voltage domain. Taking the first sub-POR unit 201 as an example, before the first sub-voltage source VCC1 rises to a reasonable stable voltage (i.e., the turn-on voltage) in this voltage domain, the first sub-POR unit 201 outputs porb_vcc1 as a low level; when the first sub-voltage source VCC1 rises to the turn-on voltage of this voltage domain, the first sub-POR unit 201 outputs porb_vcc1 as a high level. Similarly, the second sub-POR unit 202 monitors the voltage of the second sub-voltage source VCC2 and outputs the POR signal porb_vcc2 of the corresponding voltage domain.

[0094] The i-th level conversion unit plays the role of level conversion from the voltage domain corresponding to the auxiliary voltage source VCCi to the voltage domain corresponding to the main voltage source VDD. On the other hand, it plays the "AND" logic function on VCCi and VDD during the power-on process. Only when both VCCi and VDD reach a certain start-up voltage will the vcci_ok high-level signal of the VDD voltage domain be generated, which can be logically expressed as:

[0095] vcc1_ok=VCC1&VDD,vcc2_ok=VCC2&VDD。This formula is a logical expression, in which VCC1 represents that the first auxiliary voltage source VCC1 reaches the turn-on voltage of its corresponding voltage domain, VCC2 represents that the second auxiliary voltage source VCC2 reaches the turn-on voltage of its corresponding voltage domain, and VDD represents that the main voltage source VDD reaches the turn-on voltage of its corresponding voltage domain.

[0096] Taking the first level conversion unit 301 as an example, when porb_vcc1 is at a high level (ie, the first auxiliary voltage source VCC1 reaches the turn-on voltage corresponding to its voltage domain) and the main voltage source VDD reaches the turn-on voltage corresponding to its voltage domain, vcc1_ok is at a high level.

[0097] Reference Figure 9 , when the main voltage source VDD is stable, the output terminal por of the main POR unit 1 rises to a high level and resets the target circuit. When vcc1_ok and vcc2_ok are both high, the main POR unit 1 is enabled, the output terminal por changes from a high level to a low level, and the reset signal is released at the falling edge of the output terminal por, and the low level is maintained during t3, and the target circuit is in working state; otherwise, the output terminal por of the main POR unit 1 maintains a high level, and the circuit controlled by the power-on reset circuit is in a reset state. That is, V(vcc1_ok)>V dsn,M7 +V thn,M6 And V(vcc2_ok)>V thn,M7 When , the current flows through the transistor M2~M4 branch, thus forming the AND logic of vcc1_ok and vcc2_ok, and the following logical representation can be obtained:

[0098] vcc1_ok&vcc2_ok=(VCC1&VDD)&(VCC2&VDD)=VCC1&VCC2&VDD. This formula is a logical expression, in which VCC1 represents that the first auxiliary voltage source VCC1 reaches the turn-on voltage of its corresponding voltage domain, VCC2 represents that the second auxiliary voltage source VCC2 reaches the turn-on voltage of its corresponding voltage domain, and VDD represents that the main voltage source VDD reaches the turn-on voltage of its corresponding voltage domain.

[0099] Correspondingly, in the case of having n sub-voltage sources, only when the voltages of all n sub-voltage sources reach the turn-on voltages of their respective voltage domains, and the main voltage source VDD reaches the turn-on voltage of its voltage domain, the output terminal por of the main POR unit 1 outputs a low level to release the target circuit controlled by this power-on reset circuit.

[0100] It can be seen that the output terminal por of the main POR unit 1 outputs a high level regardless of the power-on sequence of the main voltage source and each sub-voltage source. Before the main voltage source and each sub-voltage source reach the turn-on voltages of their respective voltage domains, the output terminal por of the main POR unit 1 outputs a stable high level; after the main voltage source and each sub-voltage source reach the turn-on voltages of their respective voltage domains, the output terminal por of the main POR unit 1 generates a falling edge and then outputs a stable low level; as for the sequence of the main voltage source and each sub-voltage source reaching the turn-on voltages of their respective voltage domains, it does not affect the stability of the output of the output terminal por of the main POR unit 1.

[0101] Embodiment 2

[0102] This embodiment provides a power-on reset circuit. Refer to Figure 10 This power-on reset circuit includes a main POR unit 1, a POR module 2, and a level conversion module 3.

[0103] The POR module 2 includes three sub-POR units, namely a first sub-POR unit 201, a second sub-POR unit 202, and a third sub-POR unit 203. The first sub-POR unit 201 monitors the voltage of the first sub-voltage source VCC1. Before the first sub-voltage source VCC1 rises to the turn-on voltage in this voltage domain, the first sub-POR unit 201 outputs porb_vcc1 as a low level; when the first sub-voltage source VCC1 rises to the turn-on voltage in this voltage domain, the first sub-POR unit 201 outputs porb_vcc1 as a high level. Similarly, the second sub-POR unit 202 monitors the voltage of the second sub-voltage source VCC2 and outputs the POR signal porb_vcc2 corresponding to the voltage domain; the third sub-POR unit 203 monitors the voltage of the third sub-voltage source VCC3 and outputs the POR signal porb_vcc3 corresponding to the voltage domain.

[0104] As an optional implementation manner, refer to Figure 11, the level conversion module 3 includes three input PMOS transistors, three input NMOS transistors, a first NMOS transistor M21, a second NMOS transistor M23, a third NMOS transistor M24, and a first PMOS transistor M22. The three input PMOS transistors are respectively a first input PMOS transistor P1, a second input PMOS transistor P2, and a third input PMOS transistor P3; the three input NMOS transistors are respectively a first input NMOS transistor N1, a second input NMOS transistor N2, and a third input NMOS transistor N3.

[0105] The gate of the i-th input PMOS transistor serves as the i-th input terminal of the level conversion module 3 and is electrically connected to the gate of the i-th input NMOS transistor, where i ∈ [1, 3]. The sources of the three input PMOS transistors are all electrically connected to the main voltage source VDD, and the drains of the three input PMOS transistors are electrically connected and are all electrically connected to the drain of the first NMOS transistor M21, the gate of the first PMOS transistor M22, and the gate of the third NMOS transistor M24; the gates of the first NMOS transistor M21 and the second NMOS transistor M23 are electrically connected to the main voltage source, the source of the first NMOS transistor M21 is electrically connected to the drain of the first input NMOS transistor, the source of the i-th input NMOS transistor is electrically connected to the drain of the (i + 1)-th input NMOS transistor, and the source of the third input NMOS transistor (the third input NMOS transistor N3) is grounded; the source of the first PMOS transistor M22 is electrically connected to the main voltage source, and the drain of the first PMOS transistor M22 serves as the output terminal of the level conversion module 3 and is electrically connected to the drain of the second NMOS transistor M23; the source of the second NMOS transistor M23 is electrically connected to the drain of the third NMOS transistor M24, and the source of the third NMOS transistor M24 is grounded.

[0106] Based on Figure 11 For the level conversion module 3 shown, only one switching NMOS transistor, i.e., the sixth MOS transistor M6, needs to be correspondingly set in the main POR unit 1. The main POR unit 1 includes a first resistor R1, a second resistor R2, a capacitor C, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first inverter INV1, a second inverter INV2, and a switching NMOS transistor. The fourth MOS transistor M4 is a PMOS transistor, and the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fifth MOS transistor M5 are NMOS transistors.

[0107] One end of the first resistor R1, the drain of the first MOS transistor M1, and the source of the fourth MOS transistor M4 are electrically connected to the main voltage source; the other end of the first resistor R1 and one end of the capacitor C are electrically connected to the gate of the first MOS transistor M1, and the other end of the capacitor C is grounded; the source of the first MOS transistor M1, one end of the second resistor R2, the gate of the second MOS transistor M2, and the gate of the third MOS transistor M3 are electrically connected, and the other end of the second resistor R2 is grounded; the drain of the fourth MOS transistor M4, the input terminal of the first inverter INV1, and the drain of the second MOS transistor M2 are electrically connected; the source of the second MOS transistor M2, the drain of the third MOS transistor M3, and the drain of the fifth MOS transistor M5 are electrically connected; the source of the third MOS transistor M3 is electrically connected to the drain of the switch NMOS transistor; the source of the switch NMOS transistor is grounded; the source of the fifth MOS transistor M5 is grounded, the gate of the fifth MOS transistor M5, and the output terminal of the first inverter INV1 are electrically connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is used as the output terminal of the main POR unit 1; the gate of the switch NMOS transistor is electrically connected to the output terminal of the level conversion module 3.

[0108] When the voltages of the first secondary voltage source VCC1, the second secondary voltage source VCC2, and the third secondary voltage source VCC3 all reach the turn-on voltages of their respective voltage domains, prob_vcc1, prob_vcc2, and prob_vcc3 are all high levels; further, when the main voltage source VDD also reaches the turn-on voltage of its voltage domain, the output terminal vcc_ok of the level conversion module 3 is a high level. Then, the main POR unit 1 is enabled. Correspondingly, a falling edge is generated at the output terminal por of the main POR unit 1, and then a low level is output to release the target circuit and enable the target circuit to enter the working state. It can be seen that when the falling edge is generated at the output terminal por of the main POR unit 1 and then a low level is output, it is independent of the power-on sequence of the main voltage source and each secondary voltage source. Before the main voltage source and each secondary voltage source all reach the turn-on voltages of their respective voltage domains, the output terminal por of the main POR unit 1 outputs a stable high level; after the main voltage source and each secondary voltage source all reach the turn-on voltages of their respective voltage domains, a falling edge is generated at the output terminal por of the main POR unit 1, and then a stable low level is output; as for the sequence of the main voltage source and each secondary voltage source reaching the turn-on voltages of their respective voltage domains, it does not affect the stability of the output of the output terminal por of the main POR unit 1.

[0109] The structure of the power-on reset circuit in this embodiment can also be extended to applications with n auxiliary voltage sources. That is, the target circuit controlled by the power-on reset circuit has n + 1 voltage domains, where n is a positive integer greater than or equal to 2. As a general expression, VCCi represents the i-th auxiliary voltage source (i ∈ [1, n]). Then the level conversion module 3 includes n input PMOS transistors, n input NMOS transistors, a first NMOS transistor M21, a second NMOS transistor M23, a third NMOS transistor M24, and a first PMOS transistor M22. The gate of the i-th input PMOS transistor serves as the i-th input terminal of the level conversion module 3 and is electrically connected to the gate of the i-th input NMOS transistor, i ∈ [1, n]; the sources of the n input PMOS transistors are all electrically connected to the main voltage source, and the drains of the n input PMOS transistors are electrically connected to the drain of the first NMOS transistor M21, the gate of the first PMOS transistor M22, and the gate of the third NMOS transistor M24; the gates of the first NMOS transistor M21 and the second NMOS transistor M23 are electrically connected to the main voltage source VDD, the source of the first NMOS transistor M21 is electrically connected to the drain of the first input NMOS transistor, the source of the i-th input NMOS transistor is electrically connected to the drain of the (i + 1)-th input NMOS transistor, and the source of the n-th input NMOS transistor is grounded; the source of the first PMOS transistor M22 is electrically connected to the main voltage source, and the drain of the first PMOS transistor M22 serves as the output terminal of the level conversion module 3 and is electrically connected to the drain of the second NMOS transistor M23; the source of the second NMOS transistor M23 is electrically connected to the drain of the third NMOS transistor M24, and the source of the third NMOS transistor M24 is grounded.

[0110] For the voltage margin problem that may occur when the number of included voltage domains is large (i.e., n is large) or the rated voltage of the main voltage source VDD is low, the structure of the level conversion module 3 in the power-on reset circuit of this embodiment can better eliminate this voltage margin problem.

[0111] Although the specific implementation manners of the present invention have been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present invention is defined by the appended claims. Without departing from the principles and essence of the present invention, those skilled in the art can make various changes or modifications to these implementation manners, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. An on - power reset circuit, characterized in that, it includes a main POR unit, a POR module, and a level conversion module; The power supply terminal of the main POR unit is electrically connected to the main voltage source; The POR module includes at least one sub - POR unit, and the power supply terminal of the sub - POR unit is electrically connected to a sub - voltage source; The input end of the level conversion module is electrically connected to the output end of the sub - POR unit. The level conversion module is used to convert the signal at its input end to a signal in the voltage domain corresponding to the main voltage source and output it at its output end; When the output signal of the sub - POR unit is in the first state, the output end of the level conversion module is used to enable the main POR unit; When the output signal of the sub - POR unit is in the second state, the output end of the level conversion module is used to disable the main POR unit; The output end of the main POR unit serves as the output end of the on - power reset circuit; The sub - POR unit includes an eleventh resistor, a twelfth resistor, a first capacitor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, an eleventh inverter, and a twelfth inverter; the fourteenth MOS transistor M14 is a PMOS transistor, and the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the fifteenth MOS transistor are NMOS transistors; One end of the eleventh resistor, the drain of the eleventh MOS transistor, and the source of the fourteenth MOS transistor are electrically connected to the sub - voltage source; The gate of the fourteenth MOS transistor is grounded; the other end of the eleventh resistor and one end of the first capacitor are electrically connected to the gate of the eleventh MOS transistor, and the other end of the first capacitor is grounded; the source of the eleventh MOS transistor, one end of the twelfth resistor, and the gates of the twelfth MOS transistor and the thirteenth MOS transistor are electrically connected, and the other end of the twelfth resistor is grounded; the drain of the fourteenth MOS transistor and the input end of the eleventh inverter are electrically connected to the drain of the twelfth MOS transistor; the source of the twelfth MOS transistor, the drain of the thirteenth MOS transistor, and the drain of the fifteenth MOS transistor are electrically connected; the source of the thirteenth MOS transistor and the source of the fifteenth MOS transistor are grounded, the gate of the fifteenth MOS transistor, the output end of the eleventh inverter, and the input end of the twelfth inverter are electrically connected, the output end of the twelfth inverter is electrically connected to the input end of the thirteenth inverter, and the output end of the thirteenth inverter serves as the output end of the sub - POR unit.

2. The on - power reset circuit according to claim 1, characterized in that, The main POR unit includes a switch module, and the output end of the level conversion module is used to control the conduction or disconnection of the switch module to enable or disable the main POR unit.

3. The on - power reset circuit according to claim 2, characterized in that, The POR module includes n of the sub-POR units, the level conversion module includes n level conversion units, the switch module includes n switch units, and the n switch units are connected in series; The power supply terminal of the i-th sub-POR unit is electrically connected to the i-th sub-voltage source correspondingly; The output terminal of the i-th sub-POR unit is electrically connected to the input terminal of the i-th level conversion unit; The output terminal of the i-th level conversion unit is used to control the conduction or disconnection of the i-th switch unit; i ∈ [1, n], where n is a positive integer greater than or equal to 2; The voltages of any two of the sub-voltage sources are not equal.

4. The power-on reset circuit according to claim 3, characterized in that, The level conversion unit includes a first conversion PMOS transistor, a second conversion PMOS transistor, a first conversion NMOS transistor, a second conversion NMOS transistor, a third conversion NMOS transistor, and a fourth conversion NMOS transistor; The source electrodes of the first conversion PMOS transistor and the second conversion PMOS transistor are electrically connected to the main voltage source. The gate electrode of the first conversion PMOS transistor serves as the input terminal of the level conversion unit and is electrically connected to the gate electrode of the second conversion NMOS transistor. The drain electrode of the first conversion PMOS transistor is electrically connected to the drain electrode of the first conversion NMOS transistor, the gate electrode of the second conversion PMOS transistor, and the gate electrode of the fourth conversion NMOS transistor; The source electrode of the first conversion NMOS transistor is electrically connected to the drain electrode of the second conversion NMOS transistor. The gate electrodes of the first conversion NMOS transistor and the third conversion NMOS transistor are electrically connected to the main voltage source, and the source electrode of the second conversion NMOS transistor is grounded; The drain electrode of the second conversion PMOS transistor serves as the output terminal of the level conversion unit and is electrically connected to the drain electrode of the third conversion NMOS transistor. The source electrode of the third conversion NMOS transistor is electrically connected to the drain electrode of the fourth conversion NMOS transistor, and the source electrode of the fourth conversion NMOS transistor is grounded.

5. The power-on reset circuit according to claim 4, characterized in that, The first conversion PMOS transistor, the first conversion NMOS transistor, and the second conversion NMOS transistor are thick-gate transistors.

6. The power-on reset circuit according to claim 3, characterized in that, The switch unit includes a switch NMOS transistor; The main POR unit includes a first resistor, a second resistor, a capacitor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first inverter, and a second inverter; the fourth MOS transistor is a PMOS transistor, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fifth MOS transistor are NMOS transistors; One end of the first resistor, the drain electrode of the first MOS transistor, and the source electrode of the fourth MOS transistor are electrically connected to the main voltage source; The other end of the first resistor and one end of the capacitor are electrically connected to the gate electrode of the first MOS transistor, and the other end of the capacitor is grounded; The source of the first MOS transistor, one end of the second resistor, the gate of the second MOS transistor, and the gate of the third MOS transistor are electrically connected, and the other end of the second resistor is grounded; The drain of the fourth MOS transistor, the input terminal of the first inverter, and the drain of the second MOS transistor are electrically connected; The source of the second MOS transistor, the drain of the third MOS transistor, and the drain of the fifth MOS transistor are electrically connected; The source of the third MOS transistor is electrically connected to the drain of the first switching NMOS transistor; The source of the j-th switching NMOS transistor is electrically connected to the drain of the (j + 1)-th switching NMOS transistor, j ∈ [1, n - 1], and the source of the n-th switching NMOS transistor is grounded; The source of the fifth MOS transistor is grounded, the gate of the fifth MOS transistor, the output terminal of the first inverter, and the input terminal of the second inverter are electrically connected, and the output terminal of the second inverter serves as the output terminal of the main POR unit; The gate of the i-th switching NMOS transistor is electrically connected to the output terminal of the i-th level conversion unit, i ∈ [1, n].

7. The power-on reset circuit according to claim 2, characterized in that the POR module includes n sub-POR units, and the level conversion module includes n input terminals and one output terminal; the output terminal of the i-th sub-POR unit is electrically connected to the i-th input terminal of the level conversion module; i ∈ [1, n], and n is a positive integer greater than or equal to 2; the voltages of any two sub-voltage sources are not equal.

8. The power-on reset circuit according to claim 7, characterized in that the level conversion module includes n input PMOS transistors, n input NMOS transistors, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first PMOS transistor; the gate of the i-th input PMOS transistor serves as the i-th input terminal of the level conversion module and is electrically connected to the gate of the i-th input NMOS transistor, i ∈ [1, n]; the sources of the n input PMOS transistors are all electrically connected to the main voltage source, and the drains of the n input PMOS transistors are electrically connected to the drain of the first NMOS transistor, the gate of the first PMOS transistor, and the gate of the third NMOS transistor; the gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically connected to the main voltage source, the source of the first NMOS transistor is electrically connected to the drain of the first input NMOS transistor, the source of the i-th input NMOS transistor is electrically connected to the drain of the (i + 1)-th input NMOS transistor, and the source of the n-th input NMOS transistor is grounded; the source of the first PMOS transistor is electrically connected to the main voltage source, and the drain of the first PMOS transistor serves as the output terminal of the level conversion module and is electrically connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded.

9. The power-on reset circuit according to claim 7, characterized in that The switch module includes a switching NMOS transistor; The main POR unit includes a first resistor, a second resistor, a capacitor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first inverter, and a second inverter; the fourth MOS transistor is a PMOS transistor, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fifth MOS transistor are NMOS transistors; One end of the first resistor, the drain of the first MOS transistor, and the source of the fourth MOS transistor are electrically connected to the main voltage source; The other end of the first resistor and one end of the capacitor are electrically connected to the gate of the first MOS transistor, and the other end of the capacitor is grounded; The source of the first MOS transistor, one end of the second resistor, the gate of the second MOS transistor, and the gate of the third MOS transistor are electrically connected, and the other end of the second resistor is grounded; The drain of the fourth MOS transistor, the input end of the first inverter, and the drain of the second MOS transistor are electrically connected; The source of the second MOS transistor, the drain of the third MOS transistor, and the drain of the fifth MOS transistor are electrically connected; The source of the third MOS transistor is electrically connected to the drain of the switching NMOS transistor; The source of the switching NMOS transistor is grounded; The source of the fifth MOS transistor is grounded, the gate of the fifth MOS transistor, the output end of the first inverter, and the input end of the second inverter are electrically connected, and the output end of the second inverter serves as the output end of the main POR unit; The gate of the switching NMOS transistor is electrically connected to the output end of the level conversion module.

10. The power-on reset circuit according to any one of claims 1-9, characterized in that the voltage of the main voltage source is less than the voltage of the secondary voltage source.

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