RRU testing method, device and medium

Abstract

The embodiment of the present invention provides an RRU test method, device and medium, which relate to the field of communication technology. The method includes: inputting uplink simulation data of at least one channel into the path processing module of the radio remote unit RRU, and ping-pong caching the uplink data output by the uplink channel packet processing module of the RRU. Then, the uplink data of the channel to be tested is extracted from the uplink data of the ping-pong cache, and the uplink data of the channel to be tested is cached in a random access memory RAM; the uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested, and determines whether there is a fault in the channel to be tested. The development and maintenance efficiency of RRU can be improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an RRU testing method, device and medium. Background Art

[0002] The distributed base station architecture includes a remote radio unit (RRU) and a baseband unit (BBU), and the RRU and BBU are connected by optical fiber. The uplink transmission process of the RRU is as follows: the RRU receives the time domain data from the terminal through the air interface, converts the time domain data into frequency domain data, and transmits the frequency domain data to the BBU through the optical fiber. The downlink transmission process of the RRU is as follows: the RRU receives the frequency domain data transmitted by the BBU through the optical fiber, converts the frequency domain data into time domain data, and sends the time domain data to the terminal through the air interface.

[0003] In a time division duplex (TDD) wireless system, the RRU includes multiple signal transmission channels. Currently, during the development and maintenance of the RRU, it is impossible to verify whether the data output by each signal transmission channel is correct. If a fault is found in the RRU when it is actually used, it is necessary to manually troubleshoot the faulty RRU, resulting in low efficiency in the development and maintenance of the RRU. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide an RRU testing method, device and medium to solve the problem of low efficiency in the development and maintenance of RRU. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides an RRU testing method, including:

[0006] Inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU;

[0007] Performing ping-pong buffering on the uplink data output by the uplink channel packet processing module of the RRU;

[0008] Extracting the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffering the uplink data of the channel to be tested in a random access memory RAM;

[0009] The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

[0010] In a possible implementation, extracting the uplink data of the channel to be tested from the uplink data in the ping-pong buffer and buffering the uplink data of the channel to be tested in a random access memory RAM includes:

[0011] Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence;

[0012] If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, starting from the matching uplink data packet, the uplink data packets in the ping-pong buffer are extracted, and the extracted uplink data packets are written into the RAM at the clock frequency of the RRU;

[0013] The method of transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes:

[0014] The uplink data of the channel to be tested buffered in the RAM is transmitted to the DDR at the clock frequency of the PCIE interface.

[0015] In a possible implementation, starting from the matched uplink data packet, extracting the uplink data packet in the ping-pong buffer, and writing the extracted uplink data packet into the RAM at the clock frequency of the RRU includes:

[0016] Transmitting the header of the matched uplink data packet to the RAM;

[0017] Extracting the data of the matched uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0018] After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM;

[0019] Extracting the data of the next uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0020] Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, and extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

[0021] In a possible implementation, the transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes:

[0022] Aligning the uplink data of the channel to be tested cached in the RAM with the control information pre-cached in the FIFO module, and transmitting the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module to the DDR through the PCIE interface, wherein the control information includes a preset total data length and a preset first address;

[0023] Starting from the preset first address, the uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches the preset total data length.

[0024] In a second aspect, an embodiment of the present application provides an RRU testing device, including a memory, a transceiver, and a processor:

[0025] A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations:

[0026] Inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU;

[0027] Performing ping-pong buffering on the uplink data output by the uplink channel packet processing module of the RRU;

[0028] Extracting the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffering the uplink data of the channel to be tested in a random access memory RAM;

[0029] The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

[0030] In a possible implementation manner, the processor is specifically configured to read the computer program in the memory and perform the following operations:

[0031] Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence;

[0032] If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, starting from the matching uplink data packet, the uplink data packets in the ping-pong buffer are extracted, and the extracted uplink data packets are written into the RAM at the clock frequency of the RRU;

[0033] The method of transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes:

[0034] The uplink data of the channel to be tested buffered in the RAM is transmitted to the DDR at the clock frequency of the PCIE interface.

[0035] In a possible implementation manner, the processor is specifically configured to read the computer program in the memory and perform the following operations:

[0036] Transmitting the header of the matched uplink data packet to the RAM;

[0037] Extracting the data of the matched uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0038] After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM;

[0039] Extracting the data of the next uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0040] Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, and extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

[0041] In a possible implementation manner, the processor is specifically configured to read the computer program in the memory and perform the following operations:

[0042] Aligning the uplink data of the channel to be tested cached in the RAM with the control information pre-cached in the FIFO module, and transmitting the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module to the DDR through the PCIE interface, wherein the control information includes a preset total data length and a preset first address;

[0043] Starting from the preset first address, the uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches the preset total data length.

[0044] In a third aspect, an embodiment of the present application provides an RRU testing device, including:

[0045] An input unit, used for inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU;

[0046] A cache unit, used for ping-pong caching of uplink data output by the uplink channel packet processing module of the RRU;

[0047] An extraction unit, used for extracting the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffering the uplink data of the channel to be tested in a random access memory RAM;

[0048] The transmission unit is used to transmit the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and transmit the uplink data of the channel to be tested cached in the DDR to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

[0049] In a fourth aspect, an embodiment of the present application provides a processor-readable storage medium, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the method described in the first aspect above.

[0050] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0051] By adopting the above technical solution, the simulation data of at least one channel can be input into the RRU, and the uplink data output by the uplink channel packet processing module of the RRU can be ping-pong cached, ensuring that the uplink data output by the uplink packet processing module are all collected, avoiding data loss. Then, the uplink data of the channel to be tested can be extracted from the uplink data of the ping-pong cache and cached in the RAM, and then the uplink data of the channel to be tested cached in the RAM is transmitted to the DDR through the PCIE interface, so that the uplink data of the channel to be tested can be extracted through the PCIE interface, so that the test equipment can obtain the uplink data of the channel to be tested cached in the DDR to determine whether there is a fault in the channel to be tested. It can be seen that through the embodiment of the present application, the uplink data output by the channel to be tested after the transmission of the uplink simulation data can be flexibly extracted, so that each channel in the RRU can be tested during the development stage, which can improve the development and maintenance efficiency.

[0052] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of an uplink transmission architecture of an RRU provided in an embodiment of the present application;

[0055] Figure 2 A flowchart of an RRU testing method provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the structure of a PCIE data extraction module provided in an embodiment of the present application;

[0057] Figure 4 A schematic diagram of a data processing state machine provided in an embodiment of the present application;

[0058] Figure 5 A schematic diagram of the structure of an RRU test device provided in an embodiment of the present application;

[0059] Figure 6 A schematic diagram of the structure of another RRU testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0061] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] The technical solution provided in the embodiment of the present application can be applicable to a variety of systems, especially 5G systems. For example, the applicable system can be a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) general packet radio service (GPRS) system, a long term evolution (LTE) system, a LTE frequency division duplex (FDD) system, a LTE time division duplex (TDD) system, an advanced long term evolution (LTE-A) system, a universal mobile telecommunication system (UMTS), a world-wide interoperability for microwave access (WiMAX) system, a 5G new air interface (NR) system, etc. These various systems include terminal equipment and network equipment. The system may also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0064] For ease of understanding, the transmission process of RRU is first introduced. The uplink transmission of RRU data refers to the RRU receiving time domain data from the terminal through the air interface, converting the time domain data into frequency domain data, and transmitting the frequency domain data to the BBU through the optical fiber. The downlink transmission of RRU refers to the RRU receiving frequency domain data from the BBU through the optical fiber, converting the frequency domain data into time domain data, and sending the time domain data to the terminal through the air interface.

[0065] Taking the uplink transmission process of RRU as an example, the uplink transmission architecture of RRU is as follows: Figure 1 As shown, the RRU is connected to the BBU, and the RRU includes an electrical port, a path processing module, an uplink front-end processing module, a physical random access channel (PRACH), a physical uplink shared channel (PUSCH), a physical uplink control channel (PUCCH), a sounding reference signal (SRS) channel, a frequency domain data compression processing module, an uplink channel packet processing module, and an optical port transmission module. Figure 1 The PRACH channel, PUSCH channel, PUCCH channel, and SRS channel are exemplarily shown in FIG. 1 , but in fact, the uplink transmission channels in the RRU are not limited thereto.

[0066] Combination Figure 1 , the uplink transmission process of RRU specifically includes: the path processing module of RRU receives the uplink time domain data from the terminal through the electrical port, the path processing module twists the received uplink time domain data, and then transmits the uplink time domain data to the uplink front-end processing module and PRACH channel in sequence. The uplink front-end processing module performs time-frequency conversion on the uplink time domain data, separates the uplink frequency domain data of each channel, and transmits the uplink frequency domain data of each channel to each channel respectively. The PRACH channel can convert the received uplink time domain data into uplink frequency domain data, and separate the uplink frequency domain data to be transmitted by PRACH for transmission. After that, each channel transmits the uplink frequency domain data to the frequency domain data compression processing module, which is compressed by the frequency domain data compression processing module and then transmitted to the uplink channel packetization processing module. The uplink channel packetization processing module respectively packages the data from each channel and transmits them to the BBU through the optical port one by one.

[0067] In an embodiment of the present application, in order to solve the problem of low development and maintenance efficiency of RRU, uplink simulation data can be injected into the path processing module through the test equipment, and the uplink data output by the uplink channel packetization processing module can be extracted, and the uplink data output by the uplink channel packetization processing module can be transmitted to the test equipment, so that the test equipment verifies the accuracy of the uplink data output by the uplink channel packetization module, thereby determining whether there is a problem with the signal transmission channel in the RRU. It can be flexibly verified whether each signal transmission channel has defects during the development stage, which can improve the development and maintenance efficiency of the RRU.

[0068] The following is a detailed introduction to the RRU testing method provided in the embodiment of the present application.

[0069] like Figure 2 As shown, an embodiment of the present application provides an RRU testing method, which is applied to an RRU device, and can be specifically applied to a field programmable gate array (FPGA) or an ARM processor in the RRU device. The method includes:

[0070] S201. Input uplink simulation data of at least one channel into a path processing module of an RRU.

[0071] It is understandable that in the embodiment of the present application, the RRU can be tested before the RRU is actually deployed, so the test equipment can be connected to the RRU device, and the test equipment can generate the uplink simulation vector of each channel and the simulation output vector corresponding to the uplink simulation vector through MATLAB software. In the embodiment of the present application, the uplink simulation vector is referred to as uplink simulation data, and the simulation output vector is referred to as simulation output data.

[0072] Then, when the channel to be tested needs to be tested, the uplink simulation data of the channel to be tested is transmitted to the RRU device through the operation and maintenance software (e.g., OSP studio, referred to as OSP) in the test equipment. Then, the processing chip in the RRU device, such as FPGA or ARM, inputs the uplink simulation data of the channel to be tested into the path processing module of the RRU, and then the RRU will perform uplink transmission of the uplink simulation data.

[0073] Among them, the test equipment in the embodiment of the present application can be a terminal device such as a computer installed with OSP software and MATLAB software.

[0074] S202: Ping-pong buffering is performed on the uplink data output by the uplink channel packet processing module of the RRU.

[0075] Since the clock frequency of the RRU is relatively high, in order to prevent data loss, the uplink data output by the uplink packet processing module of the RRU may be firstly ping-pong cached.

[0076] S203: extract the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffer the uplink data of the channel to be tested in a random access memory (Random Access Memory, RAM).

[0077] Among them, RAM is also called main memory, which is a temporary data storage medium. In the embodiment of the present application, the uplink data of the channel to be tested can be temporarily cached in RAM, and the format of the uplink data of the channel to be tested can be converted into the format corresponding to the PCIE interface through RAM.

[0078] S204. The uplink data of the channel to be tested cached in the RAM is transmitted to the DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether there is a fault in the channel to be tested.

[0079] DDR is the abbreviation of Double Data Rate Synchronous Dynamic Random Access Memory.

[0080] Since the RAM cache space is limited, the RAM is only used as a temporary cache. After the data stream completes the format conversion and clock domain conversion in the RAM, it is transmitted to the DDR through the PCIE interface. In other words, the DDR can cache all the uplink data of the channel to be tested that needs to be tested this time.

[0081] When testing is required, the uplink data of the channel to be tested cached in the DDR can be obtained through the OSP of the test equipment. Then the test equipment can compare the obtained uplink data of the channel to be tested with the simulation data of the channel to be tested. If the obtained uplink data of the channel to be tested is consistent with the simulation data, it is determined that there is no fault in the channel to be tested; if the obtained uplink data of the test channel is inconsistent with the simulation data, it is determined that there is a fault in the channel to be tested. By analyzing the obtained uplink data of the channel to be tested, the cause of the fault of the channel to be tested can be quickly located, so as to facilitate maintenance of the channel to be tested.

[0082] By adopting the above technical solution, the simulation data of at least one channel can be input into the RRU, and the uplink data output by the uplink channel packet processing module of the RRU can be ping-pong cached, ensuring that the uplink data output by the uplink packet processing module are all collected, avoiding data loss. Then, the uplink data of the channel to be tested can be extracted from the uplink data of the ping-pong cache and cached in the RAM, and then the uplink data of the channel to be tested cached in the RAM is transmitted to the DDR through the PCIE interface, so that the uplink data of the channel to be tested can be extracted through the PCIE interface, so that the test equipment can obtain the uplink data of the channel to be tested cached in the DDR to determine whether there is a fault in the channel to be tested. It can be seen that through the embodiment of the present application, the uplink data output by the channel to be tested after the transmission of the uplink simulation data can be flexibly extracted, so that each channel in the RRU can be tested during the development stage, which can improve the development and maintenance efficiency.

[0083] In the embodiment of the present application, the conversion of the clock frequency can be achieved by temporarily caching the uplink data of the channel to be tested in the RAM. The above S203, extracting the uplink data of the channel to be tested from the uplink data of the ping-pong buffer, and caching the uplink data of the channel to be tested in the RAM, can be implemented as follows:

[0084] Each uplink data packet in the ping-pong cache is matched with the packet header of the channel to be tested in turn. If there is an uplink data packet in the ping-pong cache that matches the packet header of the channel to be tested, starting from the matching uplink data packet, the uplink data packets in the ping-pong cache are extracted, and the extracted uplink data packets are written into the RAM at the clock frequency of the RRU.

[0085] Among them, the process of data extraction in the embodiment of the present application can be implemented by the PCIE data extraction module in the RRU device, such as Figure 3 As shown, the PCIE data extraction module includes a ping-pong cache module, a data selection module and a data format conversion module. Among them, the data format conversion module includes a data format conversion submodule RAM and a control information cache submodule: a first-in first-out (First Input First Output, FIFO) queue. The data format conversion module can realize the conversion from the business clock domain to the PCIE clock domain.

[0086] Among them, the tester can write the packet header and data valid signal of the channel to be tested to the register of the RRU device through the OSP software of the test equipment. Then, when the ping-pong cache module ping-pong caches the uplink data output by the uplink channel packet processing module, if the data selection module recognizes the data valid signal of the register, each uplink data packet cached in the ping-pong cache module is matched with the packet header of the channel to be tested in the register. If there is a matching uplink data packet, the data selection module triggers the data processing state machine to extract the uplink data packet in the ping-pong cache module starting from the matching uplink data packet, and caches the extracted uplink data packet in the data format conversion submodule RAM with the service processing clock (491.52MHz) of the RRU.

[0087] In addition, the tester can also write control information to the control information cache submodule FIFO through the OSP software. The control information includes the preset total data length and the preset first address. While the PCIE data extraction module extracts data, it aligns the cached data in the RAM with the control information cached in the FIFO and transmits it to the DDR through the PCIE interface.

[0088] Optionally, the PCIE data extraction module can be implemented through the FPGA in the RRU device, making full use of the logic characteristics of the FPGA, occupying fewer FPGA logic units and having a higher resource utilization rate.

[0089] In the embodiment of the present application, the data processing state machine is as follows: Figure 4 As shown, the data processing state machine includes four states: CHIP_IDLE, CHIP_INFO, CHIP_READ, and CHIP_OVER.

[0090] Among them, CHIP_IDLE is an idle state, and the data processing state machine is in an idle state when it is not working.

[0091] CHIP_INFO is the status of the transmission data packet header.

[0092] CHIP_READ is the data reading status.

[0093] CHIP_OVER indicates the data transmission completion status.

[0094] Among them, in the CHIP_IDLE state, it will detect in real time whether the PCIE data switch is turned on. If the data selection module determines that there is an uplink data packet in the uplink data packet of the ping-pong cache that matches the packet header of the channel to be tested, the PCIE data switch is turned on, and then the data processing state machine switches to the CHIP_INFO state.

[0095] Combination Figure 4, starting from the matched uplink data packet, extracting the uplink data packet in the ping-pong buffer, and writing the extracted uplink data packet into the RAM at the clock frequency of the RRU, including the following steps:

[0096] Step 1: Transfer the header of the matching uplink data packet to the RAM.

[0097] In the CHIP_INFO state of the data processing state machine, step 1 may be executed. After the packet header of the matched uplink data packet is transmitted, the data processing state machine switches to the CHIP_READ state and executes step 2.

[0098] Step 2: extract the data of the matched uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transfer the extracted data to the RAM.

[0099] In the process of uplink data transmission, each group of data is transmitted through a fixed-length chip. A chip can include 96 data bits, and a data packet includes 90 data bits or 64 data bits. The unoccupied data bits in the chip can be filled with 0.

[0100] The data start bit and data end bit of each uplink data packet of each channel in the code piece are fixed. Taking each uplink data packet including 64 data as an example, the 64 data included in the uplink data packet can be extracted from the code piece according to the data start bit and data end bit.

[0101] The data processing state machine is in the CHIP_READ state. Each time a data is read, it determines whether the data end bit has been read. If the data end bit has not been read, the CHIP_READ state is maintained. If the data end bit is read, after waiting for a specified time and completing the transmission of the remaining part of the code chip, it switches to the CHIP_INFO state and transmits the header of the next uplink data packet.

[0102] Step 3: After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transferred to the RAM.

[0103] After the packet header of the next uplink data packet is transmitted, the data processing state machine switches to the CHIP_READ state again and executes step 4.

[0104] Step 4: extract the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transfer the extracted data to the RAM.

[0105] Then, after waiting for a specified time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM, and the data of the next uplink data packet is extracted according to the data start bit and data end bit corresponding to the channel to be tested, and the extracted data is transmitted to the RAM, that is, the above steps 3 and 4 are repeatedly executed until all the uplink data packets of the channel to be tested in the ping-pong buffer are transmitted to the RAM. Then, the data processing state machine switches back to the CHIP_IDLE state, waiting for the next data extraction.

[0106] Through the above process, after the uplink data packet of the channel to be tested is written into the RAM at the clock frequency of the RRU, in order to realize the conversion of the clock domain, correspondingly, the above S204, transferring the uplink data of the channel to be tested cached in the RAM to the DDR through the PCIE interface, can be implemented as follows:

[0107] The uplink data of the channel to be tested buffered in the RAM is transferred to the DDR at the clock frequency of the PCIE interface, wherein the clock frequency of the PCIE interface may be 250 MHz.

[0108] By using the embodiment of the present application, by matching the packet header of the data packet, the uplink data of the channel to be tested can be extracted from the ping-pong buffer, and then the uplink data of the channel to be tested is cached by the RAM, so that the clock frequency conversion can be realized. After the uplink data is converted to a lower clock frequency, it is transmitted to the test equipment for processing, which can avoid data loss caused by the inconsistency between the service clock frequency and the clock frequency of the PCIE interface, so that the uplink data of the data to be tested is completely transmitted to the test equipment.

[0109] In another embodiment of the present application, the above S204, transmitting the uplink data of the channel to be tested cached in the RAM to the DDR through the PCIE interface, can be specifically implemented as follows:

[0110] The uplink data of the channel to be tested cached in the RAM is aligned with the control information pre-cached in the FIFO module, and the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module are transmitted to the DDR through the PCIE interface, where the control information includes a preset total data length and a preset first address.

[0111] Starting from a preset first address, uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches a preset total data length.

[0112] Among them, the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module will be transmitted to the DDR at the same time. The DDR's transceiver engine can cache the received uplink data in the DDR starting from the preset first address based on the preset first address included in the control information until the cached uplink data reaches the preset total length.

[0113] When it is necessary to test the uplink data of the channel to be tested, the test equipment may obtain the uplink data of the channel to be tested buffered in the DDR.

[0114] In one implementation, the test equipment can also import the acquired uplink data of the channel to be tested into MATLAB for algorithm analysis, so as to quickly determine whether there is a fault in the channel to be tested and the cause of the fault, thereby reducing the difficulty of subsequent maintenance of the RRU.

[0115] Based on the same technical concept, the embodiment of the present application also provides an RRU testing device, such as Figure 5 As shown, the device includes a memory 520, a transceiver 510, and a processor 500:

[0116] The memory 520 is used to store computer programs; the transceiver 510 is used to send and receive data under the control of the processor 500; the processor 500 is used to read the computer program in the memory 520 and perform the following operations:

[0117] Inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU;

[0118] Ping-pong buffering is performed on the uplink data output by the uplink channel packet processing module of the RRU;

[0119] Extracting the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffering the uplink data of the channel to be tested in a random access memory RAM;

[0120] The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether there is a fault in the channel to be tested.

[0121] The processor 500 is specifically configured to read the computer program in the memory 520 and perform the following operations:

[0122] Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence;

[0123] If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, then starting from the matching uplink data packet, the uplink data packet in the ping-pong buffer is extracted, and the extracted uplink data packet is written into the RAM at the clock frequency of the RRU;

[0124] The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, including:

[0125] The uplink data of the channel to be tested buffered in the RAM is transmitted to the DDR at the clock frequency of the PCIE interface.

[0126] In one implementation, the processor 500 is specifically configured to read the computer program in the memory 520 and perform the following operations:

[0127] Transferring the header of the matched uplink data packet to the RAM;

[0128] According to the data start bit and data end bit corresponding to the channel to be tested, the data of the matched uplink data packet is extracted, and the extracted data is transferred to the RAM;

[0129] After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transferred to the RAM;

[0130] According to the data start bit and data end bit corresponding to the channel to be tested, the data of the next uplink data packet is extracted, and the extracted data is transferred to the RAM;

[0131] Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

[0132] In one implementation, the processor 500 is specifically configured to read the computer program in the memory 520 and perform the following operations:

[0133] Align the uplink data of the channel to be tested cached in the RAM with the control information pre-cached in the FIFO module, and transmit the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module to the DDR through the PCIE interface, wherein the control information includes a preset total data length and a preset first address;

[0134] Starting from the preset first address, the uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches the preset total data length.

[0135] The transceiver 510 is configured to receive and send data under the control of the processor 500 .

[0136] Among them, Figure 5 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 500 and memory represented by memory 520. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 510 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which transmission medium may include a wireless channel, a wired channel, an optical cable, and the like. The processor 500 is responsible for managing the bus architecture and general processing, and the memory 520 may store data used by the processor 500 when performing operations.

[0137] The processor 500 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processor may also adopt a multi-core architecture.

[0138] It should be noted here that the above-mentioned device provided in the embodiment of the present invention can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be described in detail here.

[0139] Based on the same technical concept, the embodiment of the present application also provides an RRU testing device, such as Figure 6 As shown, the device comprises:

[0140] An input unit 601 is used to input uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU;

[0141] The cache unit 602 is used to perform ping-pong cache on the uplink data output by the uplink channel packet processing module of the RRU;

[0142] The extraction unit 603 is used to extract the uplink data of the channel to be tested from the uplink data in the ping-pong buffer, and buffer the uplink data of the channel to be tested in a random access memory RAM;

[0143] The transmission unit 604 is used to transmit the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and transmit the uplink data of the channel to be tested cached in the DDR to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

[0144] In one implementation, the extraction unit 603 is specifically configured to:

[0145] Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence;

[0146] If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, then starting from the matching uplink data packet, the uplink data packets in the ping-pong buffer are extracted.

[0147] The extracted uplink data packet is written into the RAM at the clock frequency of the RRU.

[0148] The transmission unit 604 is specifically configured to transmit the uplink data of the channel to be tested buffered in the RAM to the DDR at the clock frequency of the PCIE interface.

[0149] In one implementation, the extraction unit 603 is specifically configured to:

[0150] Transmitting the header of the matched uplink data packet to the RAM;

[0151] Extracting the data of the matched uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0152] After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM;

[0153] Extracting the data of the next uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM;

[0154] Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, and extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

[0155] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0156] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0157] In another embodiment of the present invention, a processor-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above RRU testing methods are implemented.

[0158] The processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0159] In another embodiment of the present invention, a computer program product including instructions is provided. When the computer program product is run on a computer, the computer executes any one of the RRU testing methods in the above embodiments.

[0160] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0161] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer executable instructions. These computer executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0162] These processor executable instructions may also be stored in a processor readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0163] These processor-executable instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0164] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A RRU testing method, characterized in that: include: Inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU; Performing ping-pong buffering on the uplink data output by the uplink channel packet processing module of the RRU; Extracting uplink data of the channel to be tested from the uplink data in the ping-pong buffer, buffering the uplink data of the channel to be tested in a random access memory RAM, converting the format of the uplink data of the channel to be tested into a format corresponding to the PCIE interface through the RAM, and converting the uplink data of the channel to be tested from the service clock domain to the PCIE clock domain; The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

2. The method according to claim 1, characterized in that The uplink data of the channel to be tested is extracted from the uplink data of the ping-pong buffer, the uplink data of the channel to be tested is buffered in a random access memory RAM, the format of the uplink data of the channel to be tested is converted into a format corresponding to the PCIE interface through the RAM, and the uplink data of the channel to be tested is converted from the service clock domain to the PCIE clock domain, including: Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence; If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, starting from the matching uplink data packet, the uplink data packet in the ping-pong buffer is extracted, and the extracted uplink data packet is written into the RAM at the clock frequency of the RRU, and the format of the uplink data of the channel to be tested is converted into the format corresponding to the PCIE interface through the RAM, and the uplink data of the channel to be tested is converted from the service clock domain to the PCIE clock domain; The method of transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes: The uplink data of the channel to be tested buffered in the RAM is transmitted to the DDR at the clock frequency of the PCIE interface.

3. The method according to claim 2, characterized in that The method of extracting uplink data packets from the ping-pong buffer starting from the matched uplink data packets and writing the extracted uplink data packets into the RAM at the clock frequency of the RRU includes: Transmitting the header of the matched uplink data packet to the RAM; Extracting the data of the matched uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM; After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM; Extracting the data of the next uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM; Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, and extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

4. The method according to claim 1, characterized in that: The method of transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes: Aligning the uplink data of the channel to be tested cached in the RAM with the control information pre-cached in the FIFO module, and transmitting the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module to the DDR through the PCIE interface, wherein the control information includes a preset total data length and a preset first address; Starting from the preset first address, the uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches the preset total data length.

5. An RRU testing device, characterized in that: Including memory, transceiver, processor: A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations: Inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU; Performing ping-pong buffering on the uplink data output by the uplink channel packet processing module of the RRU; Extracting uplink data of the channel to be tested from the uplink data in the ping-pong buffer, buffering the uplink data of the channel to be tested in a random access memory RAM, converting the format of the uplink data of the channel to be tested into a format corresponding to the PCIE interface through the RAM, and converting the uplink data of the channel to be tested from the service clock domain to the PCIE clock domain; The uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

6. The device according to claim 5, characterized in that The processor is specifically configured to read the computer program in the memory and perform the following operations: Matching each uplink data packet in the ping-pong buffer with the packet header of the channel to be tested in sequence; If there is an uplink data packet matching the packet header of the channel to be tested in the uplink data packets in the ping-pong buffer, starting from the matching uplink data packet, the uplink data packet in the ping-pong buffer is extracted, and the extracted uplink data packet is written into the RAM at the clock frequency of the RRU, and the format of the uplink data of the channel to be tested is converted into the format corresponding to the PCIE interface through the RAM, and the uplink data of the channel to be tested is converted from the service clock domain to the PCIE clock domain; The method of transmitting the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface includes: The uplink data of the channel to be tested buffered in the RAM is transmitted to the DDR at the clock frequency of the PCIE interface.

7. The device according to claim 6, characterized in that The processor is specifically configured to read the computer program in the memory and perform the following operations: Transmitting the header of the matched uplink data packet to the RAM; Extracting the data of the matched uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM; After waiting for a specified period of time, the header of the next uplink data packet in the ping-pong buffer is transmitted to the RAM; Extracting the data of the next uplink data packet according to the data start bit and the data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM; Repeat the steps of waiting for a specified period of time, transferring the packet header of the next uplink data packet in the ping-pong cache to the RAM, and extracting the data of the next uplink data packet according to the data start bit and data end bit corresponding to the channel to be tested, and transferring the extracted data to the RAM, until all the uplink data packets of the channel to be tested in the ping-pong cache are transferred to the RAM.

8. The device according to claim 5, characterized in that The processor is specifically configured to read the computer program in the memory and perform the following operations: Aligning the uplink data of the channel to be tested cached in the RAM with the control information pre-cached in the FIFO module, and transmitting the uplink data of the channel to be tested cached in the RAM and the control information pre-cached in the FIFO module to the DDR through the PCIE interface, wherein the control information includes a preset total data length and a preset first address; Starting from the preset first address, the uplink data of the channel to be tested transmitted through the PCIE interface is written into the DDR until the data of the channel to be tested written into the DDR reaches the preset total data length.

9. An RRU testing device, characterized in that: include: An input unit, used for inputting uplink simulation data of at least one channel into a path processing module of a radio remote unit RRU; A cache unit, used for ping-pong caching of uplink data output by the uplink channel packet processing module of the RRU; An extraction unit is used to extract the uplink data of the channel to be tested from the uplink data of the ping-pong buffer, cache the uplink data of the channel to be tested in a random access memory RAM, convert the format of the uplink data of the channel to be tested into a format corresponding to the PCIE interface through the RAM, and convert the uplink data of the channel to be tested from the service clock domain to the PCIE clock domain; The transmission unit is used to transmit the uplink data of the channel to be tested cached in the RAM to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and transmit the uplink data of the channel to be tested cached in the DDR to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether the channel to be tested has a fault.

10. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the method according to any one of claims 1 to 4.

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