An ultra-low power switch detection circuit

Abstract

The present invention discloses an ultra-low power consumption switch value detection circuit. The technical solution of the circuit mainly comprises a switch value input INPUT, an external low-level pulse output pin INT, a switch value state output ACC_DET, a plurality of resistors, a plurality of capacitors, a diode, a PNP transistor, and a plurality of MOS transistors. When the switch value on the INPUT changes, INT generates a low-level pulse for waking up a single-chip microcomputer, and at the same time, ACC_DET provides the single-chip microcomputer with information on whether the current switch value is normally open or normally closed. The switch value detection circuit has low power consumption when in operation, which can greatly extend the standby time of battery-powered equipment. The switch value detection circuit can generate a jump interrupt signal, which can meet the requirements of most processors.

Description

Technical Field

[0001] The present invention relates to the field of signal detection, and in particular to an ultra-low power consumption switch value detection circuit. Background Art

[0002] Some battery-powered IoT devices, such as flood alarms, door magnetic alarms, access control systems, doorbell switches, and SOS systems, have relatively high power consumption for switch quantity detection circuits, or high power consumption after a jump, which is not conducive to high-frequency switch quantity change detection. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the present invention aims to provide an ultra-low power consumption switch value detection circuit.

[0004] The above technical objectives of the present invention are achieved through the following technical solutions:

[0005] One includes an input switch value INPUT, an external low-level pulse output pin INT, and a switch value status output ACC_DET, specifically:

[0006] The input switch value INPUT is connected to the first pin of the resistor R201 and the first pin of the resistor R238. The second pin of the resistor R201 is connected to the base of the PNP transistor Q201. The second pin of the resistor R238 is connected to the emitter of the PNP transistor Q201 and the positive electrode of the power supply. The collector of the PNP transistor Q201 is connected to the gate of the MOS transistor Q206 and the positive electrode of the diode D203. The drain of the MOS transistor Q206 is connected to the positive electrode of the power supply. The source is connected to the gate of the MOS transistor Q205 and the first pin of the capacitor C205. At the same time, it is connected to the drain of the MOS transistor Q209 through the resistor R254. The cathode of the diode D203 is connected to the gate of the MOS transistor Q210, the gate of the MOS transistor Q209, and the first pin of the capacitor C204, and is connected to the drain of the MOS transistor Q205 through the resistor R208. The drain of the MOS transistor Q210 is connected to ACC_DET. The second pin of the capacitor C204 is connected to the gate of the MOS transistor Q202 and grounded through the resistor R202. The second pin of the capacitor C205 is connected to the gate of the MOS transistor Q203 and grounded through the resistor R204. The drain of the MOS transistor Q202 and the drain of the MOS transistor Q203 are connected in parallel and connected to INT.

[0007] More preferably, the sources of the MOS transistors Q205 , Q209 , Q210 , Q202 and Q203 are all grounded.

[0008] More preferably, the collector of the PNP transistor Q201 is grounded via a resistor R207.

[0009] In summary, the present invention has the following beneficial effects compared to the prior art:

[0010] 1. The switch detection circuit has low power consumption when working, which can greatly extend the standby time of battery-powered equipment;

[0011] 2. The switch detection circuit can generate a jump interrupt signal, which can meet the requirements of most processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily apparent by reading the following detailed description with reference to the accompanying drawings, in which several embodiments of the present invention are shown by way of example and not limitation, in which:

[0013] Figure 1 A circuit diagram of an embodiment. DETAILED DESCRIPTION

[0014] The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. The "embodiment" or "implementation method" in the specification may represent one embodiment or one implementation method, or may represent some embodiments or some implementation methods.

[0015] Those skilled in the art will appreciate that the embodiments of the present invention may be implemented as a system, apparatus, device, method, or computer program product. Therefore, the present disclosure may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or in a combination of hardware and software.

[0016] According to an embodiment of the present invention, an ultra-low power consumption switch value detection circuit is proposed.

[0017] It should be noted that any number of elements in the drawings is for illustration only and not for limitation, and any naming is only for distinction and does not have any limiting meaning.

[0018] The following briefly describes the technical terms involved in the present invention so that relevant personnel can better understand the present solution.

[0019] An ultra-low power switch detection circuit includes a switch input INPUT, an external low-level pulse output pin INT, a switch status output ACC_DET, several resistors, several capacitors, a diode, a PNP transistor, and several MOS tubes, specifically:

[0020] The input switch quantity INPUT is connected to the first pin of the resistor R201 and the first pin of the resistor R238, and the second pin of the resistor R201 is connected to the base of the PNP transistor Q201 to control the conduction and shutdown of the PNP transistor Q201. The second pin of the resistor R238 is connected to the emitter of the PNP transistor Q201 and the positive pole of the power supply. The collector of the PNP transistor Q201 is connected to the gate of the MOS transistor Q206 and the positive pole of the diode D203 and is grounded through the resistor R207. The drain of the MOS transistor Q206 is connected to the positive pole of the power supply, and the source is connected to the gate of the MOS transistor Q205 and the first pin of C205. At the same time, it is connected to the drain of the MOS transistor Q209 through the resistor R254. The cathode of the diode D203 is connected to the gate of the MOS transistor Q210 and the MOS transistor Q20 The gate 9 is connected to the first pin of capacitor C204 and to the drain of MOS transistor Q205 through resistor R208. The drain of MOS transistor Q210 is connected to ACC_DET. The sources of MOS transistors Q205, Q209, and Q210 are all grounded. The second pin of capacitor C204 is connected to the gate of MOS transistor Q202 and to ground through resistor R202. The second pin of capacitor C205 is connected to the gate of Q203 and to ground through resistor R204. The drain of MOS transistor Q202 and the drain of MOS transistor Q203 are connected in parallel and connected to INT. When either MOS transistor Q202 or MOS transistor Q203 is turned on, a low-level pulse is generated on the INT pin, and the sources of MOS transistors Q202 and Q203 are all grounded.

[0021] When the switching value on INPUT changes from high to low, transistor Q201 turns on, the anode of diode D203 and the gate of MOS transistor Q206 are set high, and the upper path charges capacitor C204 through resistor R202. At this time, Q202 turns on, generating a low-level pulse on the INT pin. The pulse width is determined by the time constant of capacitor C204 and resistor R202. At the same time, MOS transistor Q206 on the lower path turns off, and then MOS transistor Q209 turns on. After turning on, the high level of Q206 is quickly discharged through R254. At the same time, MOS transistor Q210 also turns on, and the ACC_DET signal is short-circuited to ground, which is used to detect the low-level state of the INPUT signal.

[0022] When the switching value on INPUT changes from low level to high level, transistor Q201 will be turned off and MOS transistor Q206 will be turned on. At this time, the source of MOS transistor Q206 will be high level, and the lower path will charge capacitor C205 through resistor R204. At this time, MOS transistor Q203 will be turned on, thereby generating a low-level pulse on the INT pin. The pulse width is determined by the time constant of capacitor C205 and resistor R204. At the same time, MOS transistor Q205 will be turned on, allowing the high level of the cathode of diode D203 to be quickly discharged through resistor R208. Finally, MOS transistor Q210 will be turned off, signal ACC_DET will be open to ground, and the detection INPUT input terminal will become high level.

[0023] When the switch is long open, the current in the circuit = the voltage level at pin 1 of Q206 / R207 = 3.0V / 10MΩ = 0.3uA; when the switch is long closed, the current in the circuit = the voltage level at pin 2 of Q201 / (R238+R201) = 3.0V / 10MΩ = 0.3uA.

[0024] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

Claims

1. An ultra-low power consumption switch detection circuit, characterized in that: Including input switch value INPUT, external low-level pulse output pin INT, switch value status output ACC_DET, specifically: The input switch value INPUT is connected to the first pin of the resistor R201 and the first pin of the resistor R238, the second pin of the resistor R201 is connected to the base of the PNP transistor Q201, the second pin of the resistor R238 is connected to the emitter of the PNP transistor Q201 and the positive electrode of the power supply, the collector of the PNP transistor Q201 is connected to the gate of the MOS transistor Q206 and the positive electrode of the diode D203, the drain of the MOS transistor Q206 is connected to the positive electrode of the power supply, the source is connected to the gate of the MOS transistor Q205 and the first pin of the capacitor C205, and is connected to the drain of the MOS transistor Q209 through the resistor R254, the cathode of the diode D203 is connected to the gate of the MOS transistor Q210, the MO The gate of the S transistor Q209 is connected to the first pin of the capacitor C204, and is connected to the drain of the MOS transistor Q205 through the resistor R208. The drain of the MOS transistor Q210 is connected to ACC_DET. The second pin of the capacitor C204 is connected to the gate of the MOS transistor Q202 and is grounded through the resistor R202. The second pin of the capacitor C205 is connected to the gate of the MOS transistor Q203 and is grounded through the resistor R204. The drain of the MOS transistor Q202 and the drain of the MOS transistor Q203 are connected in parallel and connected to INT. The sources of the MOS transistors Q205, Q209, Q210, Q202, and Q203 are all grounded.

2. The ultra-low power consumption switch detection circuit according to claim 1, characterized in that: The collector of the PNP transistor Q201 is grounded via a resistor R207.

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