Error information recording method and device, electronic equipment, and storage medium

Abstract

Embodiments of the present application provide an error information recording method and device, electronic equipment and storage medium, and relate to the technical field of chip automatic test equipment. The method comprises a plurality of digital boards, a main control card and a memory. First, a test vector is created and run to generate channel data. The main control card controls the digital board to mark error data and corresponding station information according to a preset rule to form first error information. The main control card controls the digital board to convert the first error information into second error information through a data transmission mode. The second error information sent by the digital board is received, and third error information is parsed from the second error information. According to a preset gating condition, fourth error information is screened from the third error information, and the fourth error information is stored in the memory. The method can realize synchronous recording of error information for multiple test stations.

Description

Technical Field

[0001] This invention relates to the field of automated chip testing equipment technology, and in particular to error information recording methods and devices, electronic devices, and storage media. Background Technology

[0002] In chip testing technology, when running chip test vectors, automated test equipment generates corresponding clock cycles according to the chip's requirements. In each clock cycle, it provides input stimulation to the chip and compares the output feedback level to verify its correctness. When the test vector runs incorrectly, the automated test equipment needs to automatically record a certain number of error messages in the memory of the automated test equipment board. However, existing technology cannot record error messages simultaneously for multiple different test stations allocated to different test boards. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, this invention proposes an error information recording method and apparatus, electronic device, and storage medium capable of simultaneously recording error information for multiple different testing stations.

[0004] To achieve the above objectives, a first aspect of the present invention provides an error information recording method applied to a testing device. The testing device includes a plurality of digital boards, a main control card, and a memory. Each digital board contains a plurality of digital channels. The plurality of digital boards are respectively connected to the main control card, and the memory is connected to the main control card. The method includes:

[0005] Create and run test vectors to generate channel data;

[0006] The digital board is controlled to mark the erroneous data and corresponding workstation information in the channel data according to preset rules, thereby forming the first error information;

[0007] The control digital board converts the first error message into a second error message via data transmission.

[0008] Receive the second error message sent by the digital board, and parse the third error message from the second error message;

[0009] Based on preset selection criteria, a fourth error message is selected from the third error message;

[0010] The fourth error message is stored in the memory.

[0011] In some embodiments of the present invention, the control of the digital board to mark erroneous data and corresponding workstation information in the channel data according to preset rules, forming first error information, including:

[0012] Identify erroneous data in the channel data based on the truth table;

[0013] Mark the erroneous data;

[0014] The first error information is generated based on the channel data containing the error data marker and the corresponding workstation information.

[0015] In some embodiments of the present invention, controlling the digital board to convert the first error information into a second error information via data transmission includes:

[0016] The first error message is sent to the encoder via wired communication.

[0017] The encoder converts the first error information into encoded data;

[0018] The encoded data is adjusted using an equalizer to generate the second error message;

[0019] The second error message is sent to the main control card via the driver.

[0020] In some embodiments of the present invention, receiving the second error information sent by the digital board and parsing the third error information from the second error information includes:

[0021] Set the receive count counter;

[0022] Receive the second error message and calculate the number of rows;

[0023] The second error message is parsed into parallel data using a decoder;

[0024] The third error message is derived based on the parallel data and the corresponding row number.

[0025] In some embodiments of the present invention, the step of filtering out the fourth error information from the third error information according to preset gating conditions includes:

[0026] The third error information is filtered by the recording mode selection criteria to form the recording mode error information;

[0027] Then, the error information of the recording mode is filtered through the workstation information selection criteria to form the fourth error information.

[0028] In some embodiments of the present invention, the recording mode selection conditions include a recording mode that starts recording based on the number of rows, a recording mode that only records error information, and a recording mode that starts recording from the first line of error information.

[0029] In some embodiments of the present invention, the step of further filtering the record pattern error information through workstation information gating conditions to form the fourth error information includes:

[0030] Select the corresponding digital channel based on the workstation information;

[0031] The failure flag bits of all digital channel workstations in the workstation information are NOTed and then ANDed to form the workstation information selection condition.

[0032] The error information of the recording mode that meets the above workstation information selection criteria is filtered as the fourth error information.

[0033] To achieve the above objectives, a second aspect of the present invention provides an error information recording device. The testing device includes a plurality of digital boards, a main control card, and a memory. Each digital board contains a plurality of digital channels. The plurality of digital boards are respectively connected to the main control card. The memory is connected to the main control card. The device further includes:

[0034] The test vector creation and execution module is used to create and run test vectors and generate channel data;

[0035] The first error information generation module is used to control the digital board to mark the error data and corresponding workstation information in the channel data according to preset rules, thereby forming the first error information.

[0036] The second error information conversion module is used to control the digital board to convert the first error information into the second error information through data transmission.

[0037] The third error message parsing module is used to receive the second error message sent by the digital board and parse the third error message from the second error message;

[0038] The fourth error information filtering module is used to filter out the fourth error information from the third error information according to preset selection conditions;

[0039] A memory module is used to store the fourth error message into the memory.

[0040] To achieve the above objectives, a third aspect of the present invention provides an electronic device comprising:

[0041] At least one memory;

[0042] At least one processor;

[0043] At least one program;

[0044] The program is stored in memory, and the processor executes the at least one program to achieve the following:

[0045] The error message recording method described in the first aspect above.

[0046] To achieve the above objectives, a fourth aspect of the present invention provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the error information recording method as described in the first aspect above.

[0047] The error information recording method, apparatus, electronic device, and storage medium proposed in this invention are applied to a testing device. The testing device includes several digital boards, a main control card, and memory. Each digital board contains several digital channels. The digital boards are connected to the main control card, and the memory is connected to the main control card. First, a test vector is created and run to generate channel data. The digital boards are controlled to mark error data and corresponding workstation information in the channel data according to preset rules, forming first error information. The digital boards are then controlled to convert the first error information into second error information via data transmission. The second error information sent by the digital boards is received, and a third error information is parsed from the second error information. A fourth error information is selected from the third error information according to preset gating conditions and stored in memory. This application can record error information for multiple test stations while running test vectors at high speed. Attached Figure Description

[0048] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0049] Figure 1 This is a hardware framework diagram of an error information recording method provided in one embodiment of the present invention;

[0050] Figure 2 This is a flowchart of an error information recording method provided in one embodiment of the present invention;

[0051] Figure 3 This is the present invention. Figure 2 A flowchart of an error information recording method provided in one embodiment of step S120;

[0052] Figure 4 This is the present invention. Figure 2 A flowchart of an error information recording method provided in one embodiment of step S130;

[0053] Figure 5 This is the present invention. Figure 2 A flowchart of an error information recording method provided in one embodiment of step S140;

[0054] Figure 6 This is the present invention. Figure 2 A flowchart of an error information recording method provided in one embodiment of step S150;

[0055] Figure 7 This is a schematic diagram of the preset gating conditions of an error information recording method provided in an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram illustrating the row number condition of an error information recording method provided in an embodiment of the present invention;

[0057] Figure 9 This is a schematic diagram of the workstation information selection conditions for an error information recording method provided in an embodiment of the present invention;

[0058] Figure 10 This is the present invention. Figure 6 A flowchart of an error information recording method provided in one embodiment of step S520;

[0059] Figure 11 This is an illustration of error information recording using an embodiment of the error information recording method provided by the present invention;

[0060] Figure 12 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0062] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0063] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features or the order of the indicated technical features, nor is it necessary to describe a specific order or sequence.

[0064] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0065] This invention provides an error information recording method, apparatus, electronic device, and storage medium, applied to a testing device. The hardware framework includes several digital boards, a main control card, and memory. Each digital board contains several digital channels, and the digital boards are respectively connected to the main control card. The memory is also connected to the main control card. First, a test vector is created and run to generate channel data. The digital boards are controlled to mark error data and corresponding workstation information in the channel data according to preset rules, forming first error information. The digital boards are then controlled to convert the first error information into second error information via data transmission. The second error information sent by the digital boards is received, and a third error information is parsed from it. A fourth error information is selected from the third error information according to preset gating conditions and stored in memory. Existing technologies cannot simultaneously record error information for multiple different test workstations allocated to different test boards, while this application can synchronously record error information for multiple test workstations while running test vectors at high speed.

[0066] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0067] like Figure 1 As shown, Figure 1 This is a hardware framework diagram of an error information recording method provided in one embodiment of the present invention. Figure 1 In the example, the hardware framework includes a main control card 101, a digital board 102, a digital channel 103, and memory 104.

[0068] The testing device includes several digital boards 102. In some embodiments, one testing device includes eight digital boards 102, and each digital board 102 contains several digital channels 103. In some embodiments, one digital board 102 has 32 digital channels 103. In some embodiments, the testing device has 256 digital channels and eight digital boards. The digital boards send the collected first error information to the main control card. The main control card is connected to the memory. In some embodiments, in order to verify and analyze the chip's function and performance, the testing device needs to automatically record 1024 first error messages in the internal buffer of the digital board when the test vector runs incorrectly. These messages include the number of lines with errors, chip pins, high and low levels, etc. The computer terminal reads the data from the memory buffer and converts it to present the information so that test engineers and chip design engineers can analyze and locate the cause.

[0069] Figure 2This is an optional flowchart of the error information recording method provided in the embodiments of the present invention. Figure 2 The method may include, but is not limited to, steps S110 to S160.

[0070] Step S110: Create and run the test vector to generate channel data;

[0071] Step S120: Control the digital board to mark the erroneous data and corresponding workstation information in the channel data according to preset rules, and form the first error information;

[0072] Step S130: Control the digital board to convert the first error information into the second error information through data transmission;

[0073] Step S140: Receive the second error message sent by the digital board and parse the third error message from the second error message;

[0074] Step S150: Based on the preset gating conditions, filter out the fourth error message from the third error message;

[0075] Step S160: Store the fourth error message in memory.

[0076] In step S110 of some embodiments, a test vector is created and run to generate channel data; the main control card creates and runs the test vector to generate channel data. In some embodiments, the test vector can have up to 16 million rows. In step S120 of some embodiments, the control digital board marks the error data and corresponding workstation information in the channel data according to preset rules to form first error information. When the test device performs multi-workstation simultaneous testing, each digital channel may be assigned to any workstation according to the chip test board design requirements to identify the current channel. During the test vector operation, the main control card controls the digital board to mark the error data generated during the test and the workstation information corresponding to the error data according to preset rules, and forms the first error information based on the channel data with error data marking and corresponding workstation information. In some embodiments, the main control card sets a separate allow bit for each digital channel, and stops recording after the workstation corresponding to this channel has recorded 1024 pieces of channel data. In some embodiments, channels of the same digital board are assigned to different workstations. Each workstation corresponds to digital channels on several different digital boards simultaneously. When a single workstation records 1024 lines of channel data, it notifies all digital channels at that workstation to stop recording channel data to avoid overwriting previously useful information. However, other workstations that have not yet recorded 1024 lines of channel data will continue recording. In step S130 of some embodiments, the control digital board converts the first error information into the second error information through data transmission. The main control card controls the digital board to convert the first error information into encoded data via parallel data from the encoder, then into the second error information via the equalizer, and sends it to the main control card. In step S140 of some embodiments, the second error information sent by the digital board is received, and the third error information is parsed from the second error information. The main control card receives the second error information sent by the digital board and parses the third error information from the second error information using a decoder. In step S150 of some embodiments, a fourth error message is selected from the third error messages according to preset gating conditions. The preset gating conditions include recording mode gating conditions and workstation information gating conditions. Messages meeting the preset gating conditions are selected from the third error messages as the fourth error messages. In step S160 of some embodiments, the fourth error message is stored in memory. Storing the fourth error message in memory allows for later review and location of the error cause.

[0077] The error information recording method provided by the above-described embodiments of the present invention assigns a workstation information to each digital channel. When running up to 16 million test vectors, all generated error information will be recorded, regardless of the total number of test vectors or the test cycle of the test vectors. It can record error information for multiple test workstations while running test vectors at high speed.

[0078] Please refer to Figure 3 In some embodiments, step S120 may include, but is not limited to, steps S210 to S230;

[0079] Step S210: Identify erroneous data in the channel data according to the truth table;

[0080] Step S220: Mark the erroneous data;

[0081] Step S230: Generate the first error information based on the channel data with error data markers and corresponding workstation information.

[0082] Specifically, in step S210 of some embodiments, erroneous data in the channel data is identified according to the truth table; during the test, the test signals include cmpen comparator enable, cmptruth correct result, these two values ​​are expected to be stored on the digital board, comql and comqh are feedback signals of the chip under test, which are divided into low-level signals and high-level signals, and cmpresult is the comparison result. When it is 1, it represents that the chip feedback is wrong, and otherwise it is correct. The truth table is shown in Table 1:

[0083] In step S220 of some embodiments, error data is marked. According to the truth table in Table 1, the chip reports an error only when the cmpresult comparison result is 1, and the error data is marked at this time. In step S230 of some embodiments, a first error message is formed based on the channel data with the error data mark and the corresponding station information. In some embodiments, the marked error data is from digital channel 1 station and digital channel 4 station, and the channel data with the error data mark and the corresponding station information is used to form the first error message.

[0084] Table 1

[0085] cmpen cmptruth cmpql cmpqh cmpresult 0 x x x 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

[0086] The error information recording method provided by the above-described embodiments of the present invention uses truth table rules to form first error information. Since each digital channel is marked with workstation information, the first error information contains workstation information, thereby allowing the location of the error in the channel data to be located.

[0087] Please refer to Figure 4 In some embodiments, step S130 may include, but is not limited to, steps S310 to S340;

[0088] Step S310: The first error message is sent to the encoder via wired communication.

[0089] In step S320, the encoder converts the first error information into encoded data;

[0090] Step S330: Adjust the encoded data using an equalizer to generate the second error message;

[0091] Step S340: Send the second error message to the main control card via the driver.

[0092] Specifically, in step S310 of some embodiments, the first error information is sent to the encoder via wired communication; the parallel first error information is sent to the 8B / 10B encoder via the interface FIFO. In step S320 of some embodiments, the encoder converts the first error information into encoded data to avoid the data containing excessively long consecutive 0s or 1s. This is then sent to a serializer to convert the parallel data into serial data. In step S330 of some embodiments, the encoded data is adjusted by an equalizer to form the second error information. In step S340 of some embodiments, the second error information is sent to the main control card via a driver.

[0093] In some embodiments, two sets of low-voltage differential signal lines are used to transmit the clock and data separately, and the first error information is transmitted to the main control card.

[0094] The error information recording method provided by the above-described embodiments of the present invention, using a serializer, requires only one set of differential lines to achieve high-speed data transmission, reaching speeds of 1 Gbit / s or higher, thus meeting the needs for high-speed transmission of large amounts of data.

[0095] Please refer to Figure 5 In some embodiments, step S140 may include, but is not limited to, steps S410 to S440;

[0096] Step S410: Set the received quantity counter;

[0097] Step S420: Receive the second error message and calculate the number of rows;

[0098] Step S430: The second error message is parsed into parallel data using a decoder;

[0099] Step S440: Calculate the third error message based on the parallel data and the corresponding row number.

[0100] Specifically, in step S410 of some embodiments, a receive count counter is set; a receive count counter is set on the main control card to count which row of test vectors is currently received. In step S420 of some embodiments, second error information is received and the row number is calculated; in step S430 of some embodiments, the second error information is parsed into parallel data by a decoder; on the main control card, in the clock and data recovery circuit, the sampling clock is recovered from the serial second error information from the data, and converted into an aligned parallel signal by a deserializer. Then, it is decoded or descrambled by an 8B / 10B decoder to form parallel data, from which the corresponding channel data can be parsed. In step S440 of some embodiments, third error information is derived based on the parallel data and the corresponding row number. Each received row of test vectors is counted accordingly, and the third error information is derived based on the parallel data and the corresponding row number.

[0101] The error information recording method provided by the above-described embodiments of the present invention, through the deserializer method, can convert parallel data into serial data, achieve high-speed data transmission, and simultaneously record the number of rows of errors each time in a counting manner, accurately locate the position of the error in the channel data, and can also start recording at any row position for fixed-point debugging.

[0102] Please refer to Figure 6 In some embodiments, step S150 may include, but is not limited to, steps S510 to S520;

[0103] Step S510: Filter the third error information through the recording mode selection criteria to form the recording mode error information;

[0104] In step S520, error information in the record mode is filtered through the workstation information selection criteria to form the fourth error information.

[0105] Specifically, in step S510 of some embodiments, the third error information is filtered through recording mode selection conditions to form recording mode error information; in some embodiments, the recording mode selection conditions include a recording mode starting from the row number, a recording mode that only records error information, and a recording mode starting from the first row of error information. The recording mode starting from the row number records from the position at the beginning of the row number, recording a maximum of 1024 subsequent rows; the recording mode that only records error information records only the error information in the fourth error information, recording a maximum of 1024 rows; the recording mode starting from the first row of error information records the position at which the error information first appears in the fourth error information, and records from this position, recording a maximum of 1024 subsequent rows.

[0106] In step S520 of some embodiments, the recording mode error information is further filtered through the workstation information gating condition to form the fourth error information. The third error information and the corresponding row number are sent to the workstation information gating condition. The third error information is the channel data selected by the recording mode gating condition, which contains error data markers and corresponding workstation information. Since the channels of the same digital board are assigned to different workstation information, one workstation information corresponds to the digital channels on several different digital boards. Each digital channel contains a failure flag bit. The failure flag bit is inverted to obtain the gating flag bit. All gating flag bits are ANDed to determine whether to start recording error information. In some specific embodiments, initially, no error information appears, and the failure flag bits of all digital channels are 0. The failure flag bits are inverted to obtain all gating flag bits as 1. All gating flag bits are ANDed to obtain a result of 1, indicating that error information has not yet started recording. When the failure flag of one digital channel is set from 0 to 1, that is, when one of the strobe flags is set from 1 to 0, all the strobe flags are ANDed together to obtain a result of 0, which indicates that error information is being recorded. Error information is recorded until the recording mode selected in step S510 is met. For example, if the recording mode based on the number of rows is selected, then the following 1024 rows of data are recorded starting from the row number. This dataset is the fourth error information.

[0107] Please refer to Figure 7 The present invention provides a schematic diagram of preset selection conditions for an error information recording method according to an embodiment of the present invention. The preset selection conditions include a third error information 701, a recording mode selection condition 702, a workstation information selection condition 703, and a fourth error information 704. The third error information 701 is first filtered by the recording mode selection condition 702, and then filtered by the workstation information selection condition 703 to obtain the fourth error information 704.

[0108] Please refer to Figure 8 This invention provides a schematic diagram of the row count conditions for an error information recording method according to an embodiment of the present invention. The row count conditions include a row count selection register 801, a row count counter 802, a row count enable 803, and a row count strobe gate 804. In some embodiments, when the row count selection register 801 pre-stores a value of 5, the main control card begins receiving data, and the row count counter 802 begins counting. When the count value is 4, the values ​​of the row count selection register 801 and the row count counter 802 are inconsistent, and the row count enable 803 is not enabled. When the count value of the row count counter 802 is 5, the values ​​of the row count selection register 801 and the row count counter 802 are consistent, the row count enable 803 is enabled, and the row count strobe gate is opened to record information.

[0109] Please refer to Figure 9This invention provides a schematic diagram of the station information gating conditions for an error information recording method according to an embodiment of the present invention. The station information gating conditions include recording mode error information 901, station information gating conditions 703, and fourth error information 704. Recording mode error information 901 includes channel 0 data, channel 0 failure flag, channel 1 data, channel 1 failure flag, etc. The condition for a digital channel to start recording error information is that all digital channels contain one failure flag. In the same station, if any channel has a failure flag set to 1, all digital channels in that station will be opened and begin recording error information. This also means that if any gating flag is set to 0, all digital channels in that station will be opened and begin recording error information. The condition for a digital channel to stop recording error information is that if all channels have failure flags set to 0, then all gating flags are 1. If the AND operation of the gating flags results in 1, then error information recording stops.

[0110] In some embodiments, the selection condition for the recording mode is the row number start recording mode. Recording is performed based on the starting position of the row number, recording a maximum of 1024 rows. In station 1, this corresponds to channels 0, 1, 2, etc. The test vector starts working, and channel data transmission begins. If an error occurs in digital channel 1, the gating flag is set from 1 to 0, and error data recording begins. After the test vector runs for a period of time, the number of rows counted in channel 1 reaches 1024, the gating flag is set from 0 to 1, and the gating flags of other channels are also 1. Finally, the AND result is 1, and error information recording stops.

[0111] Please refer to Figure 10 In some embodiments, step S520 may include, but is not limited to, steps S610 to S630;

[0112] Step S610: Select the corresponding digital channel based on the workstation information;

[0113] Step S620: After performing a NOT operation on the failure flag bits of all digital channel workstations in the workstation information, perform a AND operation to form the workstation information selection condition.

[0114] Step S630: Filter the record pattern error information that meets the workstation information selection criteria as the fourth error information.

[0115] In step S610 of some embodiments, the corresponding digital channel is selected based on the workstation information. There are multiple digital channels on the same digital board, but the workstation information marked on these channels is different. Digital channels belonging to the same workstation information are selected into a set. In step S620 of some embodiments, the failure flag bits of all digital channels within the workstation information are NOT-NOT-ANDed to form the workstation information gating condition. The workstation information includes a failure flag bit. When the failure flag bit is 1, it indicates that the channel has transmitted a failure flag bit. The failure flag bit is NOT-NOT-ANDed to obtain the gating flag bit. The gating flag bit is then ANDed. If the AND result is 0, it means to continue recording error information; if the AND result is 1, it means to stop recording error information. In step S630 of some embodiments, the recording mode error information that meets the workstation information gating condition is filtered as the fourth error information. According to the embodiment, the error information recorded in step S620 of the workstation information gating condition is used as the fourth error information. The fourth error information includes the selected channel data and the corresponding row number. The channel data is stored in the test vector running data memory, and the corresponding row number is stored in the row number memory.

[0116] Please refer to Figure 11 The error information recording method provided in one embodiment of the present invention is illustrated in the diagram. After the fourth error information is stored in memory, the terminal device can retrieve the data in memory for reading. After reading the fourth error information, the terminal device compares the running data with the correct test vector and marks the vector points where errors occur. The running error information of the test vector is clear at a glance, and chip designers can see the running status of the test vector very intuitively, so as to further analyze the error situation.

[0117] This invention also provides an error information recording device that can implement the above-described error information recording method. The testing device includes several digital boards, a main control card, and a memory. Each digital board contains several digital channels. The digital boards are respectively connected to the main control card, and the memory is connected to the main control card. The device also includes:

[0118] The test vector creation and execution module is used to create and run test vectors and generate channel data;

[0119] The first error message generation module is used to control the digital board to mark the error data and corresponding workstation information in the channel data according to preset rules, thereby forming the first error message.

[0120] The second error information conversion module is used to control the digital board to convert the first error information into the second error information through data transmission.

[0121] The third error message parsing module is used to receive the second error message sent by the digital board and parse the third error message from the second error message;

[0122] The fourth error message filtering module is used to filter out the fourth error message from the third error message according to preset selection conditions;

[0123] The memory module is used to store the fourth error message in memory.

[0124] The specific implementation of the error information recording device in this embodiment is basically the same as the specific implementation of the error information recording method described above, and will not be repeated here.

[0125] This disclosure also provides an electronic device, including:

[0126] At least one memory;

[0127] At least one processor;

[0128] At least one program;

[0129] The program is stored in memory, and the processor executes at least one program to implement the error information recording method described above in this invention. The electronic device can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0130] Please see Figure 12 , Figure 12 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0131] The processor 1201 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention.

[0132] The memory 1202 can be implemented in the form of ROM (Read-Only Memory), static storage device, dynamic storage device, or RAM (Random Access Memory). The memory 1202 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1202 and is called and executed by the processor 1201 to execute the error information recording method of the embodiments of this disclosure.

[0133] The input / output interface 1203 is used to implement information input and output;

[0134] The communication interface 1204 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0135] Bus 1205 transmits information between various components of the device (e.g., processor 1201, memory 1202, input / output interface 1203, and communication interface 1204);

[0136] The processor 1201, memory 1202, input / output interface 1203 and communication interface 1204 are connected to each other within the device via bus 1205.

[0137] This disclosure also provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the above-described error information recording method.

[0138] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0139] The embodiments described in this invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of this invention, and do not constitute a limitation on the technical solutions provided by the embodiments of this invention. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this invention are also applicable to similar technical problems.

[0140] It will be understood by those skilled in the art that Figures 2 to 6 , Figure 10 The technical solutions shown do not constitute a limitation on the embodiments of the present invention, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0141] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0143] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0144] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0148] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0149] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the claims of the present invention.

Claims

1. A method for recording error messages, characterized in that, The method is applied to a testing device, which includes several digital boards, a main control card, and a memory. Each digital board contains several digital channels. The digital boards are respectively connected to the main control card, and the memory is connected to the main control card. Create and run test vectors to generate channel data; The control board identifies erroneous data in the channel data according to a truth table, marks the erroneous data, and forms a first error message based on the marked erroneous data and the channel data corresponding to the workstation information. The main control card sets a separate allow bit for each digital channel. Recording stops after the workstation corresponding to the digital channel has recorded a preset number of channel data entries. Digital channels on the same digital board can be assigned to different workstations, and each workstation corresponds to a digital channel on a different digital board. When a single workstation records a preset number of channel data entries, it notifies all digital channels at that workstation to stop recording, while other workstations that have not yet recorded the preset number of channel data entries continue recording. The control digital board sends the first error information to the encoder via wired communication. The encoder converts the first error information into encoded data, adjusts the encoded data through an equalizer to form a second error information, and sends the second error information to the main control card through a driver. Receive the second error message sent by the digital board, and parse the third error message from the second error message; Based on preset selection criteria, a fourth error message is selected from the third error message; The fourth error message is stored in the memory; In the process of simultaneous testing at multiple stations in the testing device, each digital channel is assigned to any station according to the design requirements of the chip test board to identify the current channel; in each clock cycle, the chip is provided with input stimulus and the output feedback level is compared at the same time to verify its correctness. During the test, the test signals include cmpen comparator enable, cmptruth correct result, comql and comqh are feedback signals of the chip under test, which are divided into low-level signals and high-level signals, and cmpresult is the comparison result. When it is 1, it means that the chip feedback is wrong, and otherwise it is correct. After the fourth error message is stored in memory, the terminal device reads the fourth error message, compares the running data with the correct test vector, and marks the vector points where errors occur in order to obtain the running error information of the test vector.

2. The error information recording method according to claim 1, characterized in that, The step of receiving the second error information sent by the digital board and parsing the third error information from the second error information includes: Set the receive count counter; Receive the second error message and calculate the number of rows; The second error message is parsed into parallel data using a decoder; The third error message is derived based on the parallel data and the corresponding row number.

3. The error information recording method according to claim 2, characterized in that, The step of filtering out the fourth error information from the third error information according to preset selection criteria includes: The third error information is filtered by the recording mode selection criteria to form the recording mode error information; Then, the error information of the recording mode is filtered through the workstation information selection criteria to form the fourth error information.

4. The error information recording method according to claim 3, characterized in that, The recording mode selection conditions include recording mode based on the number of rows, recording mode that only records error information, and recording mode that starts recording from the first line of error information.

5. The error information recording method according to claim 3, characterized in that, The step of further filtering the record pattern error information using workstation information selection criteria to form the fourth error information includes: Select the corresponding digital channel based on the workstation information; The failure flag bits of all digital channel workstations in the workstation information are NOTed and then ANDed to form the workstation information selection condition. The error information of the recording mode that meets the above workstation information selection criteria is filtered as the fourth error information.

6. An error information recording device, characterized in that, The device is applied to a testing apparatus, which includes several digital boards, a main control card, and a memory. Each digital board contains several digital channels. The digital boards are respectively connected to the main control card, and the memory is connected to the main control card. The recording device includes: The test vector creation and execution module is used to create and run test vectors and generate channel data; The first error information generation module is used to control the digital board to identify erroneous data in the channel data according to the truth table, mark the erroneous data, and form a first error information based on the marked erroneous data and the channel data corresponding to the workstation information. The main control card sets a separate allow bit for each digital channel. Recording stops after the workstation corresponding to the digital channel has recorded a preset number of channel data entries. The digital channels of the same digital board can be assigned to different workstations, and each workstation corresponds to a digital channel on a different digital board. When a single workstation records a preset number of channel data entries, it notifies all digital channels of that workstation to stop recording, while other workstations that have not yet recorded the preset number of channel data entries continue recording. The second error information conversion module is used to control the digital board to send the first error information to the encoder via wired communication. The encoder converts the first error information into encoded data, adjusts the encoded data through an equalizer to form the second error information, and sends the second error information to the main control card through a driver. The third error message parsing module is used to receive the second error message sent by the digital board and parse the third error message from the second error message; The fourth error information filtering module is used to filter out the fourth error information from the third error information according to preset selection conditions; A memory module is used to store the fourth error message into the memory; In the process of simultaneous testing at multiple stations in the testing device, each digital channel is assigned to any station according to the design requirements of the chip test board to identify the current channel; in each clock cycle, the chip is provided with input stimulus and the output feedback level is compared at the same time to verify its correctness. During the test, the test signals include cmpen comparator enable, cmptruth correct result, comql and comqh are feedback signals of the chip under test, which are divided into low-level signals and high-level signals, and cmpresult is the comparison result. When it is 1, it means that the chip feedback is wrong, and otherwise it is correct. After the fourth error message is stored in memory, the terminal device reads the fourth error message, compares the running data with the correct test vector, and marks the vector points where errors occur in order to obtain the running error information of the test vector.

7. An electronic device, characterized in that, include: At least one memory; At least one processor; At least one program; The program is stored in memory, and the processor executes the at least one program to achieve the following: The error message recording method as described in any one of claims 1 to 5.

8. A storage medium, said storage medium being a computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform: The error message recording method as described in any one of claims 1 to 5.

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