A method and device for preparing a superconducting quantum bit chip

Abstract

The embodiment of the present application discloses a method and device for preparing a superconducting quantum bit chip. It includes obtaining the size and pin position information of the superconducting quantum bit chip to be prepared, and obtaining the reference size of different components required for the superconducting quantum bit chip to be prepared; wherein different components are used to realize different functions of the superconducting quantum bit chip to be prepared; based on the size and pin position information of the superconducting quantum bit chip to be prepared, and the reference size of different components required for the superconducting quantum bit chip to be prepared, determine the reference data corresponding to different components respectively; based on the reference data and the preset electromagnetic simulation software, verify the reference data to obtain the actual data corresponding to different components respectively; based on the actual data, perform multi-bit chip wiring on the superconducting quantum bit chip to be prepared to realize the preparation of the superconducting quantum bit chip. Through the above method, the chip preparation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of quantum chip technology, and in particular to a method and device for preparing a superconducting quantum bit chip. Background Art

[0002] Quantum chips are the core components of quantum computers, which fundamentally determine the number and quality of bits of quantum computers and the control accuracy of quantum computers. High-quality quantum chips are the prerequisite for realizing quantum computing.

[0003] However, there are many inconveniences in the preparation of superconducting quantum bit chips in the existing related technologies. For example, there are multiple different component designs in the superconducting quantum bit chip, such as quantum bit cross capacitor design, readout resonant cavity design, transmission line design, Josephson junction design, microwave excitation line design, and flux bias line design. Different R&D personnel usually have different preparation schemes and preparation processes in the preparation process of superconducting quantum bit chips, so that when different R&D personnel prepare the same superconducting quantum bit chip, conflicts often arise, resulting in lengthy preparation process, which brings great obstacles to improving process efficiency. Summary of the invention

[0004] The embodiments of the present application provide a method and device for preparing a superconducting quantum bit chip, which is used to solve the following technical problems: the existing technology has a lengthy preparation process for superconducting quantum bit chips, which poses a great obstacle to improving process efficiency.

[0005] The present application embodiment adopts the following technical solutions:

[0006] The embodiment of the present application provides a method for preparing a superconducting quantum bit chip. The method includes obtaining the size and pin position information of the superconducting quantum bit chip to be prepared, and obtaining the reference size of different components required for the superconducting quantum bit chip to be prepared; wherein different components are used to realize different functions of the superconducting quantum bit chip to be prepared; based on the size and pin position information of the superconducting quantum bit chip to be prepared, and the reference size of different components required for the superconducting quantum bit chip to be prepared, determining the reference data corresponding to different components respectively; wherein the reference data is the data in the design drawings corresponding to different components respectively; based on the reference data and the preset electromagnetic simulation software, verifying the reference data to obtain the actual data corresponding to different components respectively; based on the actual data, performing multi-bit chip wiring on the superconducting quantum bit chip to be prepared, so as to realize the preparation of the superconducting quantum bit chip.

[0007] The embodiment of the present application can first determine the size and pin position of the chip by obtaining the size and pin position information of the superconducting quantum bit chip to be prepared, and obtain the reference size of different components required for the superconducting quantum bit chip to be prepared, so as to limit the position and size of different components. Secondly, the embodiment of the present application can draw the design drawings corresponding to different components by determining the reference data corresponding to different components, and repeatedly iterate the actual value and design value errors obtained by electromagnetic simulation software to achieve the design purpose, complete multi-bit wiring, and thus complete the preparation process of the superconducting quantum bit chip, and uniformly define the process of chip preparation, so that the whole process is clear. Furthermore, in the case where different R&D personnel prepare different components separately, the chip preparation can be completed efficiently in a short time.

[0008] In one implementation of the present application, based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, reference data corresponding to different components are determined, specifically including: based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, the reference data of the qubit cross capacitor is determined; and the reference data of the transmission line and the readout resonant cavity is determined; and the reference data of the Josephson junction is determined; and the reference data of the microwave excitation line is determined; and the reference data of the flux bias line is determined; and the reference data of the test node and the test resonant cavity is determined.

[0009] In one implementation of the present application, determining the reference data of the quantum bit cross capacitor specifically includes: determining the reference data of the cross structure inside the quantum bit cross capacitor based on the obtained reference size of the quantum bit cross capacitor, and; determining the reference data corresponding to the portion that needs to be etched away around the quantum bit cross capacitor based on the obtained reference size of the quantum bit cross capacitor.

[0010] In one implementation of the present application, reference data of the cross structure inside the qubit cross capacitor is determined based on the obtained reference size of the qubit cross capacitor, specifically including: determining a first reference width of the qubit cross capacitor based on the obtained reference size of the qubit cross capacitor; wherein the qubit cross capacitor is a cross-shaped structure, and the first reference width is the width of any edge of the qubit cross capacitor; and determining a reference spacing distance between the qubit cross capacitor and the peripheral circuit based on the obtained reference size of the qubit cross capacitor.

[0011] In one implementation of the present application, based on the obtained reference size of the quantum bit cross capacitor, the reference data corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched is determined, specifically including: determining the second reference width corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched; wherein the second reference width is the distance between the left edge and the right edge of the periphery of the quantum bit cross capacitor; and determining the reference height corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched; wherein the reference height is the vertical distance between the upper side edge and the lower edge of the periphery of the quantum bit cross capacitor.

[0012] In one implementation of the present application, reference data of a transmission line and a readout resonant cavity are determined, specifically including: comparing the acquired reference dimensions of the transmission line and the readout resonant cavity with the data in a preset database to determine a reference value of the resonant cavity frequency of the readout resonant cavity, and determining the spacing distance between two adjacent readout resonant cavities; wherein the preset database includes reference dimensions of a plurality of different readout resonant cavities, and reference values ​​of the resonant cavity frequencies corresponding to resonant cavities of different reference dimensions; simulating the readout resonant cavity and the quantum bit cross capacitor through preset electromagnetic simulation software to obtain the coupling strength between the readout resonant cavity and the quantum bit cross capacitor; and simulating the readout resonant cavity and the transmission line through preset electromagnetic simulation software to obtain the coupling strength between the readout resonant cavity and the transmission line.

[0013] In one implementation of the present application, reference data of a Josephson junction is determined, specifically including: determining the length, width and area of ​​the Josephson junction based on the obtained reference size of the Josephson junction; preparing the Josephson junction by a cross method; wherein the Josephson junction includes two different sizes, and the Josephson junctions of different sizes are arranged at intervals; and two adjacent Josephson junctions correspond to different operating frequencies.

[0014] In one implementation of the present application, reference data corresponding to the microwave excitation line and the flux bias line are determined, specifically including: determining the coupling capacitor corresponding to the microwave excitation line based on the obtained reference size of the microwave excitation line, so that the microwave excitation line is coupled to the quantum bit through the capacitor; wherein the coupling capacitor is used to transmit microwave signals to the quantum bit to change the working state of the quantum bit; determining the inductance corresponding to the magnetic flux bias line and the time magnitude based on the obtained reference size of the magnetic flux bias line; providing a magnetic flux bias to the quantum bit based on the inductance, time magnitude and magnetic flux bias line to change the working frequency of the quantum bit.

[0015] In one implementation of the present application, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared based on actual data, specifically including: based on actual data, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared; wherein, the distance between two adjacent microwave transmission lines is greater than a first preset spacing distance, the distance between other two adjacent transmission lines except the microwave transmission line is greater than a second preset spacing distance, and the first preset spacing distance is greater than the second preset spacing distance.

[0016] An embodiment of the present application provides a superconducting quantum bit chip preparation device, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can: obtain the size and pin position information of the superconducting quantum bit chip to be prepared, and obtain the reference size of different components required for the superconducting quantum bit chip to be prepared; wherein different components are used to realize different functions of the superconducting quantum bit chip to be prepared; based on the size and pin position information of the superconducting quantum bit chip to be prepared, and the reference size of different components required for the superconducting quantum bit chip to be prepared, determine the reference data corresponding to the different components respectively; wherein the reference data is the data in the design drawings corresponding to the different components respectively; based on the reference data and the preset electromagnetic simulation software, verify the reference image data to obtain the actual data corresponding to the different components respectively; based on the actual data, perform multi-bit chip wiring on the superconducting quantum bit chip to be prepared to realize the preparation of the superconducting quantum bit chip.

[0017] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: the embodiments of the present application can first determine the size and pin position of the chip by obtaining the size and pin position information of the superconducting quantum bit chip to be prepared, and obtaining the reference size of different components required for the superconducting quantum bit chip to be prepared, thereby limiting the position and size of different components. Secondly, the embodiments of the present application can draw the design drawings corresponding to different components by determining the reference data corresponding to different components, and repeatedly iterate the actual value and design value errors obtained through electromagnetic simulation software to achieve the design purpose, complete multi-bit wiring, and thus complete the preparation process of the superconducting quantum bit chip, and define the chip preparation process in a unified manner, so that the whole process is clear and organized. Furthermore, in the case where different R&D personnel prepare different components separately, the chip preparation can be completed efficiently in a short time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0019] Figure 1 A flow chart of a method for preparing a superconducting quantum bit chip provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a quantum bit cross capacitor design provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a transmission line and a readout resonant cavity design provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a Josephson junction design provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a superconducting quantum bit chip provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a superconducting quantum bit chip preparation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application provide a method and device for preparing a superconducting quantum bit chip.

[0026] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0027] Quantum chips are the core components of quantum computers, which fundamentally determine the number and quality of bits of quantum computers and the control accuracy of quantum computers. High-quality quantum chips are the prerequisite for realizing quantum computing.

[0028] However, there are many inconveniences in the preparation of superconducting quantum bit chips in the existing related technologies. For example, there are multiple different component designs in the superconducting quantum bit chip, such as quantum bit cross capacitor design, readout resonant cavity design, transmission line design, Josephson junction design, microwave excitation line design, and flux bias line design. Different R&D personnel usually have different preparation schemes and preparation processes in the preparation process of superconducting quantum bit chips, so that when different R&D personnel prepare the same superconducting quantum bit chip, conflicts often arise, resulting in lengthy preparation process, which brings great obstacles to improving process efficiency.

[0029] In order to solve the above problems, the embodiments of the present application provide a method and device for preparing a superconducting quantum bit chip. By obtaining the size and pin position information of the superconducting quantum bit chip to be prepared, and obtaining the reference size of the different components required for the superconducting quantum bit chip to be prepared, the size and pin position of the chip can be determined first, thereby limiting the position and size of the different components. Secondly, by determining the reference data corresponding to different components, the embodiments of the present application can draw the design drawings corresponding to different components, and use electromagnetic simulation software to obtain the actual value and the design value error to iterate repeatedly to achieve the design purpose, complete multi-bit wiring, and thus complete the preparation process of the superconducting quantum bit chip, and define the chip preparation process in a unified manner, so that the whole process is clear. Furthermore, in the case where different R&D personnel prepare different components separately, the chip preparation can be completed efficiently in a short time.

[0030] The technical solution proposed in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0031] Figure 1 A flow chart of a method for preparing a superconducting quantum bit chip provided in an embodiment of the present application. Figure 1 As shown, the method for preparing a superconducting quantum bit chip includes the following steps:

[0032] S101. Obtain the size and pin position information of the superconducting quantum bit chip to be prepared, and obtain the reference sizes of different components required for the superconducting quantum bit chip to be prepared.

[0033] In one embodiment of the present application, the present application embodiment provides a design method for a 10-bit superconducting quantum chip, using Klayout layout drawing tool, Electronic Desktop HFSS and Sonnet electromagnetic simulation software to realize the overall design and layout drawing of the 10-bit superconducting quantum chip.

[0034] Specifically, the size of the superconducting quantum chip in the embodiment of the present application is 10.5mm×10.5mm, which is determined by the external connector. The chip needs to be placed in a special holder and fixed in the refrigerator for wiring, and the chip window reserved in this holder is of this size. The reference sizes of the different components required for the superconducting quantum bit chip to be prepared can be determined by empirical values. The reference sizes of the different components of the superconducting quantum bit chip can be saved to a database. When the size of the superconducting quantum chip is obtained, the reference sizes of the different components that match the size of the superconducting quantum chip are searched in the database, so as to perform simulation calibration through the reference sizes of the different components found and the size of the superconducting quantum bit chip obtained.

[0035] Furthermore, different components in the embodiments of the present application are used to realize different functions of the superconducting quantum bit chip to be prepared.

[0036] S102: Based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, determine the reference data corresponding to the different components, wherein the reference data is the data in the design drawings corresponding to the different components.

[0037] In one embodiment of the present application, based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, the reference data of the qubit cross capacitor is determined. The reference data of the transmission line and the readout resonant cavity are determined, the reference data of the Josephson junction is determined, the reference data corresponding to the microwave excitation line and the magnetic flux bias line are determined, and the reference data of the test node and the test resonant cavity are determined.

[0038] Specifically, the design of the 10-bit superconducting quantum bit chip in the embodiment of the present application mainly includes: quantum bit cross capacitor design, readout resonant cavity design, transmission line design, Josephson junction design, microwave excitation line design, flux bias line design, test junction and test resonant cavity design, multi-bit wiring and electromagnetic simulation, etc. First determine the chip size and pin position, determine the reference data of each component through theoretical calculation, draw the design drawings of each component, obtain the error between the actual value and the design value through electromagnetic simulation software, repeatedly iterate to achieve the design purpose, and complete the multi-bit wiring.

[0039] In one embodiment of the present application, reference data of the cross structure inside the quantum bit cross capacitor is determined based on the reference size of the quantum bit cross capacitor obtained, and reference data corresponding to the portion of the quantum bit cross capacitor that needs to be etched away is determined based on the reference size of the quantum bit cross capacitor obtained.

[0040] Specifically, Figure 2 A schematic diagram of a quantum bit cross capacitor design provided for an embodiment of the present application. The small picture on the right is an enlarged view of the bottom part of the cross capacitor. The width of the small cross structure nested in the cross structure is 24μm, and the distance from the outermost side is 24μm. The width of the large cross structure is 404μm and the height is 383μm. There are slightly irregular ridges on both sides of the large cross structure, which serves to increase the coupling capacitance with adjacent bits. The main reason why the embodiment of the present application is designed as a cross is that the four corners are convenient for capacitive coupling with other bits or devices, which facilitates the expansion of the number of bits. In addition, the middle cross structure is a white copy of the metal film left after the outer periphery is etched away. The large cross structure outside the middle cross structure is the interval between the middle cross structure and the peripheral circuit.

[0041] Furthermore, multiple reference data of the quantum bit cross capacitor in the embodiment of the present application can be queried and obtained in the database according to the size of the superconducting quantum chip.

[0042] In one embodiment of the present application, a first reference width of the qubit cross capacitor is determined based on the reference size of the qubit cross capacitor obtained. The qubit cross capacitor is a cross-shaped structure, and the first reference width is the width of any edge of the qubit cross capacitor. And based on the reference size of the qubit cross capacitor obtained, a reference spacing distance between the qubit cross capacitor and the peripheral circuit is determined.

[0043] Specifically, by querying the database, it can be determined that the first reference width corresponding to the small cross structure nested in the cross structure is 24μm, and the reference spacing distance between the quantum bit cross capacitor and the peripheral circuit is 24μm. It should be noted that the embodiment of the present application preferably sets the first reference width to 24μm, and preferably sets the reference spacing distance to 24μm. In application, the reference size of the quantum bit cross capacitor can be determined in the database according to the actual situation and the size of the superconducting quantum bit chip to be prepared.

[0044] Specifically, in one embodiment of the present application, a second reference width corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched is determined. The second reference width is the distance between the left edge and the right edge of the periphery of the quantum bit cross capacitor. And a reference height corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched is determined. The reference height is the distance between the upper side edge and the lower edge of the periphery of the quantum bit cross capacitor.

[0045] Specifically, the second reference width corresponding to the portion of the quantum bit cross capacitor that needs to be etched away is 404μm, and the reference height corresponding to the portion of the quantum bit cross capacitor that needs to be etched away is 383μm. It should be noted that the embodiment of the present application preferably sets the second reference width to 404μm, and preferably sets the reference spacing distance to 383μm. In application, the corresponding reference size can be determined in the database according to the actual situation and the size of the superconducting quantum bit chip to be prepared.

[0046] Further, Figure 2 The large cross structure outside the small and medium cross structures is the etched part, and only the small cross in the middle is left. The large cross structure outside is just the interval between the small cross structure in the middle and the peripheral circuit. The ridges on both sides of the cross structure are to form capacitive coupling with another cross structure next to it. A slight ridge will increase the coupling capacitance value.

[0047] In one embodiment of the present application, the acquired reference dimensions of the transmission line and the readout resonant cavity are compared with the data in the preset database to determine the reference value of the resonant cavity frequency of the readout resonant cavity, and to determine the spacing distance between two adjacent readout resonant cavities. The preset database includes reference dimensions of a variety of different readout resonant cavities, and reference values ​​of the resonant cavity frequencies corresponding to the resonant cavities of the reference dimensions. The readout resonant cavity and the quantum bit cross capacitor are simulated by preset electromagnetic simulation software to obtain the coupling strength between the readout resonant cavity and the quantum bit cross capacitor; and the readout resonant cavity and the transmission line are simulated by preset electromagnetic simulation software to obtain the coupling strength between the readout resonant cavity and the transmission line.

[0048] Specifically, Figure 3 A schematic diagram of a transmission line and a readout resonant cavity design provided in an embodiment of the present application. Figure 3 As shown, the resonant cavity frequencies corresponding to the 10-bit readout resonant cavities are 6.6 GHz to 7.5 GHz, and the interval can be 100 MHz. A certain frequency interval is maintained to prevent read crosstalk. The coupling strength between the readout resonant cavity and the quantum bit and the coupling strength with the transmission line can be obtained through simulation, maintaining a suitable coupling capacitance to ensure readout efficiency, while the coupling is not too strong, so that the quantum bit decoheres quickly.

[0049] In one embodiment of the present application, the length, width and area of ​​the Josephson junction are determined according to the reference size of the Josephson junction obtained. The Josephson junction is prepared by a cross method. The Josephson junction includes two different sizes, the Josephson junctions of different sizes are arranged at intervals, and two adjacent Josephson junctions correspond to different operating frequencies.

[0050] Specifically, Figure 4 A schematic diagram of a Josephson junction design provided in an embodiment of the present application. Figure 4 As shown, the portion marked with number 1 is the Josephson junction electrode, and the portion marked with number 2 is the Josephson junction portion, and the line widths thereof decrease successively. The Josephson junction in the embodiment of the present application is designed using a cross-cross method, and the size of the Josephson junction is 120×120 nm. 2 120×180nm 2 Two sizes, arranged at intervals, because the cross capacitors of the ten bits in the design are exactly the same, the staggered Josephson junction sizes provide different operating frequencies, so that the operating frequencies of adjacent bits are slightly different, preventing crosstalk during control. In addition, the cross-cross method for preparing Josephson junctions has a simpler process and more stable performance.

[0051] In one embodiment of the present application, a coupling capacitor corresponding to the microwave excitation line is determined based on the reference size of the microwave excitation line obtained, so that the microwave excitation line is coupled to the quantum bit through capacitance. The coupling capacitor is used to transmit microwave signals to the quantum bit to change the working state of the quantum bit. Based on the reference size of the magnetic flux bias line obtained, the inductance corresponding to the magnetic flux bias line is determined, and the time magnitude is determined; based on the inductance, time magnitude and magnetic flux bias line, a magnetic flux bias is provided to the quantum bit to change the working frequency of the quantum bit.

[0052] Specifically, the microwave excitation line is coupled to the qubit via capacitance, which is generally in the order of aF (10-18F), and is used to transmit microwave signals to the qubit, changing it from state 0 to state 1. The flux bias line is coupled to the bit via inductance, which is generally multiple picohenries, with a control time in the order of nanoseconds, and is used to provide flux bias to the qubit and change the operating frequency.

[0053] In one embodiment of the present application, multi-bit chip wiring is performed on a superconducting quantum bit chip to be prepared based on actual data, wherein the distance between two adjacent microwave transmission lines is greater than a first preset spacing distance, the distance between two other adjacent transmission lines other than the microwave transmission line is greater than a second preset spacing distance, and the first preset spacing distance is greater than the second preset spacing distance.

[0054] Specifically, in actual use, if the spacing between adjacent transmission lines is too small, signal crosstalk will occur. In the design process of the chip of the embodiment of the present application, in order to ensure that there is no signal interference between different transmission lines, the spacing between every two microwave transmission lines is more than 400μm, and the distance between other two adjacent transmission lines other than microwave transmission lines is set to more than 100μm.

[0055] Figure 5 A schematic diagram of a superconducting quantum bit chip provided in an embodiment of the present application. Figure 5 As shown, there are two lines under each cross structure, of which A is the magnetic flux bias line, B is the microwave excitation line, and the line connected to C is the transmission line. The curved part below the transmission line is 10 resonant cavities, and the other curved part above is 5 test cavities. During use, the bit frequency is adjusted through the magnetic flux bias line, and the bit state (0 to 1) is changed through the microwave excitation line. Information can be transmitted between bits through coupling capacitors, and the current state of the bit can be transmitted through the resonant cavity. The quantum bit state can be read by measuring the cavity frequency offset of the resonant cavity through the transmission line.

[0056] S103, based on the reference image data and the preset electromagnetic simulation software, verify the reference data to obtain the actual data corresponding to different components.

[0057] In one embodiment of the present application, the embodiment of the present application uses the Klayout layout drawing tool, Electronic Desktop HFSS and Sonnet electromagnetic simulation software to verify the reference data to obtain the actual data corresponding to different components, thereby realizing the overall design and layout drawing of the 10-bit superconducting quantum chip.

[0058] S104. Perform multi-bit chip wiring on the superconducting quantum bit chip to be prepared based on actual data to achieve the preparation of the superconducting quantum bit chip.

[0059] In one embodiment of the present application, after the design of each component is completed, multi-bit wiring is performed to ensure the spacing between the lines and prevent control crosstalk. For example, the spacing between every two microwave transmission lines is more than 400μm, and the distance between other two adjacent transmission lines other than the microwave transmission lines is set to more than 100μm. It should be noted that in the embodiment of the present application, the spacing between every two microwave transmission lines is preferably more than 400μm, and the distance between other two adjacent transmission lines other than the microwave transmission lines is preferably set to more than 100μm. During use, it can be adjusted according to actual conditions, and the embodiment of the present application does not limit this.

[0060] Figure 6 A schematic diagram of a superconducting quantum bit chip manufacturing device provided in an embodiment of the present application. Figure 6 As shown, the superconducting quantum bit chip preparation equipment includes:

[0061] at least one processor; and,

[0062] a memory communicatively connected to the at least one processor; wherein,

[0063] The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to:

[0064] Obtaining the size and pin position information of the superconducting qubit chip to be prepared, and obtaining the reference sizes of different components required for the superconducting qubit chip to be prepared; wherein the different components are used to realize different functions of the superconducting qubit chip to be prepared;

[0065] Based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, determining reference data corresponding to the different components respectively; wherein the reference data is data in the design drawings corresponding to the different components respectively;

[0066] Based on the reference data and the preset electromagnetic simulation software, the reference image data is verified to obtain the actual data corresponding to the different components respectively;

[0067] Based on the actual data, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared to achieve the preparation of the superconducting quantum bit chip.

[0068] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0069] The above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0070] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for preparing a superconducting quantum bit chip, It is characterized in that The method comprises: Obtaining the size and pin position information of the superconducting qubit chip to be prepared, and obtaining the reference sizes of different components required for the superconducting qubit chip to be prepared; wherein the different components are used to realize different functions of the superconducting qubit chip to be prepared; Based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, reference data corresponding to the different components are determined by theoretical calculation, and design drawings of the different components are drawn; wherein the reference data are data in the design drawings corresponding to the different components; Based on the reference data and the preset electromagnetic simulation software, the actual value obtained by the electromagnetic simulation software and the design value error are repeatedly iterated to verify the reference data to obtain the actual data corresponding to the different components respectively; Based on the actual data, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared to achieve the preparation of the superconducting quantum bit chip.

2. A method for preparing a superconducting quantum bit chip according to claim 1, It is characterized in that The step of determining reference data corresponding to the different components based on the size and pin position information of the superconducting qubit chip to be prepared and the reference sizes of the different components required for the superconducting qubit chip to be prepared specifically includes: Determining reference data of a quantum bit cross capacitor based on the size and pin position information of the superconducting quantum bit chip to be prepared, and reference sizes of different components required for the superconducting quantum bit chip to be prepared; and determining reference data of the transmission line and the readout resonant cavity; and Determine the reference data of the Josephson junction; and Determining reference data corresponding to the microwave excitation line and the magnetic flux bias line respectively; and Determine the reference data of the test section and the test resonant cavity.

3. A method for preparing a superconducting quantum bit chip according to claim 2, It is characterized in that The reference data for determining the quantum bit cross capacitance specifically includes: Determining reference data of the cross structure inside the qubit cross capacitor according to the obtained reference size of the qubit cross capacitor, and; According to the obtained reference size of the quantum bit cross capacitor, reference data corresponding to the portion of the periphery of the quantum bit cross capacitor that needs to be etched away is determined.

4. A method for preparing a superconducting quantum bit chip according to claim 3, It is characterized in that Determining reference data of the cross structure inside the qubit cross capacitor according to the obtained reference size of the qubit cross capacitor specifically includes: Determining a first reference width of the qubit cross capacitor according to the obtained reference size of the qubit cross capacitor; wherein the qubit cross capacitor is a cross-shaped structure, and the first reference width is the width of any edge of the qubit cross capacitor; and According to the obtained reference size of the quantum bit cross capacitor, a reference spacing distance between the quantum bit cross capacitor and the peripheral circuit is determined.

5. A method for preparing a superconducting quantum bit chip according to claim 3, It is characterized in that Determining reference data corresponding to a portion of the periphery of the quantum bit cross capacitor that needs to be etched away based on the obtained reference size of the quantum bit cross capacitor specifically includes: Determine a second reference width corresponding to a portion of the periphery of the quantum bit cross capacitor that needs to be etched away; wherein the second reference width is the distance between the left edge and the right edge of the periphery of the quantum bit cross capacitor; and Determine a reference height corresponding to a portion of the periphery of the quantum bit cross capacitor that needs to be etched away; wherein the reference height is a vertical distance between an upper edge and a lower edge of the periphery of the quantum bit cross capacitor.

6. A method for preparing a superconducting quantum bit chip according to claim 2, It is characterized in that The step of determining reference data of the transmission line and the readout resonant cavity specifically includes: Comparing the acquired reference dimensions of the transmission line and the readout resonant cavity with the data in a preset database to determine a reference value of the resonant cavity frequency of the readout resonant cavity and a spacing distance between two adjacent readout resonant cavities; wherein the preset database includes reference dimensions of a plurality of different readout resonant cavities and reference values ​​of the resonant cavity frequencies corresponding to resonant cavities of different reference dimensions; By using preset electromagnetic simulation software, the readout resonant cavity and the quantum bit cross capacitor are simulated to obtain the coupling strength between the readout resonant cavity and the quantum bit cross capacitor; and The readout resonant cavity and the transmission line are simulated by using preset electromagnetic simulation software to obtain the coupling strength between the readout resonant cavity and the transmission line.

7. A method for preparing a superconducting quantum bit chip according to claim 2, It is characterized in that The reference data for determining the Josephson junction specifically includes: Determining the length, width and area of ​​the Josephson junction according to the obtained reference size of the Josephson junction; The Josephson junction is prepared by a cross method; The Josephson junctions include two different sizes, and the Josephson junctions of different sizes are arranged at intervals; and two adjacent Josephson junctions correspond to different operating frequencies respectively.

8. A method for preparing a superconducting quantum bit chip according to claim 2, It is characterized in that The determining of the reference data corresponding to the microwave excitation line and the magnetic flux bias line respectively comprises: Determine a coupling capacitor corresponding to the microwave excitation line according to the obtained reference size of the microwave excitation line, so that the microwave excitation line is capacitively coupled to the quantum bit; wherein the coupling capacitor is used to transmit a microwave signal to the quantum bit to change the working state of the quantum bit; According to the reference size of the obtained flux bias line, the inductance corresponding to the flux bias line and the time magnitude are determined; based on the inductance, the time magnitude and the flux bias line, a flux bias is provided to the quantum bit to change the operating frequency of the quantum bit.

9. A method for preparing a superconducting quantum bit chip according to claim 1, It is characterized in that Performing multi-bit chip wiring on the superconducting quantum bit chip to be prepared based on the actual data specifically includes: Based on the actual data, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared; wherein, the distance between two adjacent microwave transmission lines is greater than a first preset spacing distance, the distance between other two adjacent transmission lines except the microwave transmission line is greater than a second preset spacing distance, and the first preset spacing distance is greater than the second preset spacing distance.

10. A superconducting quantum bit chip preparation device, include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to: Obtaining the size and pin position information of the superconducting qubit chip to be prepared, and obtaining the reference sizes of different components required for the superconducting qubit chip to be prepared; wherein the different components are used to realize different functions of the superconducting qubit chip to be prepared; Based on the size and pin position information of the superconducting qubit chip to be prepared, and the reference sizes of different components required for the superconducting qubit chip to be prepared, reference data corresponding to the different components are determined by theoretical calculation, and design drawings of the different components are drawn; wherein the reference data are data in the design drawings corresponding to the different components; Based on the reference data and the preset electromagnetic simulation software, the actual value obtained by the electromagnetic simulation software and the design value error are repeatedly iterated to verify the reference data to obtain the actual data corresponding to the different components respectively; Based on the actual data, multi-bit chip wiring is performed on the superconducting quantum bit chip to be prepared to achieve the preparation of the superconducting quantum bit chip.

Images