Sense amplifier, storage device, and electronic device

Abstract

The present disclosure relates to a sense amplifier, a memory device including the sense amplifier, and an electronic device including the memory device. The sense amplifier includes: a first isolation unit; a second isolation unit; a first offset cancellation unit; a second offset cancellation unit; and a sense amplifier unit including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The sense amplifier further includes at least one of a first equalization unit and a second equalization unit, wherein the first equalization unit is configured to selectively apply a precharge voltage to a bit line, and the second equalization unit is configured to selectively apply a precharge voltage to a complementary bit line. This improves the equalization performance of the bit lines during a precharge operation, thereby increasing the sensing efficiency of the sense amplifier.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to a sense amplifier for sensing and amplifying a bit line of the semiconductor memory device, a memory device including the sense amplifier, and an electronic device including the memory device. Background Art

[0002] Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a memory device in which the data stored is lost when the power is turned off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). A non-volatile memory device is a memory device that retains the data stored therein even when the power is turned off. Non-volatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0004] Some memory devices, such as DRAM, operate by writing and reading data using the charge stored in the cell capacitors of memory cells. In DRAM, the memory cell array is connected by a bit line (BL) and a complementary bit line (BLB). During a read or refresh operation, a sense amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line.

[0005] The semiconductor devices that make up the sense amplifier may have different device characteristics, such as different threshold voltages, due to deviations in factors such as process, voltage, and temperature (PVT). Such different device characteristics may generate offset noise in the sense amplifier. Offset noise can reduce the effective sensing margin of the sense amplifier, thereby reducing the performance of the DRAM. Methods have been proposed in the prior art to improve the effective sensing margin by eliminating the offset of the sense amplifier. However, the sense amplifier in the prior art has limitations in terms of transistor arrangement, which leads to degradation of the equalizing performance of the sense amplifier. Summary of the Invention

[0006] The present disclosure aims to provide a sense amplifier, a memory device including the sense amplifier, and an electronic device including the memory device, wherein the sense amplifier can improve the equalization performance of bit lines in a precharge operation, thereby improving the sensing efficiency of the sense amplifier.

[0007] According to one aspect of the present disclosure, a sense amplifier is provided, comprising: a first isolation unit configured to selectively connect a bit line and a sense bit line; a second isolation unit configured to selectively connect a complementary bit line and a complementary sense bit line; a first offset cancellation unit configured to selectively connect the bit line and the complementary sense bit line; a second offset cancellation unit configured to selectively connect the complementary bit line and the sense bit line; and a sense amplifier unit comprising a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein the first NMOS transistor connects or disconnects the complementary sense bit line in response to a signal of the bit line. The sense amplifier further comprises a first equalization unit and a second equalization unit, wherein the first equalization unit is configured to selectively apply a precharge voltage to the bit line, and the second equalization unit is configured to selectively apply a precharge voltage to the complementary bit line.

[0008] According to another aspect of the present disclosure, a memory device including the aforementioned sense amplifier is provided.

[0009] According to yet another aspect of the present disclosure, an electronic device including the aforementioned storage device is provided.

[0010] It should be understood that the contents described in this section are not intended to represent the key or important purposes, features, and technical effects of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other purposes, features, and technical effects of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings are only used to better understand the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0012] in:

[0013] Figure 1 is a block diagram illustrating an illustrative embodiment of a storage device.

[0014] Figure 2 is used to describe Figure 1Schematic diagram of the sensing operation of the sense amplifier SA on the voltage change of the bit line BL.

[0015] Figure 3 It shows Figure 2 A circuit diagram of an exemplary embodiment of a sense amplifier in FIG.

[0016] Figure 4 It shows Figure 3 FIG. 1 is a timing diagram illustrating the schematic operation of the sense amplifier.

[0017] Figures 5 to 6D Schematic embodiments of layouts of sense amplifiers are shown respectively.

[0018] Figure 7 is a block diagram illustrating an exemplary embodiment in which a memory device including a sense amplifier is applied to an electronic device. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, those skilled in the art will appreciate that the present disclosure may be implemented in other specific forms without changing the technical concept and essential features. Therefore, the embodiments described below should be understood to be merely illustrative and not restrictive.

[0020] As a convention in the field of the present disclosure, one or more components of an embodiment can be described and illustrated according to functional blocks, units and / or modules. These blocks, units and / or modules can be physically implemented by electronic circuits such as logic circuits, microprocessors, hard-wired circuits, etc., and are optionally driven by firmware and / or software. In addition, without departing from the scope of the present disclosure, each functional block, unit and / or module of an embodiment can be physically separated into two or more interactive and discrete blocks, units and / or modules. Moreover, without departing from the scope of the present disclosure, two or more functional blocks, units and / or modules of an embodiment can be physically combined into more complex blocks or units.

[0021] Figure 1 is a block diagram illustrating an illustrative embodiment of a storage device.

[0022] Reference Figure 1The storage device may be a storage device based on a semiconductor device or component. For example, the storage device may be a volatile memory, such as DRAM, SDRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type 2 synchronous dynamic random access memory (DDR2 SDRAM), double data rate type 3 synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as PRAM, MRAM, RRAM, etc.

[0023] The memory device can output data through a data line DQ in response to a command CMD, an address ADDR, and a control signal received from an external device such as a memory controller. The memory device includes a memory cell array 100, a command decoder 800, control logic 700, an address buffer 500, a row decoder 300, a column decoder 400, a sense amplifier component 200, and a data input / output circuit 600.

[0024] The memory cell array 100 includes a plurality of memory cells MC arranged in a matrix of multiple rows and columns. Figure 1 Memory cells MC are exemplarily shown in FIG. The memory cell array 100 includes a plurality of word lines and a plurality of bit lines BL. The plurality of word lines may be connected to a plurality of rows of memory cells MC, respectively, and the plurality of bit lines BL may be connected to a plurality of columns of memory cells MC, respectively.

[0025] The command decoder 800 may decode a write enable signal / WE, a row address select signal / RAS, a column address select signal / CAS, a chip select signal / CS, etc. received from an external device such as a memory controller, and may allow the control logic 700 to generate a control signal corresponding to a command CMD. The command CMD may include an activate command, a read command, a write command, a precharge command, etc.

[0026] The address buffer 500 receives an address ADDR from a memory controller as an external device. The address ADDR includes a row address RA for addressing a row of the memory cell array 100 and a column address CA for addressing a column of the memory cell array 100. The address buffer 500 may transmit the row address RA to the row decoder 300 and the column address CA to the column decoder 400.

[0027] The row decoder 300 may select any one of a plurality of word lines connected to the memory cell array 100. The row decoder 300 may decode the row address RA received from the address buffer 500, select any one word line corresponding to the row address RA, and activate the selected word line.

[0028] The column decoder 400 may select a predetermined number of bit lines BL from a plurality of bit lines BL of the memory cell array 100. The column decoder 400 may decode the column address CA received from the address buffer 500 and select a predetermined number of bit lines BL corresponding to the received column address CA.

[0029] The sense amplifier assembly 200 includes a plurality of sense amplifiers SA. Figure 1 2 , a sense amplifier SA is shown as an example. Each sense amplifier SA can be connected to one bit line BL of the memory cell array 100. The sense amplifier component 200 can sense and amplify voltage changes of the plurality of bit lines BL and output the amplified voltage change on the selected bit line BL. The data input / output circuit 600 can output data through the data line DQ based on the voltage sensed and amplified by the sense amplifier component 200.

[0030] The sense amplifier component 200 may receive control signals such as an isolation control signal ISO, an offset cancellation control signal OC, and a precharge control signal PRE from the control logic 700. The sense amplifier component 200 may perform a precharge operation in response to the precharge control signal PRE. The sense amplifier component 200 may perform an offset cancellation operation in response to the isolation control signal ISO and the offset cancellation control signal OC. For example, the offset represents a characteristic difference between semiconductor devices constituting the sense amplifier component 200, such as a difference between threshold voltages of different semiconductor devices.

[0031] Hereinafter, the configuration and operation of the sense amplifier SA will be described in detail with reference to various embodiments.

[0032] Figure 2 is used to describe Figure 1 Schematic diagram of the sensing operation of the sense amplifier SA on the voltage change of the bit line BL.

[0033] Reference Figure 2, the memory cell MC included in the memory cell array 100 includes a cell transistor 101 and a cell capacitor 102. The memory device can perform a read operation or a refresh operation based on the amount of charge stored in the cell capacitor 102 included in the memory cell. In this case, the bit line BL connected to the memory cell is first precharged to a precharge voltage (Vpre). Then, when the word line WL is activated, a charge sharing operation is performed between the charge of the bit line BL charged to the precharge voltage (Vpre) and the charge of the cell capacitor 102 of the memory cell. Due to the charge sharing operation, the voltage of the bit line BL can be reduced or increased by a voltage change amount (ΔV) from the precharge voltage Vpre. The sense amplifier SA can sense the voltage change amount (ΔV) and amplify it.

[0034] In this case, due to bitline coupling noise (caused by coupling between adjacent bitlines) and the offset noise of the sense amplifier, the effective sensing margin Veffetive of the sense amplifier SA is effectively equal to ΔV - (Vcouple + Voffset), where Vcouple represents bitline coupling noise and Voffset represents offset noise. Therefore, when the voltage change (ΔV) is less than or equal to a predetermined level, the sense amplifier SA may be unable to sense the voltage change (ΔV) of the bitline BL. In other words, the offset noise of the sense amplifier is one of the main factors that reduce the effective sensing margin of the sense amplifier SA.

[0035] To this end, prior art solutions have proposed increasing the effective sensing margin by enhancing the circuit design and corresponding operations for offset cancellation of the sense amplifier. However, these prior art solutions suffer from limitations in the transistor layout of the equalization unit used to perform the precharge operation of the sense amplifier. This results in a longer required row precharge time (tRP), thereby limiting the time available for offset cancellation or increasing the entire sensing operation cycle of the sense amplifier, thereby reducing the overall sensing efficiency of the sense amplifier.

[0036] In view of this, the present disclosure aims to provide an improved sense amplifier, which can at least shorten the row precharge time required in the sensing operation of the sense amplifier.

[0037] Figure 3 is a circuit diagram illustrating an exemplary embodiment of a sense amplifier SA.

[0038] Reference Figure 3 The sense amplifier SA includes first and second equalizing units 251 and 252 , first and second isolation units 241 and 242 , first and second offset cancellation units 231 and 232 , and a sense amplification unit.

[0039] The first equalization unit 251 is configured to selectively apply the precharge voltage VBLP to the bit line BL, and the second equalization unit 252 is configured to selectively apply the precharge voltage VBLP to the complementary bit line BLB.

[0040] The first equalization unit 251 may include a first equalization transistor that applies or does not apply the precharge voltage VBLP to the bit line BL in response to a signal of the first precharge control signal line PRE1. For example, one terminal of the first equalization transistor is connected to the bit line BL, the other terminal thereof is connected to the precharge voltage VBLP, and the gate thereof is connected to the first precharge control signal line PRE1.

[0041] The second equalization unit 252 may include a second equalization transistor that applies or does not apply the precharge voltage VBLP to the complementary bit line BLB in response to a signal of the second precharge control signal line PRE2. For example, one terminal of the second equalization transistor is connected to the complementary bit line BLB, the other terminal thereof is connected to the precharge voltage VBLP, and the gate thereof is connected to the second precharge control signal line PRE2.

[0042] As an alternative embodiment, the sense amplifier SA may also include only one of the first equalizing unit 251 and the second equalizing unit 252 .

[0043] The precharge voltage VBLP may be substantially a half level of the power supply voltage (VCORE).

[0044] In the prior art, transistors in an equalization unit used to perform a precharge operation are typically directly connected to a sense bit line SABL or a complementary sense bit line SABLB, which serves as an internal bit line of a sense amplifier. Consequently, the transistors are relatively far away from the bit line BL and / or the complementary bit line BLB, which reduces precharge performance and results in a longer required tRP. However, in the present disclosure, by at least connecting the equalization unit to the bit line BL and / or the complementary bit line BLB, the equalization unit is positioned relatively close to the bit line BL and / or the complementary bit line BLB, for example, moved outside the sense amplifier. This accelerates precharging of the bit line BL and / or the complementary bit line BLB, thus shortening the required tRP. This not only shortens the overall sensing cycle of the sense amplifier, but also ensures a longer offset cancellation period in the next activation operation, thereby improving offset cancellation performance. This improves the sensing efficiency of the sense amplifier.

[0045] The first isolation unit 241 is configured to selectively connect the bit line BL and the sensing bit line SABL, and the second isolation unit 242 is configured to selectively connect the complementary bit line BLB and the complementary sensing bit line SABLB.

[0046] The first isolation unit 241 may include a first isolation transistor that connects the bit line BL and the sensing bit line SABL or isolates the bit line BL from the sensing bit line SABL in response to a signal of the first isolation control signal line ISO1. For example, one terminal of the first isolation transistor is connected to the bit line BL, the other terminal thereof is connected to the sensing bit line SABL, and the gate thereof is connected to the first isolation control signal line ISO1.

[0047] The second isolation unit 242 may include a second isolation transistor that connects or isolates the complementary bit line BLB and the complementary sensing bit line SABLB in response to a signal of the second isolation control signal line ISO2. For example, one terminal of the second isolation transistor is connected to the complementary bit line BLB, the other terminal thereof is connected to the complementary sensing bit line SABLB, and the gate thereof is connected to the second isolation control signal line ISO2.

[0048] The first offset cancellation unit 231 is configured to selectively connect the bit line BL and the complementary sensing bit line SABLB, and the second offset cancellation unit 232 is configured to selectively connect the complementary bit line BLB and the sensing bit line SABL.

[0049] The first offset cancellation unit 231 may include a first offset cancellation transistor that connects or disconnects the bit line BL and the complementary sensing bit line SABLB in response to a signal from the first offset cancellation control signal line OC1. For example, one terminal of the first offset cancellation transistor is connected to the bit line BL, the other terminal is connected to the complementary sensing bit line SABLB, and the gate is connected to the first offset cancellation control signal line OC1.

[0050] The second offset cancellation unit 232 may include a second offset cancellation transistor that connects or disconnects the complementary bit line BLB and the sensing bit line SABL in response to a signal from the second offset cancellation control signal line OC2. For example, one terminal of the second offset cancellation transistor is connected to the complementary bit line BLB, the other terminal is connected to the sensing bit line SABL, and the gate is connected to the second offset cancellation control signal line OC2.

[0051] The sense amplification unit senses and amplifies a voltage difference between the bit line BL and the complementary bit line BLB in response to a sense driving signal.

[0052] The sense amplifier unit may include a pair of N-type metal oxide semiconductor (NMOS) transistors (ie, first NMOS transistor 211 and second NMOS transistor 212 ) and a pair of P-type metal oxide semiconductor (PMOS) transistors (ie, first PMOS transistor 221 and second PMOS transistor 222 ).

[0053] One terminal of the first NMOS transistor 211 is connected to the complementary sensing bit line SABLB, the other terminal thereof is connected to the first sensing drive signal line SB1, and the gate thereof is connected to the bit line BL. One terminal of the second NMOS transistor 212 is connected to the sensing bit line SABL, the other terminal thereof is connected to the second sensing drive signal line SB2, and the gate thereof is connected to the complementary bit line BLB.

[0054] One terminal of the first PMOS transistor 221 is connected to the complementary sensing bit line SABLB, the other terminal thereof is connected to the third sensing drive signal line RTO1, and the gate thereof is connected to the sensing bit line SABL. One terminal of the second PMOS transistor 221 is connected to the sensing bit line SABL, the other terminal thereof is connected to the fourth sensing drive signal line RTO2, and the gate thereof is connected to the complementary sensing bit line SABLB.

[0055] The bit line BL may be connected to the cell transistor 101 (see FIG. Figure 2 ) terminal.

[0056] A first data input and output unit 261 may be connected to the bit line BL, and a second data input and output unit 262 may be connected to the complementary bit line BLB. The first data input and output unit 261 and the second data input and output unit 262 may constitute Figure 1 at least a portion of the data input-output circuit 600 .

[0057] The first data input-output unit 261 selectively connects the bit line BL and the data input-output line IO, and the second data input-output unit 262 selectively connects the complementary bit line BLB and the complementary data input-output line IOB.

[0058] The first data input-output unit 261 may include a first column selection transistor that connects or disconnects the bit line BL and the data input-output line 10 in response to a signal of the first column selection signal line CSL1. One terminal of the first column selection transistor is connected to the bit line BL, the other terminal thereof is connected to the data input-output line 10, and a gate thereof is connected to the first column selection signal line CSL1.

[0059] The second data input-output unit 262 may include a second column selection transistor that connects or disconnects the complementary bit line BLB and the complementary data input-output line 10B in response to a signal of the second column selection signal line CSL2. One terminal of the second column selection transistor is connected to the complementary bit line BLB, the other terminal thereof is connected to the complementary data input-output line 10B, and the gate thereof is connected to the second column selection signal line CSL2.

[0060] Figure 4 It shows Figure 3Schematic operation timing diagram of the sense amplifier SA in FIG. Figure 4 The X-axis represents time, and the Y-axis represents signal level.

[0061] Reference Figure 4 , the sense amplifier SA sequentially performs a precharge operation, an offset cancellation operation, a charge sharing operation, and a restore operation.

[0062] During a first interval before t0, the sense amplifier SA performs a precharge operation. The sense amplifier SA precharges the bit line BL, the complementary bit line BLB, the sense bit line SABL, and the complementary sense bit line SABLB to a precharge voltage VBLP. For example, the precharge control signal PRE (applied to the first and second precharge control signal lines PRE1 and PRE2) is logic high (H), the isolation control signal ISO (applied to the first and second isolation control signal lines ISO1 and ISO2) is logic low (L), and the offset cancellation control signal OC (the first and second offset cancellation control signal lines OC1 and OC2) is logic high (H). In response, the first and second equalization transistors 251 and 252 are turned on, the first and second isolation transistors 241 and 242 are turned off, and the first and second offset cancellation transistors 231 and 232 are turned on, thereby precharging the bit line BL, the complementary bit line BLB, the sense bit line SABL, and the complementary sense bit line SABLB to the precharge voltage VBLP. At this time, the sensing driving signal SB (applied to the first and second sensing driving signal lines SB1 and SB2 ) and the sensing driving signal RTO (the third and fourth sensing driving signals RTO1 and RTO2 ) may also be precharged to the precharge voltage VBLP.

[0063] During the second interval from t0 to t1, the sense amplifier SA performs an offset cancellation operation. For example, the isolation control signal ISO remains at a logic low (L), and the offset cancellation control signal OC remains at a logic high (H). This means that the first and second isolation transistors 241 and 242 remain off, and the first and second offset cancellation transistors 231 and 232 remain on. At this time, the precharge control signal PRE becomes logic low (L), meaning that the first and second equalization transistors 251 and 252 are off. Furthermore, the sense drive signal RTO rises from the precharge voltage VBLP to the internal power supply voltage (VCORE), while the sense drive signal SB falls from the precharge voltage VBLP to the ground voltage (VSS). The internal power supply voltage (VCORE) may be the voltage supplied to the memory cell array 100. Subsequently, both sense drive signals RTO and SB return to the precharge voltage VBLP. Consequently, a voltage difference corresponding to the offset noise exists between the bit line BL and the complementary bit line BLB. This means that the offset noise of the sense amplifier 150 is removed, meaning that the offset of the sense amplifier 150 is compensated.

[0064] During the third interval from t1 to t2, the sense amplifier SA performs a charge sharing operation. For example, first, the isolation control signal ISO remains at a logic low (L), and the offset cancellation control signal OC becomes a logic low (L). In response, the first and second isolation transistors 241 and 242 remain off, and the first and second offset cancellation transistors 231 and 232 become off. At this time, the word line WL connected to the memory cell MC becomes a logic high (H), that is, it is activated, and a charge sharing operation is performed between the charge stored in the cell capacitor 102 of the memory cell MC and the charge stored in the bit line BL. When data with a value of "1" is stored in the memory cell MC, the voltage level of the bit line BL increases by a predetermined level during the charge sharing operation. In another embodiment, when data with a value of "0" is stored in the memory cell MC, the voltage level of the bit line BL decreases by a predetermined level during the charge sharing operation. Subsequently, the isolation control signal ISO becomes logic high (H) at a specified time between t1 and t2. In response, the first and second isolation transistors 241 and 242 become conductive at the specified time between t1 and t2. That is, the bit line BL and the sensing bit line SABL are connected to each other, and the complementary bit line BLB and the complementary sensing bit line SABLB are connected to each other. Therefore, the voltage level of the sensing bit line SABL also increases or decreases accordingly.

[0065] During the fourth interval, from t2 to t3, the sense amplifier SA performs a restore operation. At this time, the sense drive signal RTO transitions to the internal power supply voltage VCORE, and the second sense drive signal SB transitions to the ground voltage VSS. Therefore, in the sense amplifier SA, based on the voltage difference between the bit line BL and the complementary bit line BLB, when data with a value of "1" is stored in the memory cell MC, the sense bit line SABL rises to the internal power supply voltage VCORE, and the complementary sense bit line SABLB falls to the ground voltage VSS. However, when data with a value of "0" is stored in the memory cell MC, the sense bit line SABL falls to the ground voltage VSS, and the complementary sense bit line SABLB rises to the internal power supply voltage VCORE. Simultaneously, the bit line BL connected to the sense bit line SABL is charged or discharged to the voltage level of the sense bit line SABL, and the complementary bit line BLB connected to the complementary sense bit line SABLB is also charged or discharged to the voltage level of the complementary sense bit line SABLB. At this point, the cell capacitor 102 of the memory cell MC connected to the bit line BL will be restored to the previously stored charge, that is, the corresponding data "1" or "0". At the same time, the first and second data input and output units 261 and 262 can output the amplified voltage levels on the bit line BL and the complementary bit line BLB to the data input and output line IO and the complementary data input and output line IOB in response to the signals of the first and second column select signal lines CSL1 and CSL2, respectively.

[0066] In a fifth interval after t3, the precharge control signal PRE becomes logic high (H), the isolation control signal ISO becomes logic low (L), and the offset cancellation control signal OC becomes logic high (H). In response, the first and second equalization transistors 251 and 252 are turned on, the first and second isolation transistors 241 and 242 are turned off, and the first and second offset cancellation transistors 231 and 232 are turned on, thereby precharging the bit line BL, the complementary bit line BLB, the sensing bit line SABL, and the complementary sensing bit line SABLB to the precharge voltage VBLP.

[0067] Figures 5 to 6D Schematic embodiments of the layout of the sense amplifier SA are shown respectively. Figures 5 to 6D 2 shows an exemplary layout of only a partial area of ​​the sense amplifier component 200, namely, a layout of four sense amplifiers SA_0 to SA_3, wherein two sense amplifiers are arranged along the extending direction of the bit line BL and / or the complementary bit line BLB and in a direction perpendicular thereto. Each sense amplifier SA may have the following configuration: Figure 3 The structure shown in the figure, for example, is provided with a first balancing unit 251 and / or a second balancing unit 252, a first isolation unit 241 and a second isolation unit 242, a first offset cancellation unit 231 and a second offset cancellation unit 232, and a sense amplifier unit, wherein the sense amplifier unit is composed of a first NMOS transistor 211 and a second NMOS transistor 212 and a first PMOS transistor 221 and a second PMOS transistor 222. In addition, Figures 5 to 6D A first data input-output unit 261 and a second data input-output unit 262 are also exemplarily shown in the figure to facilitate description of different layouts of the sense amplifier SA below.

[0068] Reference Figure 5 Sense amplifiers SA_0 through SA_3 are connected to their respective bit line pairs (i.e., BL0 / BLB0, BL1 / BLB1, BL2 / BLB2, and BL3 / BLB3). Sense amplifiers SA_0 and SA_1 are arranged adjacent to each other along the direction in which bit lines BL and / or complementary bit lines BLB extend. Sense amplifiers SA_2 and SA_3 are arranged adjacent to each other along the direction in which bit lines BL and / or complementary bit lines BLB extend. Sense amplifiers SA_0 and SA_2 are closer to bit lines BL (or farther from complementary bit lines BLB) than sense amplifiers SA_1 and SA_3. Since the layout of sense amplifiers SA_0 and SA_1 (at least along the direction in which bit lines BL and / or complementary bit lines BLB extend) is essentially the same as that of sense amplifiers SA_2 and SA_3, only the layout of sense amplifiers SA_0 and SA_1 will be described in detail below.

[0069] In the sense amplifier SA_0, a first NMOS transistor 211_0, a first offset cancellation unit 231_0, a first isolation unit 241_0, a first PMOS transistor 221_0, a second PMOS transistor 222_0, a second isolation unit 242_0, a second offset cancellation unit 232_0, and a second NMOS transistor 212_0 are sequentially arranged adjacent to each other in a direction away from the bit line BL0 (i.e., away from the memory cell MC connected to the bit line BL0 or toward the sense amplifier SA_1). In the sense amplifier SA_1, a first NMOS transistor 211_1, a first offset cancellation unit 231_1, a first isolation unit 241_1, a first PMOS transistor 221_1, a second PMOS transistor 222_1, a second isolation unit 242_1, a second offset cancellation unit 232_1, and a second NMOS transistor 212_1 are sequentially arranged adjacent to each other in a direction away from the bit line BL1 (i.e., away from the memory cell MC connected to the bit line BL1 or away from the sense amplifier SA_0).

[0070] As an alternative embodiment, in the readout amplifier SA_1, a first NMOS transistor 211_1, a first offset elimination unit 231_1, a first isolation unit 241_1, a first PMOS transistor 221_1, a second PMOS transistor 222_1, a second isolation unit 242_1, a second offset elimination unit 232_1 and a second NMOS transistor 212_1 can be arranged adjacent to each other in sequence along a direction close to the bit line BL (i.e., a direction close to the memory cell MC connected to the bit line BL1 or the readout amplifier SA_0).

[0071] As an alternative embodiment, in at least one of the sense amplifier SA_0 and the sense amplifier SA_1 , the positions of the first offset cancellation unit and the first isolation unit may be swapped; and / or the positions of the second isolation unit and the second offset cancellation unit may be swapped.

[0072] As an alternative embodiment, in at least one of the sense amplifier SA_0 and the sense amplifier SA_1 , positions of the first PMOS transistor and the second PMOS transistor may be swapped with each other.

[0073] As an alternative embodiment, in at least one of the sense amplifier SA_0 and the sense amplifier SA_1 , the first NMOS transistor and the first PMOS transistor, and the second NMOS transistor and the second PMOS transistor may be swapped with each other.

[0074] The first equalizing units 251_0 and 251_1 of the sense amplifiers SA_0 and SA_1 are arranged on a side of the first NMOS transistor 211_0 of the sense amplifier SA_0 that is close to the bit line BL0 (or on a side that is away from the sense amplifier SA_1). For example, the first equalizing unit 251_0 and the first equalizing unit 251_1 can be arranged adjacent to each other in a direction close to or away from the bit line BL0.

[0075] Second equalizing units 252_0 and 252_1 of sense amplifiers SA_0 and SA_1 are arranged on a side of second NMOS transistor 212_1 of sense amplifier SA_1 that is away from bit line BL (or away from sense amplifier SA_0). For example, second equalizing units 252_0 and 252_1 may be arranged adjacent to each other in a direction toward or away from bit line BL0.

[0076] On the side of the first equalizer units 251_0 and 251_1 close to the bit line BL (or away from the sense amplifier SA_1), first data input / output units 261_0 and 261_1 are arranged, connected to the sense amplifiers SA_0 and SA_1 (or the bit lines BL0 and BL1), respectively. On the side of the second equalizer units 252_0 and 252_1 away from the bit line BL (or away from the sense amplifier SA_0), second data input / output units 262_0 and 262_1 are arranged, connected to the sense amplifiers SA_0 and SA_1 (or the complementary bit lines BLB0 and BLB1), respectively.

[0077] Considering only the layout of the device itself without considering circuit connections, the sense amplifier SA_0 and the sense amplifier SA_1 are substantially mirror-symmetric to each other (eg, with respect to an axis perpendicular to the direction in which the bit line BL extends).

[0078] As an alternative embodiment, the positions of the first equalizing units 251_0 and 251_1 and the first data input and output units 261_0 and 261_1 may be swapped, and the positions of the second equalizing units 252_0 and 252_1 and the second data input and output units 262_0 and 262_1 may be swapped.

[0079] The first equalizing units 251_0 and 251_1 can each employ a first equalizing transistor, each comprised of an active pattern 2511 and a gate pattern 2512. For example, one side of the active pattern 2511 can be electrically connected to the respective bit line BL, while the other side (e.g., the side connected to or shared with the active pattern 2511 of another first equalizing transistor) can be applied with a precharge voltage VBLP, and the gate pattern 2512 can be connected to the first precharge signal line PRE1. The second equalizing units 252_0 and 252_1 can each employ a second equalizing transistor, each comprised of an active pattern 2521 and a gate pattern 2522. For example, one side of the active pattern 2521 can be electrically connected to the respective complementary bit line BLB, while the other side (e.g., the side connected to or shared with the active pattern 2521 of another second equalizing transistor) can be applied with a precharge voltage VBLP, and the gate pattern 2522 can be connected to the second precharge signal line PRE2.

[0080] The first PMOS transistors 221_0 and 221_1 may each include an active pattern 2211 and a gate pattern 2212, and the second PMOS transistors 222_0 and 222_1 may each include an active pattern 2221 and a gate pattern 2222. The first NMOS transistors 211_0 and 211_1 may each include an active pattern 2111 and a gate pattern 2112, and the second NMOS transistors 212_0 and 212_1 may each include an active pattern 2121 and a gate pattern 2122.

[0081] The first offset cancellation units 231_0 and 231_1 can each employ a first offset cancellation transistor. The first isolation units 241_0 and 241_1 can each employ a first isolation transistor. The first offset cancellation transistor and the first isolation transistor can share a common active pattern 2311 and have respective gate patterns 2312 and 2412, respectively. The second offset cancellation units 232_0 and 232_1 can each employ a second offset cancellation transistor. The second isolation units 242_0 and 242_1 can each employ a second isolation transistor. The second offset cancellation transistor and the second isolation transistor can share a common active pattern 2321 and have respective gate patterns 2322 and 2422, respectively. The gate patterns 2312 and 2322 are connected to the first offset cancellation control signal line OC1 and the second offset cancellation control signal line OC2, respectively. The gate patterns 2412 and 2422 are connected to the first isolation control signal line ISO1 and the first isolation control signal line ISO2, respectively.

[0082] As an alternative embodiment, Figure 6A As shown, Figure 5Compared to the layout embodiment of the sense amplifier of FIG, the only difference is that the first equalizing units 251_0, 251_1 and the second equalizing units 252_0, 252_1 of the sense amplifiers SA_0, SA_1 are arranged between the second NMOS transistor 212_0 of the sense amplifier SA_0 and the first NMOS transistor 211_1 of the sense amplifier SA_1. For example, the first equalizing units 251_0, 251_1 and the second equalizing units 252_0, 252_1 can be arranged sequentially between the second NMOS transistor 212_0 and the first NMOS transistor 211_1, in a direction approaching or away from the bit line BL.

[0083] As an alternative embodiment, Figure 6B As shown, Figure 5 Compared with the layout embodiment of the sense amplifier, the only difference is that the sense amplifier SA_0 has only the first balancing unit 251_0 but not the second balancing unit 252_0, and the sense amplifier SA_1 has only the second balancing unit 252_1 but not the first balancing unit 251_1.

[0084] As an alternative embodiment, Figure 6C As shown, Figure 6A Compared with the layout embodiment of the sense amplifier, the only difference is that the sense amplifier SA_0 has only the second balancing unit 252_0 but not the first balancing unit 251_0, and the sense amplifier SA_1 has only the first balancing unit 251_1 but not the second balancing unit 252_1.

[0085] As an alternative embodiment, Figure 6D As shown, Figure 5 Compared with the layout embodiment of the sense amplifier, the only difference is that the second equalizing unit 252_0 of the sense amplifier SA_0 and the first equalizing unit 251_1 of SA_1 are arranged between the second NMOS transistor 212_0 of the sense amplifier SA_0 and the first NMOS transistor 211_1 of the sense amplifier SA_1.

[0086] Figure 7 1 is a block diagram illustrating an example embodiment in which a memory device including a sense amplifier as described herein is applied to an electronic device. The electronic device may be a mobile device, such as a mobile phone or a smart phone.

[0087] Reference Figure 7 , the mobile device 70 includes a Global System for Mobile Communications (GSM) block 710 , a Near Field Communication (NFC) transceiver 720 , an input and output block 730 , an application block 740 , a memory 750 , and a display 760 . Figure 7The components or blocks of the mobile device 70 in FIG. 7 are shown as examples. The mobile device 70 may include more or fewer components or blocks. In addition, although components or blocks using GSM technology are shown in the current embodiment, the mobile device 70 may be implemented using other technologies such as code division multiple access (CDMA). It may be implemented in the form of an integrated circuit. Figure 7 Alternatively, while some blocks may be implemented in the form of integrated circuits, other blocks may be implemented in separate forms.

[0088] The GSM block 710 may be connected to an antenna 711 and may operate in a known manner to provide radiotelephone operation. The GSM block 710 may include a receiver and a transmitter therein and perform corresponding receive and transmit operations.

[0089] The NFC transceiver 720 may be configured to transmit and receive NFC signals using inductive coupling for wireless communication. The NFC transceiver 720 may provide the NFC signal to the NFC antenna matching network system (NFC AMNS) 721, and the NFC antenna matching network system 721 may transmit the NFC signal using inductive coupling. The NFC antenna matching network system 721 may receive an NFC signal provided from another NFC device and provide the received NFC signal to the NFC transceiver 720.

[0090] The application block 740 may include hardware circuits such as one or more processors and may operate to provide various user applications provided by the mobile device 70. User applications may include voice call operations, data transmission, data exchange, etc. The application block 740 may operate in conjunction with the GSM block 710 and / or the NFC transceiver 720 and provide the operating characteristics of the GSM block 710 and / or the NFC transceiver 720. Alternatively, the application block 740 may include a program for a mobile point of sale (POS). Such a program may provide credit card purchase and payment functionality using a mobile phone (e.g., a smartphone).

[0091] The display 760 may display an image in response to a display signal received from the application block 740. The image may be provided from the application block 740 or may be generated by a camera embedded in the mobile device 70. The display 760 may include a frame buffer therein for temporarily storing pixel values ​​and may be constructed as a liquid crystal display screen with associated control circuitry.

[0092] The input and output block 730 provides input functionality to the user and provides output to be received by the application block 740 .

[0093] The memory 750 may store programs (instructions) and / or data to be used by the application block 740 and may be implemented as a random access memory (RAM), a read-only memory (ROM), a flash memory, etc. Therefore, the memory 750 may include a non-volatile memory device as well as a volatile memory device. For example, the memory 750 may correspond to Figure 1 The memory 750 may include a memory device based on the combination of Figures 2 to 6D The sense amplifier of the aforementioned embodiment is described.

[0094] While the disclosed concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A sense amplifier for a memory device, comprising: a first isolation unit configured to selectively connect the bit line and the sensing bit line; a second isolation unit configured to selectively connect the complementary bit line and the complementary sensing bit line; a first offset cancellation unit configured to selectively connect the bit line and the complementary sensing bit line; a second offset cancellation unit configured to selectively connect the complementary bit line and the sensing bit line; as well as a sense amplifier unit including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein the first NMOS transistor connects or disconnects the complementary sensing bit line and the first sensing drive signal line in response to a signal of the bit line, the second NMOS transistor connects or disconnects the sensing bit line and the second sensing drive signal line in response to a signal of the complementary bit line, the first PMOS transistor connects or disconnects the complementary sensing bit line and the third sensing drive signal line in response to a signal of the sensing bit line, and the second PMOS transistor connects or disconnects the sensing bit line and the fourth sensing drive signal line in response to a signal of the complementary sensing bit line, The sense amplifier further includes at least one of a first equalization unit and a second equalization unit, wherein the first equalization unit is connected to the bit line and the second equalization unit is connected to the complementary bit line, the first equalization unit is configured to selectively apply a precharge voltage to the bit line, and the second equalization unit is configured to selectively apply the precharge voltage to the complementary bit line.

2. The sense amplifier according to claim 1 , wherein the first balancing unit comprises a first balancing transistor, one end of which is connected to the precharge voltage, the other end of which is connected to the bit line, and the gate of which receives a precharge control signal; and the second balancing unit comprises a second balancing transistor, one end of which is connected to the precharge voltage, the other end of which is connected to the complementary bit line, and the gate of which receives the precharge control signal.

3. The sense amplifier according to claim 1 , wherein the first isolation unit includes a first isolation transistor that connects or disconnects the bit line and the sensing bit line in response to an isolation control signal; the second isolation unit includes a second isolation transistor that connects or disconnects the complementary bit line and the complementary sensing bit line in response to the isolation control signal; the first offset cancellation unit includes a first offset cancellation transistor that connects or disconnects the bit line and the complementary sensing bit line in response to the offset cancellation control signal; and the second offset cancellation unit includes a second offset cancellation transistor that connects or disconnects the complementary bit line and the sensing bit line in response to the offset cancellation control signal.

4. A storage device comprising: a memory cell array comprising a plurality of bit lines, a plurality of complementary bit lines, and a plurality of memory cells, each memory cell being connected to one bit line or one complementary bit line; a data input-output circuit comprising a plurality of first data input-output units respectively connected to the plurality of bit lines and a plurality of second data input-output units respectively connected to the plurality of complementary bit lines; as well as The plurality of sense amplifiers according to claim 1, comprising a first sense amplifier and a second sense amplifier arranged adjacent to each other along an extending direction of the bit line, the first sense amplifier being closer to the bit line than the second sense amplifier. The first sense amplifier and the second sense amplifier include a first component and a second component, respectively. The first component and the second component are respectively composed of a first NMOS transistor, a second NMOS transistor, a first offset cancellation unit, a second offset cancellation unit, a first isolation unit, a second isolation unit, a first PMOS transistor, and a second PMOS transistor. Two first data input / output units respectively connected to the first sense amplifier and the second sense amplifier are arranged on a side of the first component away from the second component, and two second data input / output units respectively connected to the first sense amplifier and the second sense amplifier are arranged on a side of the second component away from the first component. wherein the first NMOS transistor, the second NMOS transistor, the first offset cancellation unit, the second offset cancellation unit, the first isolation unit, the second isolation unit, the first PMOS transistor, and the second PMOS transistor in the first component and the second component are arranged identically or mirror-symmetrically along the extending direction of the bit line; wherein in each of the first component and the second component, a first NMOS transistor and a second NMOS transistor are arranged at opposite ends, and a first PMOS transistor and a second PMOS transistor are arranged in a middle region between the first NMOS transistor and the second NMOS transistor; In the first component, the first NMOS transistor is arranged at one end close to the bit line; in the second component, the first NMOS transistor is arranged at one end close to or far from the bit line.

5. A storage device according to claim 4, wherein each of the first sense amplifier and the second sense amplifier includes a first equalization unit and a second equalization unit, the two first equalization units of the first sense amplifier and the second sense amplifier are both arranged between the two first data input-output units and the first component, and the two second equalization units of the first sense amplifier and the second sense amplifier are both arranged between the two second data input-output units and the second component.

6. The storage device according to claim 4, wherein each of the first sense amplifier and the second sense amplifier includes a first equalization unit and a second equalization unit, the two first equalization units of the first sense amplifier and the second sense amplifier are both arranged on a side of the two first data input-output units away from the first component, and the two second equalization units of the first sense amplifier and the second sense amplifier are both arranged on a side of the two second data input-output units away from the second component.

7. The storage device according to claim 4, wherein each of the first sense amplifier and the second sense amplifier includes a first equalization unit and a second equalization unit, and the two first equalization units and the two second equalization units of the first sense amplifier and the second sense amplifier are each arranged between the first component and the second component.

8. A storage device according to claim 4, wherein each of the first sense amplifier and the second sense amplifier includes a first equalization unit and a second equalization unit, the first equalization unit of the first sense amplifier is arranged between the two first data input-output units and the first component, the second equalization unit of the second sense amplifier is arranged between the two second data input-output units and the second component, and the second equalization unit of the first sense amplifier and the first equalization unit of the second sense amplifier are both arranged between the first component and the second component.

9. The storage device according to claim 4, wherein each of the first sense amplifier and the second sense amplifier includes a first equalizing unit and a second equalizing unit, the first equalizing unit of the first sense amplifier is arranged on a side of the two first data input-output units away from the first component, the second equalizing unit of the second sense amplifier is arranged on a side of the two second data input-output units away from the second component, and the second equalizing unit of the first sense amplifier and the first equalizing unit of the second sense amplifier are both arranged between the first component and the second component.

10. The storage device according to claim 4, wherein the first sense amplifier includes a first equalizing unit, the second sense amplifier includes a second equalizing unit, the first equalizing unit of the first sense amplifier is arranged between the two first data input-output units and the first component, and the second equalizing unit of the second sense amplifier is arranged on a side of the two second data input-output units away from the second component.

11. The memory device according to claim 4, wherein the first sense amplifier includes a second equalizing unit, the second sense amplifier includes a first equalizing unit, and the second equalizing unit of the first sense amplifier and the first equalizing unit of the second sense amplifier are both arranged between the first component and the second component.

12. An electronic device comprising the storage device according to claim 4.

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