Multilayer ceramic capacitors with ultra-wideband performance

Abstract

A multilayer ceramic capacitor is disclosed, comprising a first external terminal disposed along a first end of the capacitor, a second external terminal disposed along a second end of the capacitor opposite the first end, an active electrode region comprising alternating dielectric layers and active electrode layers, and a shield electrode region comprising at least two shield electrodes, the at least two shield electrodes being separated in a longitudinal direction by a shield layer gap. The distance from the active electrode region to the shield electrode region may range from about 4% to about 20% of the thickness of the capacitor between a top surface and a bottom surface opposite the top surface. On at least one of the top surface or the bottom surface, the shield layer gap may range from about 3% to about 60% of the external terminal gap between the first external terminal and the second external terminal in the longitudinal direction.

Description

[0001] This application is a divisional application of the invention patent application with application number 201980016585.7, application date March 5, 2019, and invention name “Multilayer ceramic capacitor with ultra-wideband performance”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 639,236, filed on March 6, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0004] The diversity of modern technology applications has created a demand for efficient electronic components and integrated circuits used therein. Capacitors are essential components for filtering, coupling, bypassing, and other aspects of such modern applications, which can include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. The significant increase in speed and packaging density of integrated circuits has particularly necessitated advances in coupling capacitor technology. Performance characteristics become increasingly important when high capacitance coupling capacitors are subjected to the high frequencies of many current applications. Since capacitors are fundamental to such a wide range of applications, their precision and efficiency are critical. Therefore, many specific aspects of capacitor design have become the focus of improving their performance characteristics.

[0005] While the prior art has provided various configurations for capacitors to allow for improved performance, it would be advantageous to provide capacitors with similar or improved results, particularly in broadband applications. Summary of the invention

[0006] According to one embodiment of the present invention, a multilayer ceramic capacitor is disclosed. The capacitor may include a first external terminal arranged along a first end of the capacitor, a second external terminal arranged along a second end of the capacitor opposite to the first end in a longitudinal direction, an active electrode region including alternating dielectric layers and active electrode layers, and a shielding electrode region. The shielding electrode region may include at least two shielding electrodes, and the at least two shielding electrodes are separated by a shielding layer gap in the longitudinal direction. The distance from the active electrode region to the shielding electrode region may be about 4% to about 20% of the thickness of the capacitor between the top surface and the bottom surface opposite to the top surface. On at least one of the top surface or the bottom surface, the shielding layer gap may range from about 3% to about 60% of the external terminal gap between the first external terminal and the second external terminal in the longitudinal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The remainder of the specification, including with reference to the accompanying drawings, more particularly sets forth a full and enabling disclosure of the present invention, including the best mode to one skilled in the art, in which:

[0008] Figure 1A and 1C shows a top view of an electrode layer according to an embodiment of the present invention;

[0009] Figure 1B A perspective view showing alternating electrode layers of one embodiment of the present invention;

[0010] Figure 1D A side cross-sectional view of one embodiment of a capacitor of the present invention is shown;

[0011] Figure 2 A top view of an embodiment of an electrode layer of the present invention is shown;

[0012] Figure 3A A side cross-sectional view of one embodiment of a capacitor of the present invention is shown;

[0013] Figure 3B An embodiment of the present invention is shown. Figure 3A A top view of an electrode of a capacitor;

[0014] Figure 4A A side cross-sectional view of one embodiment of a capacitor of the present invention is shown;

[0015] Figure 4B An embodiment of the present invention is shown. Figure 4A A top view of an electrode of a capacitor;

[0016] Figures 5A-5C shows a top view of an anchor electrode according to some embodiments of the present invention;

[0017] Figures 6A-6D A top view showing an electrode layer according to some embodiments of the present invention; and Figure 7A-7B A schematic diagram of a circuit having a capacitive region is depicted;

[0018] Figures 8A-8C Top views of various embodiments of the electrode layer of the present invention are shown. DETAILED DESCRIPTION

[0019] Those skilled in the art will appreciate that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention.

[0020] In general, the present invention relates to a multilayer ceramic capacitor. In particular, the present invention relates to a multilayer ceramic capacitor comprising an active electrode region comprising alternating dielectric layers and electrode layers, and a shielding electrode region comprising at least one shielding electrode. The multilayer ceramic capacitor also includes a top surface and a bottom surface opposite the top surface. The inventors have discovered that by controlling the distance between the active electrode region and the shielding region and / or the distance between the active electrode region and the top surface of the capacitor, various advantages are provided.

[0021] In general, the distance between the active electrode region and the shielding region is about 1.0 mil or more, such as about 1.3 mil or more, such as about 1.5 mil or more, such as about 1.7 mil or more, such as about 1.9 mil or more to about 2.5 mil or less, such as about 2.3 mil or less, such as about 2.1 mil or less. For example, the distance between the active electrode region and the shielding region is from about 1.0 mil to about 2.5 mil, such as from about 1.3 mil to about 2.3 mil, such as from about 1.5 mil to about 2.1 mil, such as from about 1.7 mil to about 2.3 mil, such as from about 1.9 mil to about 2.1 mil. Such a distance can be about 4% or more of the thickness of the capacitor, such as about 5% or more, such as about 6% or more, such as about 7% or more to about 20% or less, such as about 18% or less, such as about 15% or less, such as about 13% or less, such as about 11% or less.

[0022] In general, the distance between the active electrode area and the top surface of the capacitor is about 1.5 mils or more, such as about 1.8 mils or more, such as about 2.0 mils or more, such as about 2.1 mils or more, such as about 2.3 mils or more, such as about 2.5 mils or more to about 3.2 mils or less, such as about 3.0 mils or less, such as about 2.9 mils or less, such as about 2.8 mils or less. For example, the distance between the active electrode area and the top surface of the capacitor is from about 1.8 mils to about 3.2 mils, such as from about 2.0 mils to about 3.0 mils, such as from about 2.3 mils to about 3.0 mils, such as from about 2.5 mils to about 2.9 mils. Such a distance can be about 5% or more of the thickness of the capacitor, such as about 8% or more, such as about 9% or more, such as about 10% or more to about 25% or less, such as about 20% or less, such as about 18% or less, such as about 15% or less, such as about 14% or less.

[0023] The inventors have discovered that such distances can provide multilayer ceramic capacitors with low insertion loss. In general, insertion loss is the loss of power through a capacitor and can be measured using any method known in the art. In addition to low insertion loss, such insertion loss generally increases with increasing frequency. For example, such an increase may occur over at least a portion of the frequency range from 4 GHz to 40 GHz, such as at least 25% of the range, such as at least 50% of the range, such as at least 75% of the range, such as at least 80% of the range.

[0024] For example, when measured in a frequency range from 4 GHz to 10 GHz, the insertion loss may be about 0.3 dB or less, such as about 0.28 dB or less, such as about 0.25 dB or less, such as about 0.23 dB or less. When measured in a frequency range from 4 GHz to 10 GHz, the insertion loss may be about 0.05 dB or more, such as about 0.08 dB or more, such as about 0.10 dB or more.

[0025] When measured in the frequency range from 13 GHz to 20 GHz, the insertion loss may be about 0.4 dB or less, such as about 0.38 dB or less, such as about 0.35 dB or less, such as about 0.34 dB or less. When measured in the frequency range from 13 GHz to 20 GHz, the insertion loss may be about 0.15 dB or more, such as about 0.18 dB or more, such as about 0.20 dB or more.

[0026] When measured in the frequency range from 23 GHz to 30 GHz, the insertion loss may be about 0.45 dB or less, such as about 0.4 dB or less, such as about 0.38 dB or less, such as about 0.35 dB or less, such as about 0.32 dB or less. When measured in the frequency range from 23 GHz to 30 GHz, the insertion loss may be about 0.15 dB or more, such as about 0.18 dB or more, such as about 0.20 dB or more, such as about 0.22 dB or more.

[0027] When measured in the frequency range from 33 GHz to 40 GHz, the insertion loss may be about 0.55 dB or less, such as about 0.5 dB or less, such as about 0.48 dB or less, such as about 0.45 dB or less, such as about 0.43 dB or less. When measured in the frequency range from 33 GHz to 40 GHz, the insertion loss may be about 0.20 dB or more, such as about 0.25 dB or more, such as about 0.28 dB or more.

[0028] In addition, the total capacitance of the capacitor can be about 20nF or more, such as about 50nF or more, such as about 70nF or more, such as about 90nF or more, such as about 100nF or more, such as about 115nF or more, such as about 130nF or more. The total capacitance can be about 250nF or less, such as about 200nF or less, such as about 175nF or less, such as about 160nF or less, such as about 150nF or less, such as about 130nF or less, such as about 120nF or less.

[0029] In addition, these advantages can be achieved when using capacitors with relatively small thicknesses. For example, the capacitor can have a thickness of about 13 mils or more, such as about 15 mils or more, such as about 18 mils or more to about 50 mils or less, such as about 40 mils or less, such as about 30 mils or less, such as about 25 mils or less, such as about 23 mils or less, such as about 22 mils or less.

[0030] As a result, the inventors have discovered that the capacitors disclosed herein can be used over a wide frequency range, thereby allowing use in a variety of ultra-wideband applications.

[0031] As described above, the present invention includes a multilayer ceramic capacitor that includes multiple capacitive elements in a single integral package. The capacitor includes a top surface and a bottom surface opposite to the top surface. The capacitor also includes at least one side surface that extends between the top surface and the bottom surface. The capacitor may include at least four side surfaces that extend between the top surface and the bottom surface. In one embodiment, the capacitor includes at least six total surfaces (e.g., a top surface, a bottom surface, four side surfaces). For example, the capacitor and / or the body of the capacitor may have a parallelepiped shape, such as a cuboid shape.

[0032] In general, the capacitor includes alternating dielectric layers and electrode layers, which may form at least a portion of the body of the capacitor. By arranging the dielectric layers and electrode layers in a stacked or laminated configuration, the capacitor may be referred to as a multilayer capacitor and, for example, a multilayer ceramic capacitor when the dielectric layers include ceramics. In general, the stack of alternating dielectric layers and electrode layers (i.e., active electrode layers) may be referred to herein as an active electrode region.

[0033] The electrode layer includes a plurality of first electrode layers and a plurality of second electrode layers. Specifically, the first electrode layers and the second electrode layers are interlaced in a relative and spaced relationship with the dielectric layer located between each adjacent electrode layer. In this regard, the first electrode layers and the second electrode layers can be presented in a parallel relationship.

[0034] In general, the thickness of the dielectric layer and the electrode layer is not limited and can be any thickness as needed according to the performance characteristics of the capacitor. For example, the thickness of the electrode layer can be, but is not limited to, about 500 nm or more, such as about 1 μm or more, such as about 2 μm or more, such as about 3 μm or more, such as about 4 μm or more to about 10 μm or less, such as about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less. For example, the thickness of the electrode layer can be from about 1 μm to about 2 μm. In addition, in one embodiment, the thickness of the dielectric layer can be defined according to the aforementioned thickness of the electrode layer. Similarly, it should be understood that such a thickness of the dielectric layer can also be applied to the layer between any anchor electrode layer, shield electrode layer, and / or floating electrode layer that is present and as defined herein.

[0035] Each electrode layer includes a first electrode and a second (counter) electrode. For example, the first electrode and the second electrode can be substantially in the same plane longitudinally and transversely. The first electrode includes a central portion or body, which extends away from the external terminal and one end of the first electrode toward the other external terminal. Such a portion can extend directly from the external terminal. Alternatively, such a portion can extend from the base portion of the first electrode, which also extends from the external terminal along with the central portion or body. In general, the base portion of the first electrode extends along the longitudinal edge of the first electrode adjacent to the external terminal. In addition, the central portions of the first electrodes of adjacent electrode layers eventually partially overlap in the vertical direction.

[0036] Each first electrode includes at least one electrode arm extending away from the external terminal. The electrode arm may extend directly from the external terminal. Alternatively, the electrode arm may extend from a base portion of the first electrode, which along with the arm also extends from the external terminal. In some embodiments, at least two electrode arms extend away from the external terminal. The electrode arm may extend directly from the external terminal. Alternatively, the electrode arm may extend from a base portion of the first electrode, which along with the arm also extends from the external terminal.

[0037] The second electrode may also include at least one electrode arm. The electrode arm may extend directly from the external terminal. When there are two electrode arms, both electrode arms may extend directly from the external terminal. Alternatively, the electrode arm may extend from a base portion of the second electrode, which along with the arm also extends from the external terminal. In some embodiments, at least two electrode arms extend from the base portion; in such embodiments, the electrode arms are adjacent to each side of the central portion of the first electrode. In general, the electrode arm(s) of the second electrode are longitudinally aligned with the electrode arm(s) of the first electrode.

[0038] It should be understood that when the arm extends from the base portion, such extensions also extend from the external terminals; however, such extensions may not necessarily extend directly from the external terminals.

[0039] In general, at least one electrode arm may include a main body portion and a step portion. For example, at least one electrode arm of each electrode may include a main body portion and a step portion. In some embodiments, each electrode may include two electrode arms and both electrode arms of the electrode may include a main body portion and a step portion. The step portion is offset from at least one lateral edge of the main body portion. In one embodiment, the offset is from a lateral edge of the main body portion close to a center portion of the first electrode. In another embodiment, the offset is from a lateral edge of the main body portion away from a center portion of the first electrode. In one embodiment, the step portion is offset from two lateral edges of the main body portion. However, in another embodiment, it should be understood that the electrode arm may not include a step portion.

[0040] The main body of the electrode arm has a width in the transverse direction, and the step portion of the electrode arm has a width in the transverse direction. The width of the step portion is more than 5% of the width of the main body, such as more than 15%, such as more than 25%, such as more than 35%, such as more than 40%. The width of the step portion is less than 100% of the width of the main body, such as less than 90%, such as less than 80%, such as less than 70%, such as less than 60%, such as less than 50%.

[0041] In addition, the electrode arm has a length in the longitudinal direction, wherein the length is the distance of the arm from the longitudinal edge adjacent to and connected to the external terminal to the longitudinal edge opposite to the longitudinal edge defining the step portion. Thus, the main body portion of the electrode arm and the step portion of the electrode arm have a length in the longitudinal direction, wherein such length is a portion of the length of the electrode arm. The step portion of the electrode arm may have a length (i.e., the distance from the longitudinal edge adjacent to and connected to the external terminal to the longitudinal edge opposite to the longitudinal edge defining the step portion) that is more than 5% of the length of the electrode arm, such as more than 15%, such as more than 20%, such as more than 25%, such as more than 35%, such as more than 40%. The step portion of the electrode arm may have a length that is less than 80%, such as less than 70%, such as less than 60%, such as less than 50%, such as less than 40%, such as less than 30%, of the length of the electrode arm. The main body portion of the electrode arm may have a length (i.e., the distance from the longitudinal edge adjacent to and connected to the external terminal to the opposite longitudinal edge defining the main body portion) that is more than 5%, such as more than 15%, such as more than 25%, such as more than 35%, such as more than 45%, such as more than 55%, such as more than 65%, such as more than 75% of the length of the electrode arm. The main body portion of the electrode arm may have a length that is less than 100% of the length of the electrode arm, such as less than 90%, such as less than 80%, such as less than 70%, such as less than 60%, such as less than 50%, such as less than 40%.

[0042] In addition, a gap (i.e., a main gap distance) exists between the main portion of the electrode arm of the first electrode and the second electrode (e.g., the second electrode arm, in particular the main portion of the second electrode arm). The length of such a gap may be more than 5%, such as more than 15%, such as more than 20%, such as more than 25%, such as more than 35%, of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction. The length of such a gap may be less than 60%, such as less than 50%, such as less than 45%, such as less than 40%, such as less than 35%, of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction. The length of such a gap may be more than 50%, such as more than 60%, such as more than 70%, such as more than 80%, such as more than 90%, such as more than 95%, such as more than 98%, such as 100%, of the length of the main portion of the electrode arm.

[0043] In addition, a gap (i.e., a step gap distance) exists between the step portion of the electrode arm of the first electrode and the second electrode (e.g., the second electrode arm, in particular the step portion of the second electrode arm). The length of such a gap may be more than 1% of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction, for example, more than 3%, for example, more than 5%, for example, more than 7%, for example, more than 8%. The length of such a gap may be less than 30% of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction, for example, less than 20%, for example, less than 15%, for example, less than 10%. The length of such a gap may be more than 5% of the length of the step portion of the electrode arm, for example, more than 10%, for example, more than 15%, for example, more than 18%. The length of such a gap may be less than 50% of the length of the step portion of the electrode arm, for example, less than 40%, for example, less than 30%, for example, less than 25%, for example, less than 20%.

[0044] In addition, the gap between the stepped portion of the electrode arm of the first electrode and the second electrode may be more than 5%, such as more than 10%, such as more than 15%, such as more than 20%, such as more than 25%, of the gap between the main body of the electrode arm of the first electrode and the second electrode. The gap between the stepped portion of the electrode arm of the first electrode and the second electrode may be less than 70%, such as less than 50%, such as less than 40%, such as less than 35%, such as less than 30%, such as less than 25%, of the gap between the main body of the electrode arm of the first electrode and the second electrode.

[0045] In addition, a gap or space exists between a lateral edge of the central portion of the first electrode and a lateral edge of the electrode arm adjacent to (closest to) the lateral edge of the central portion. The lateral edge of the electrode arm adjacent to the central portion may be of the first electrode or the second electrode. Such a gap or space may be more than 40%, such as more than 50%, such as more than 60%, such as more than 70%, such as more than 80%, such as more than 90%, such as 100% of the width of the stepped portion of the electrode arm of the first electrode.

[0046] In addition, in an embodiment where the second electrode does not include a base portion, a gap may exist between a longitudinal edge of the central portion opposite to a longitudinal edge adjacent to and connected to an external terminal and another external terminal. Such a gap may be more than 1% of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction, such as more than 3%, such as more than 5%, such as more than 7%, such as more than 8%. The length of such a gap may be less than 30% of the length of the capacitor from one external terminal to another external terminal in the longitudinal direction, such as less than 20%, such as less than 15%, such as less than 10%.

[0047] Such an electrode configuration can allow a multilayer ceramic capacitor to contain multiple capacitive elements or regions. Figures 1A-1C , the first electrode layer 104 includes a first electrode 106 and a second electrode 108. The first electrode 106 and the second electrode 108 include an electrode arm 110, and the electrode arm 110 includes a main body portion 128 and a step portion 130 offset from a lateral edge 131 of the main body portion 128. In general, at least one capacitive element or region can be formed between a central portion 112 of the first electrode 106 of the first electrode layer 102 and a central portion 112 of the first electrode 106 of the second active electrode layer 104 (i.e., a primary capacitive element). However, with the specific electrode configurations disclosed herein, a secondary capacitive element or region (i.e., a central capacitive region 122) can be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or the electrode arm 110 of the second electrode 108. In addition, another secondary capacitive element (i.e., a main body arm gap capacitive region 124) can be formed in the gap between the main body portion 128 of the electrode arm 110 of the first electrode 106 and the second electrode 108. Additionally, another secondary capacitive element (i.e., a stepped arm gap capacitive region 126) may be formed between the stepped portion 130 of the electrode arm 110 of the first electrode 106 and the second electrode 108. However, as described above, it should be understood that in at least one embodiment, the electrode may not include a stepped portion.

[0048] Thus, the electrode configuration may allow for a primary capacitive element (ie, parallel plate capacitance) between the central portions of adjacent electrode layers as well as an additional secondary capacitive element. Fig. 7A and 7B This capacitance is further depicted in . For example, Fig. 7A Three groups of capacitive regions are depicted: primary capacitive elements between adjacent electrode layers, central capacitive region 122, and bulk arm gap capacitive region 124. When the electrode arms include stepped portions, the electrodes may include stepped arm gap capacitive regions 126. In this regard, Figure 7B Four groups of capacitive regions are depicted: primary capacitive elements between adjacent electrode layers, central capacitive region 122, main arm gap capacitive region 124, and step arm gap capacitive region 126. The capacitive region of the primary capacitive element is depicted as 112', while the capacitive regions of the secondary capacitive elements 122, 124 are depicted as 122', 124', and 126', respectively. In addition, external terminals are depicted as 152 and 154.

[0049] It should be understood that the actual values ​​of capacitors 112', 122', 124', and 126' can be selectively designed by adjusting the configuration of the capacitors and various parameters, such as the number of electrode layers, the surface area of ​​the overlapping center portions of the electrode pairs, the distance separating the electrodes, the dielectric constant of the dielectric material, etc. However, the capacitors disclosed herein may include arrays of combined series and parallel capacitors to provide effective broadband performance.

[0050] In an exemplary ultra-wideband capacitor embodiment, primary capacitor 112' generally corresponds to a relatively large capacitance suitable for operation in a generally lower frequency range, such as on the order of between about a few kilohertz (kHz) to about 200 megahertz (MHz), while secondary capacitors 122', 124' and 126' generally correspond to relatively smaller value capacitors configured to operate in a relatively higher frequency range, such as on the order of about 200 megahertz (MHz) to many gigahertz (GHz).

[0051] In this regard, additional means for coupling electrodes of opposite polarity within the capacitor body may be introduced, and by forming such multiple capacitive elements in a single set of stacked electrodes, this approach may be more efficient and effective. For example, the primary capacitive element may be effective at relatively low frequencies, while the secondary capacitive element may be effective at relatively medium and / or higher frequencies. For example, the primary capacitance may be within 1 and 500 nF, such as within about 10 and 100 nF, while the secondary capacitance may be within 1 and 500 pF, such as within 10 and 100 pF.

[0052] In addition to the above, it should be understood that the capacitor of the present invention may include additional electrode layers. For example, as is known in the art, the capacitor of the present invention may include an anchoring electrode layer, a shielding electrode layer, a floating electrode layer, or a combination thereof. In one embodiment, the capacitor includes an anchoring (or dummy) electrode layer. In another embodiment, the capacitor includes at least a shielding electrode layer. In another embodiment, the capacitor includes at least a floating electrode. In another embodiment, the capacitor includes both an anchoring electrode layer and a shielding electrode layer. In another embodiment, the capacitor includes an anchoring electrode layer, a shielding electrode layer, and a floating electrode layer. When present, such an electrode layer is also arranged in an interlaced configuration with the dielectric layer. However, it should be understood that the capacitor may not include any of the above-mentioned anchoring electrode layers or shielding electrode layers.

[0053] As described above, the capacitor may include an anchoring electrode layer. In such an embodiment, the anchoring electrode layer may include a third anchoring electrode and a fourth anchoring electrode. Such anchoring electrodes may be substantially in the same plane longitudinally and laterally. The anchoring electrode layer may be used to provide additional nucleation points and guidance for external terminations, for example, when a thin film layer of conductive material is plated directly on an electrode layer exposed along a surface of the capacitor body. As further described herein, such plating techniques may be referred to as electroless and / or electrolytic plating.

[0054] In general, the positioning of such anchoring electrode layers is not necessarily limited. In one embodiment, such an anchoring electrode layer may be disposed between the corresponding first electrode layer and the second electrode layer. In another embodiment, such an anchoring electrode layer may be disposed above and / or below a stack of alternating dielectric layers and internal (active or first / second) electrode layers. Such an anchoring electrode layer may be disposed within an anchoring electrode region, wherein each region includes at least one anchoring electrode layer. For example, the anchoring electrode layer may be disposed on and near the top of a stacked assembly of dielectric layers and active electrode layers. The anchoring electrode layer may be disposed below and near a stacked assembly of dielectric layers and electrode layers. When present, a third anchoring electrode of the anchoring electrode layer may contact the first external terminal, and a fourth anchoring electrode of the anchoring electrode layer may contact the second external terminal.

[0055] In addition, the anchoring electrode layer can have any configuration known in the art. For example, the third anchoring electrode and the fourth anchoring electrode can have a C-shaped configuration. For example, the anchoring electrode can have a base portion and at least one electrode arm, such as two electrode arms, which extend from the base portion, in particular from the lateral ends of the base portion. Such an electrode arm can extend away from the end of the capacitor body in the longitudinal direction. The electrode arms of the third anchoring electrode and the fourth anchoring electrode can also be aligned longitudinally. The electrode arms can have sizes and gaps as shown; such sizes and gaps can be the same as the gaps and arms described for the first electrode and the second electrode of the electrode layer. In general, the anchoring electrode can have a configuration different from the configuration of the above-mentioned first active electrode layer and the second active electrode layer and the shielding electrode described below.

[0056] In one embodiment, the electrode arm of the anchoring electrode may also have a main body portion and a stepped portion. Such a main body portion and stepped portion are defined identically to the electrode arms of the first electrode and the second electrode of the electrode layer. In this regard, the size of the arms, main body portions and / or stepped portions of the anchoring electrode and the first electrode and / or the second electrode may be substantially similar. However, it should be understood that the anchoring electrode may also include an electrode arm without a stepped portion.

[0057] As described above, the capacitor may include a shielding electrode layer. In such an embodiment, the shielding electrode layer may include five shielding electrodes and six shielding electrodes. Such shielding electrodes may be substantially in the same plane longitudinally and laterally. The shielding electrode layer may be used to provide additional capacitance, protection against electromagnetic interference, and / or other shielding properties.

[0058] In general, the positioning of such a shielding electrode layer is not necessarily limited. For example, in one embodiment, the shielding electrode layer may be arranged above and / or below the stack of alternating dielectric layers and internal (active or first / second) electrode layers. Such a shielding electrode layer may be arranged in a shielding electrode region, wherein each region includes at least one shielding electrode layer. For example, the shielding electrode layer may be arranged above the stacked assembly of the dielectric layer and the electrode layer. Alternatively, the shielding electrode layer may be arranged below the stacked assembly of the dielectric layer and the electrode layer. In another embodiment, the shielding electrode layer may be arranged above and below the stacked assembly of the dielectric layer and the electrode layer. When present, the fifth shielding electrode of the shielding electrode layer may contact the first external terminal, and the sixth shielding electrode of the shielding electrode layer may contact the second external terminal.

[0059] The shield electrode region may be directly above the active electrode region. In one embodiment, the shield electrode region may be separated from the active electrode region by a dielectric region, such as a dielectric region that does not include any electrode layers. In one embodiment, the shield electrode region may be separated from the active electrode region by an anchor electrode region. In another embodiment, the shield electrode region may be separated from the active electrode region by a dielectric region and an anchor electrode region.

[0060] In general, the shielding electrode layer can have any configuration known in the art. For example, the fifth shielding electrode and the sixth shielding electrode can have a rectangular configuration (i.e., not including a stepped portion). Alternatively, the fifth shielding electrode and the sixth shielding electrode can have a step as disclosed herein. For example, the step can be located in the lateral direction from the lateral edge of the shielding electrode. In this regard, the size of the stepped portion of the shielding electrode and the first electrode and / or the second electrode can be substantially similar. In general, the shielding electrode can have a configuration different from the configuration of the first active electrode layer and the second active electrode layer and the above-mentioned anchoring electrode.

[0061] In addition, the shielding electrode layer may include a shielding layer gap between the fifth electrode and the sixth electrode. For example, the fifth electrode may be connected to the first terminal, and the sixth electrode may be connected to the second terminal. The shielding layer gap may be the distance between the unconnected ends of the corresponding terminals in the longitudinal direction. In one embodiment, such a shielding layer gap may be smaller than the external terminal gap between the external terminals on the top surface and / or the bottom surface of the capacitor. For example, the external terminal may be terminated on the top surface and / or the bottom surface of the capacitor. The distance between the termination ends of the external terminals on such a surface may be defined as the external terminal gap in the longitudinal direction. For example, such a length of the shielding layer gap in the longitudinal direction may be about 3% or more of the length of the external terminal gap in the longitudinal direction, such as about 5% or more, such as about 10% or more, such as about 15% or more, such as about 20% or more, such as about 25% or more, such as about 30% or more to less than 100%, such as about 80% or less, such as about 60% or less, such as about 40% or less, such as about 35% or less, such as about 25% or less, such as about 20% or less, such as about 15% or less, such as about 10% or less. However, it should be understood that in another embodiment, the length of the shield gap may be substantially the same as the length of the external terminal gap.

[0062] In one embodiment, the shielding electrode layer can be separated from the stacked components by an anchoring electrode region comprising at least one anchoring electrode layer. In this regard, the shielding electrode layer can be disposed above and / or below the at least one anchoring electrode region. For example, the shielding electrode layer can be disposed on top of and near the at least one anchoring electrode region. The shielding electrode layer can be disposed directly below and near the at least one anchoring electrode region. In one embodiment, such an anchoring electrode region can include multiple anchoring electrode layers.

[0063] In addition, the shielding electrode can be embedded in the capacitor. For example, the body of the capacitor can include a ceramic cover on the top surface and / or the bottom surface. In one embodiment, the capacitor includes a ceramic cover on both the top surface and the bottom surface. The ceramic cover can be the same material as used for the dielectric layer. However, in one embodiment, the capacitor can include a shielding electrode layer adjacent to the top surface and / or the bottom surface of the capacitor. Such a shielding electrode can help form an external terminal.

[0064] As described above, the capacitor may include a floating electrode layer including at least one floating electrode. In such an embodiment, the floating electrode layer may include a seventh electrode. Generally, such a floating electrode is not directly connected to an external terminal. However, the floating electrode may be part of a floating electrode layer including at least one electrode electrically connected to an external terminal; however, such a floating electrode layer includes at least one floating electrode that does not directly contact such an electrode or an external terminal.

[0065] The floating electrode may be arranged or configured according to any method known in the art. For example, the floating electrode may be arranged so that it overlaps at least a portion (e.g., a central portion) of the first electrode of the first electrode layer and / or the second electrode layer. In this regard, the floating electrode layer is layered and alternately arranged with the first electrode layer and the second internal electrode layer; in this regard, these layers may be separated by a dielectric layer.

[0066] In addition, such floating electrodes may have any shape known in the art. For example, in one embodiment, the floating electrode layer may include at least one floating electrode having a dagger-like configuration. For example, such a configuration may be similar to the configuration and shape of the first electrode described herein. However, it should be understood that such a first electrode may or may not include an electrode arm having a stepped portion.

[0067] In addition, in one embodiment, the floating electrode layer may include at least one floating electrode, wherein an end of the floating electrode is near at least one external terminal but does not contact such external terminal. In this regard, such a gap may be referred to as a floating electrode gap in the longitudinal direction. Such a floating electrode gap may be greater than 0%, such as about 3% or more, such as about 5% or more to about 50% or less, such as about 40% or less, such as about 30% or less, such as about 20% or less, such as about 10% or less of the length of the capacitor in the longitudinal direction.

[0068] In addition, the capacitor includes a first external terminal and a second external terminal. In particular, the first external terminal can be arranged along a first end or side surface of the capacitor, and the second external terminal can be arranged along a second end or side surface of the capacitor opposite to the first end or side surface in the longitudinal direction. In general, the first electrode of the first electrode layer and the second (counter) electrode of the second electrode layer are electrically connected to the first external terminal. At the same time, the first electrode of the second electrode layer and the second (counter) electrode of the first electrode layer are electrically connected to the second external terminal. In one embodiment, the external terminals are wrapped around the top surface and / or the bottom surface. In another embodiment, each external terminal is wrapped around five surfaces and in contact with them-the top surface, the bottom surface and three side surfaces. In another embodiment, the external terminals are only present on the side surfaces so that they are not wrapped around the top surface, the bottom surface and / or any other side surface.

[0069] In addition, it should be understood that the capacitors disclosed herein can be installed in any orientation as desired. For example, the capacitor can be installed horizontally so that the dielectric layer and / or the electrode layer are substantially parallel to the surface on which the capacitor is installed. In this regard, the dielectric layer and / or the electrode layer are stacked in a vertical direction. Alternatively, the capacitor can be installed vertically, wherein the dielectric layer and / or the electrode layer are substantially orthogonal to the surface on which the capacitor is installed. In addition, when installed vertically, the capacitor can be installed in at least two different orientations. For example, the capacitor can be installed so that the long side of the dielectric layer and / or the electrode layer is adjacent to the surface. Alternatively, the capacitor can be installed so that the short side of the dielectric layer and / or the electrode layer is adjacent to the surface.

[0070] The present invention also relates to a method of making an ultra-wideband capacitor. The method comprises providing an active electrode region comprising a dielectric layer and an active electrode layer and providing a shielding electrode region comprising at least one shielding electrode. The method may also require a distance between the active electrode region and the shielding electrode region and / or a distance between the active electrode region and the top surface of the capacitor as defined herein. In addition, when present, the method may also include providing at least one anchoring electrode layer.

[0071] In addition, the method may include exposing a longitudinal edge of each base portion in the body; such exposure may facilitate the formation of external terminals. Such exposure may already exist when the electrode layer is formed. In addition, the electrode may be exposed on at least three sides; such exposure may allow for wrap-around termination. For example, such wrap-around termination may be present on at least three surfaces, such as at least five surfaces of the capacitor. Thus, the method may also include forming a first external terminal and a second external terminal as disclosed herein.

[0072] according to Figures 1A-1D , 2, 3A-3B, 4A-4B, 5A-5C, 6A-6D and 8A-8C, can further describe the capacitor of the present invention. As shown in the figure, 134 is called the lateral direction, and 132 is called the longitudinal direction, wherein the lateral direction 134 can be perpendicular to the longitudinal direction 132. At the same time, 136 is called the vertical direction (i.e., the Z direction).

[0073] Go to Figures 1A-1D , an embodiment of a multilayer ceramic capacitor is disclosed. Figure 1D A multilayer capacitor 100 is shown that includes a plurality of first electrode layers 106 and second electrode layers 108. The multilayer capacitor 100 includes a first external terminal 118 that is connected to the first electrode 106 of the first electrode layer 102 and the second (counter) electrode of the second electrode layer 104. The multilayer capacitor includes a second external terminal 120 that is connected to the first electrode 106 of the second electrode layer 104 and the second (counter) electrode of the first electrode layer 102.

[0074] Figure 1A A top view of a first electrode layer 102 and a second electrode layer 104 is shown. Each electrode layer includes a first electrode 106 and a second electrode 108. The first electrode 106 may have a base portion 114 that extends along a longitudinal edge of the first electrode 106. The first electrode 106 has a pair of electrode arms 110 and at least one center portion 112 extending from the base portion 114. The second electrode 108 may have a base portion 114 that extends along a longitudinal edge of the second electrode layer 108. The second electrode has a pair of electrode arms 110 extending from the base portion 114. In addition, Figure 1A An electrode horn 110 is shown including a main body portion 128 and a stepped portion 130. The stepped portion is formed by a step or offset 116. That is, the stepped portion 116 is offset from at least one lateral edge 131 of the main body portion 128 of the electrode horn 110.

[0075] At the same time, if Figure 1A As shown, the second electrode layer 104 has the same configuration as the first electrode layer 102, except that it is a mirror image configuration.

[0076] Apart from Figure 1AIn addition to the embodiments of the present invention, it should be understood that various other electrode configurations may be used. For example, such an electrode configuration in Figures 8A-8C As shown in Fig. 8A As shown, the first electrode 106 includes a central portion 112 and a pair of electrode arms 110 extending from a base portion 114. Meanwhile, the second electrode 108 includes a pair of electrode arms 110 extending from longitudinal ends near the external terminal 119. Figure 8B In the embodiment, the first electrode 106 includes a central portion 112 and a pair of electrode arms 110 extending from longitudinal ends near the external terminal 121; meanwhile, the second electrode 108 includes a pair of electrode arms 110 extending from a base portion 114. Figure 8C In the embodiment, the first electrode 106 includes a central portion 112 and a pair of electrode arms 110 extending from longitudinal ends near the external terminal 121 ; meanwhile, the second electrode 108 includes a pair of electrode arms 110 extending from longitudinal ends adjacent to the external terminal 119 .

[0077] Therefore, if Fig. 8A and 8C As shown, without the base portion in the second electrode 108, the central capacitive region 122 is formed between the central portion 112 of the first electrode 106 and the arm 110 of the second electrode 108, and the outer capacitive region 125 is formed between the front longitudinal edge (opposite the edge adjacent to the outer terminal 121) of the central portion 112 of the first electrode 106 and the outer terminal 119. In this regard, the depiction in FIG. 7 may include additional parallel connections for the capacitive region 125'.

[0078] refer to Figure 1B , the plurality of first electrode layers 102 and the plurality of second electrode layers 104 exist in an alternating mirror configuration. As shown, the central portions 112 of the respective electrode layers at least partially overlap. Figure 1B A total of six electrode layers are shown; however, it should be understood that any number of electrode layers may be employed to achieve the desired capacitance for the desired application.

[0079] refer to Figure 1C and 1D, the first electrode 106 of the second electrode layer 104 can be electrically connected to the second terminal 120 along the second end 121; similarly (and not shown), the first electrode 106 of the first electrode layer 102 can be electrically connected to the first external terminal 118 along the first end 119. In some embodiments, several capacitive regions can be formed between the first electrode 106 and the second electrode 108. For example, in some embodiments, the central capacitive region 122 can be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or arm 110 of the second electrode 108. In some embodiments, the main arm gap capacitive region 124 can be formed between the main portion 128 of the electrode arm 110 of the first electrode 106 and the second electrode 108. In addition, the step arm gap capacitive region 126 can be formed between the step portion 130 of the electrode arm 110 of the first electrode 106 and the second electrode 108.

[0080] refer to Figure 2 In some embodiments, the second electrode layer 104 may include the first electrode 106 and the second electrode 108 described above. The first electrode 106 may have an electrode arm 110, and the electrode arm 110 may include a main body portion 128 and a stepped portion 130. The main body portion 128 may have at least one lateral edge 131 extending from the second end 120 of the multilayer capacitor in a longitudinal direction 132. The stepped portion 130 may be offset from the lateral edge 131 of the main body portion 128 in a lateral direction 134.

[0081] The second electrode 108 can be electrically connected to the first external terminal 119 and can have an electrode arm 202 extending in the longitudinal direction 132. In some embodiments, the electrode arm 110 can be generally longitudinally aligned with the electrode arm 202. In some embodiments, the electrode arm 110 and the electrode arm 202 can be spaced apart in the longitudinal direction 132 to form a body gap 226 between the body portion 128 of the electrode arm 100 and the electrode arm 202. The body gap 226 can have a body gap distance 240 in the longitudinal direction 132.

[0082] In some embodiments, the electrode arm 110 step portion 130 may extend beyond the main body portion 128 of the electrode arm 110 and away from the second end 120 in the longitudinal direction 132. Similarly, the electrode arm 202 step portion 130 may extend beyond the main body portion 128 of the electrode arm 202 and away from the second end 119 in the longitudinal direction 132. In this regard, in some embodiments, the electrode arm 110 and the electrode arm 202 may form a step distance 230 between the step portion 130 of the electrode arm 110 and the electrode arm 202. The step distance 230 may have a step gap distance 232 in the longitudinal direction 132.

[0083] In some embodiments, the stepped portion 130 of the electrode horn 110 can be offset inwardly from the lateral edge 131 of the body portion 128 toward the lateral centerline 234 of at least one of the plurality of electrode layers. An offset distance 238 can be defined in the lateral direction 134 between the lateral edge 131 and a lateral edge of the stepped portion 130 proximate to the lateral edge 131 of the body portion 128. However, as further described herein, it should be understood that the electrode horn can have alternative configurations with respect to the stepped portion.

[0084] refer to Figure 3A and Figure 3B In some embodiments, the multilayer capacitor 300 may include a first external terminal 118 disposed along a first end 119 and a second external terminal 120 disposed along a second end 121 opposite the first end 119 in the longitudinal direction 132. The multilayer capacitor 300 may include a plurality of dielectric layers and a plurality of electrode layers, wherein the electrode layers are interleaved in an opposing and spaced relationship with the dielectric layers located between each adjacent electrode layer.

[0085] In addition, as described above, the multilayer capacitor may include a shield electrode. Figure 3A As shown, the multilayer capacitor 300 may include a first shielding region 210 and a second shielding region 212, and each of the shielding regions 210, 212 may include one or more shielding electrode layers 214. The shielding regions 210, 212 may be separated from the active electrode region 216 by a dielectric region (e.g., a dielectric region that does not include any electrode layer). Figure 3B , the shielding electrode layer 214 can have a first shielding electrode configuration, wherein each shielding electrode 220 is substantially rectangular. In other embodiments, the shielding electrode layer 214 can have a second shielding electrode configuration, wherein the shielding electrode 222 includes a step 224, such as the above reference Figure 1A and 2 As explained above, the shielding electrode is at an edge of the shielding electrode opposite to an edge of the shielding electrode adjacent to the external terminal.

[0086] In some embodiments, the active electrode region 218 may be disposed between the first shielding region 210 and the second shielding region 212. The active electrode region 216 may include a plurality of alternating active electrode layers 218, for example, as described in reference Figures 1A-1D Additionally, a pair of ceramic caps 226 may be disposed along the top surface and / or the bottom surface of the capacitor 300 .

[0087] refer to Figure 4A and 4BIn some embodiments, the multilayer capacitor 300 may further include anchoring electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 may include a first anchoring electrode region 304 on top of the active electrode region 216. Additionally, the shielding electrode region 210 including the shielding electrode layer 214 may be disposed above the first anchoring electrode region 304, such as on top thereof. Additionally, the second anchoring electrode region 302 may be disposed above the shielding electrode region 210, such as on top thereof. Similarly, the multilayer capacitor 300 may include a third anchoring electrode region 316 below the active electrode region 216, such as directly below it. Additionally, the shielding electrode region 210 including the shielding electrode layer 214 may be disposed below the third anchoring electrode region 316, such as directly below it. Additionally, the fourth anchoring electrode region 318 may be disposed below the shielding electrode region 210, such as directly below it. In this regard, for example, the active electrode region 216 can be disposed between the first anchor electrode region 304 and the third anchor electrode region 316. The active electrode region 216 can be as described above with reference to Figure 3A and 3B Configure as described.

[0088] refer to Figure 4B , the anchoring electrode regions 302, 304, 316, and / or 318 may include a plurality of anchoring electrode layers 310, each of which has a pair of anchoring electrodes 312. The anchoring electrodes 312 may include a pair of electrode arms 314. Each electrode arm 314 of the anchoring electrode 312 may include a main body portion 328 and a stepped portion 330, for example, in a manner similar to that described above with reference to Figure 1A and 2 The electrodes are described in the manner described.

[0089] refer to Figure 5A , 5B 5C, the anchor electrode 312 can have various configurations. For example, referring to Figure 5A In some embodiments, the electrode arm 314 of the anchor electrode 312 may not include a step. For example, such an electrode may have a C-shaped configuration without a step. Figure 5B In some embodiments, the electrode arm 314 of the anchor electrode 312 may include a stepped portion 320 that is offset inwardly from an outer lateral edge 322 of the anchor electrode 312. Figure 5C In other embodiments, the stepped portion 320 can be offset from the inner lateral edge 324 of the arm 314 of the anchor electrode 312. Other configurations are also possible. For example, in some embodiments, the stepped portion 320 can be offset from the outer lateral edge 322 and the inner lateral edge 324.

[0090] refer to Figures 6A-6CIn some embodiments, the active electrodes 106, 108 may have various other configurations. For example, referring to Fig. 6A In some embodiments, the first electrode 106 and the second electrode 108 may include a single arm 110, rather than a pair of arms 110, 202, as described above with reference to Figure 2 In this regard, such an electrode may include an electrode comprising a central portion extending from a base portion and an electrode arm also extending from the base portion; while the counter electrode may include a base portion and only one electrode arm extending from the base portion of such a second electrode.

[0091] refer to Figure 6B In some embodiments, each of the first electrode 106 and the second electrode 108 may include a central portion 112. For example, in addition to at least one electrode arm 110, 202, such as two electrode arms 110, 202 extending from the corresponding base portion, each electrode 106, 108 may include a central portion 112 extending from the corresponding base portion.

[0092] refer to Figure 6C In some embodiments, the electrode arms 110, 202 of the electrodes 106, 108 may have a stepped portion 130, wherein a lateral centerline 236 of at least one of the electrodes 106, 108 away from the electrode layer is offset outwardly from an inner lateral edge 324 of the main body portion of the electrode arm. Fig.6D In some embodiments, the electrode arms 110 of the electrodes 106 , 108 may have a stepped portion 130 that is offset from the outer lateral edge 322 and the inner lateral edge 324 of the electrode arms 110 , 202 .

[0093] In addition to the embodiments shown and described herein, the central portion of the electrode can have any configuration known in the art. Figure 1A and 6A -6D, the center portion can have a relatively rectangular configuration. That is, the lateral edges can extend substantially linearly in the longitudinal direction. However, other configurations can also be used. For example, in one embodiment, the center portion of the electrode can include a paddle-shaped configuration; in such an embodiment, the lateral edges extend substantially linearly in the longitudinal direction away from the base portion, then extend in the lateral direction away from the center portion, and then extend substantially linearly in the longitudinal direction away from the base portion again. In another embodiment, the center portion of the electrode can include a wing-shaped configuration; in such an embodiment, the lateral edges extend substantially linearly in the longitudinal direction away from the base portion, then extend in the lateral direction away from the center portion, then extend substantially linearly in the longitudinal direction away from the base portion again, then extend in the lateral direction toward the center portion, and then extend substantially linearly in the longitudinal direction away from the base portion again.

[0094] In general, the present invention provides a multilayer capacitor having electrodes having a unique configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used to construct the capacitor may not be limited and may be any material commonly used in the art and may be formed using any method commonly used in the art.

[0095] In general, the dielectric layer is typically formed of a material having a relatively high dielectric constant (K), such as from about 10 to about 40,000, in some embodiments, from about 50 to about 30,000, and in some embodiments, from about 100 to about 20,000.

[0096] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms, such as a wafer (eg, pre-fired) or a co-fired dielectric material within the device itself.

[0097] Specific examples of types of high dielectric materials include, for example, NPO (COG) (to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be understood that the above materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and therefore, those of ordinary skill in the art should recognize. For example, such materials may include ceramics. Such materials may include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate, barium strontium zirconate titanate, calcium barium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lanthanum lead zirconate titanate), sodium bismuth titanate, etc. In a specific embodiment, for example, a material with the chemical formula Ba may be used. x Sr 1-x TiO 3 Barium strontium titanate ("BSTO"), wherein x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments, from about 0.25 to about 0.6. Other suitable perovskites may include, for example, Ba x Ca 1- x TiO 3 , wherein x is from about 0.2 to about 0.8, and in some embodiments, from about 0.4 to about 0.6, Pb x Zr 1-x TiO 3 (“PZT”), wherein x ranges from about 0.05 to about 0.4, lead lanthanum zirconate titanate (“PLZT”), lead titanate (PbTiO 3 ), barium calcium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ) and NaBa 2 (NbO 3 ) 5 HkDJ 2 PO 4 Other complex perovskites can include A[B1 1 / 3 B2 2 / 3 ]O 3 Materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z may have a value from 0 to 1.) In one particular embodiment, the dielectric layer may include titanate.

[0098] The electrode layer can be formed of any of a variety of different metals known in the art. The electrode layer can be made of a metal, such as a conductive metal. The material can include precious metals (e.g., silver, gold, palladium, platinum, etc.), basic metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys and corresponding sputtered layers of chromium, nickel, and gold may also be applicable. The electrode may also be made of a low resistance material, such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the electrode layer may include nickel or its alloys.

[0099] The external terminals may be formed from any of a variety of different metals known in the art. The external terminals may be made of metals, such as conductive metals. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), basic metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. In a particular embodiment, the external terminals may include copper or an alloy thereof.

[0100] The external terminals can be formed using any method known in the art. The external terminals can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / air brush, etc.

[0101] In one embodiment, the external terminals can be formed so that the external terminals are relatively thick. For example, such terminals can be formed by applying a thick film strip of metal on the exposed portion of the electrode layer. Such metal can be in a glass matrix and can include silver or copper. For example, such strips can be printed and fired onto the capacitor. Thereafter, additional metal plating (e.g., nickel, tin, solder, etc.) can be formed on the termination strip to allow the capacitor to be soldered to the substrate. The application of such thick film strips can be performed using any method known in the art (e.g., by a termination machine and printing wheel for transferring a metal-loaded paste to the exposed electrode layer). Examples of assembly components with external terminals formed by baked terminals and metal films plated thereon are disclosed in U.S. Patent No. 5,021,921 to Sano et al., which is incorporated herein by reference for all purposes.

[0102] The thick plated external terminals may have an average thickness of about 150 μm or less, such as about 125 μm or less, such as about 100 μm or less, such as about 80 μm or less. The thick plated external terminals may have an average thickness of about 25 μm or more, such as about 35 μm or more, such as about 50 μm or more, such as about 75 μm or more. For example, the thick plated external terminals may have an average thickness from about 25 μm to about 150 μm, such as from about 35 μm to about 125 μm, such as from about 50 μm to about 100 μm.

[0103] In another embodiment, the external terminal can be formed such that the external terminal is a thin film plating of a metal. Such a thin film plating can be formed by depositing a conductive material such as a conductive metal on an exposed portion of the electrode layer. For example, the leading edge of the electrode layer can be exposed so that it can allow the formation of a plated termination.

[0104] The thin plated external terminals may have an average thickness of about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less. The thin plated external terminals may have an average thickness of about 5 μm or more, such as about 10 μm or more, such as about 15 μm or more. For example, the external terminals may have an average thickness from about 5 μm to about 50 μm, such as from about 10 μm to about 40 μm, such as from about 15 μm to about 30 μm, such as from about 15 μm to about 25 μm.

[0105] In general, the external terminal may include a plated terminal. For example, the external terminal may include a plated terminal, an electroless terminal, or a combination thereof. For example, the plated terminal may be formed via electrolytic plating. The electroless terminal may be formed via electroless plating.

[0106] When multiple layers constitute the external terminals, the external terminals may include electroplated terminals and electroless plated terminals. For example, electroless plating may be first used to deposit the initial layer of material. The plating technique may then be switched to an electrochemical plating system, which may allow for faster material deposition.

[0107] When forming the plated terminal by any plating method, the leading edge of the lead tab of the electrode layer exposed from the body of the capacitor is subjected to the plating solution. By being subjected, in one embodiment, the capacitor can be immersed in the plating solution.

[0108] The plating solution contains a conductive material, such as a conductive metal, which is used to form a plated termination. Such a conductive material can be any of the aforementioned materials or any material known in the art. For example, the plating solution can be a nickel sulfamate bath or other nickel solution, so that the coating and the external terminal include nickel. Alternatively, the plating solution can be a cupric acid bath or other suitable copper solution, so that the coating and the external terminal include copper.

[0109] In addition, it should be understood that the plating solution may include other additives known in the art. For example, the additive may include other organic additives and media that may assist in the plating process. In addition, additives may be used to use the plating solution at a desired pH. In one embodiment, an additive that reduces resistance may be used in the solution to assist in complete coating coverage and bonding of the plating material to the exposed leading edge of the capacitor and lead tabs.

[0110] The capacitor may be exposed, submerged or immersed in the plating solution for a predetermined time. Such exposure time need not be limited, but may take sufficient time to allow sufficient plating material to be deposited to form a plated terminal. In this regard, the time should be sufficient to form a continuous connection between the desired exposed adjacent leading edges of the desired lead tabs of a given polarity of the corresponding electrode layer within a set of alternating dielectric layers and electrode layers.

[0111] Generally, electrolytic plating differs from electroless plating in that electrolytic plating employs an electrical bias, such as using an external power source. Electrolytic plating baths can typically withstand a relatively high current density range, for example, ten to fifteen amp / ft 2 (rated at 9.4 volts). Connections can be made in the same plating bath, with a negative connection to the capacitor to which the plating terminal is to be formed and a positive connection to the solid material (e.g., Cu in a Cu plating bath). That is, the capacitor is biased to a polarity opposite to that of the plating bath. Using this approach, the conductive material of the plating bath is attracted to the metal at the exposed leading edge of the lead tab of the electrode layer.

[0112] Various pre-treatment steps may be used before immersing or subjecting the capacitor to a plating solution. These steps may be performed for a variety of purposes, including catalyzing, accelerating, and / or improving adhesion of the plating material to the leading edge of the lead tab.

[0113] In addition, an initial cleaning step may be used prior to plating or any other pretreatment step. Such a step may be employed to remove any oxide buildup formed on the exposed lead tabs of the electrode layer. When the internal electrodes or other conductive elements are formed of nickel, this cleaning step may be particularly helpful in assisting in removing any buildup of nickel oxide. Part cleaning may be performed by complete immersion in a pre-cleaning bath, such as a pre-cleaning bath comprising an acid cleaner. In one embodiment, exposure may be continued for a predetermined time, such as on the order of about 10 minutes. Alternatively, cleaning may also be performed by a chemical polishing or harperizing step.

[0114] In addition, a step of activating the exposed metal leading edge of the lead tab of the electrode layer may be performed to facilitate the deposition of the conductive material. Activation may be achieved by immersion in a palladium salt, a photopatterned palladium organometallic precursor (via a mask or laser), a palladium compound deposited by screen printing or inkjet, or electrophoretic palladium deposition. It should be understood that only palladium-based activation is currently disclosed as an example of an activation solution, which generally works well with activation of the exposed tab portion formed of nickel or its alloys. However, it should be understood that other activation solutions may also be used.

[0115] Additionally, in lieu of or in addition to the activation step described above, an activating dopant may be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer comprises nickel and the activating dopant comprises palladium, a palladium dopant may be introduced into the nickel ink or composition that forms the electrode layer. Doing so may eliminate the palladium activation step. It should be further understood that certain activation methods described above, such as organometallic precursors, are also suitable for co-deposition of glass formers to increase adhesion to the general ceramic body of the capacitor. When an activation step is taken as described above, traces of the activator material may often remain at the exposed conductive portions before and after termination plating.

[0116] In addition, post-treatment steps after plating can also be used. These steps can be performed for a variety of purposes, including enhancing and / or improving the adhesion of the material. For example, a heating (or annealing) step can be used after performing the plating step. This heating can be performed via baking, laser irradiation, ultraviolet irradiation, microwave irradiation, arc welding, etc.

[0117] As indicated herein, the external terminal includes at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may also include a third plating layer. The materials of these plating layers may be any of the aforementioned and are well known in the art.

[0118] For example, one coating, such as the first coating, may include copper or an alloy thereof. Another coating, such as the second coating, may include nickel or an alloy thereof. Another coating, such as the third coating, may include tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, the initial coating may include nickel, followed by a coating of tin or gold. In another embodiment, an initial coating of copper may be formed, followed by a layer of nickel.

[0119] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistor polymer material for sealing. The area may then be polished to selectively remove the resistive polymer material and then plated again with a third layer comprising a conductive metal material (e.g., copper).

[0120] The second layer above the initial plated layer may correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the layer may be formed by electroplating an additional metal (e.g., nickel) layer on top of the initial electroless or electrolytic plated layer (e.g., copper plating). Other exemplary materials for forming the solder barrier layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the solder barrier layer may correspond to a conductive layer, such as nickel plating, nickel / chromium, silver, palladium, tin, lead / tin, or other suitable plated solder.

[0121] Additionally, a metal coating may be formed and then an electroplating step may be performed to provide a resistive alloy or a higher resistive metal alloy coating on the metal coating, such as an electroless Ni-P alloy. However, it should be understood that any metal coating may be included, as will be understood by those of ordinary skill in the art from the overall disclosure herein.

[0122] It should be understood that any of the above steps can occur as a bulk process, such as barrel plating, fluidized bed plating and / or flow plating termination processes, all of which are well known in the art. Such bulk processes enable multiple components to be processed together, thereby providing an efficient and fast termination process. This is a particular advantage over traditional termination methods (e.g., printing of thick film terminations that require individual processing of components).

[0123] As described herein, the formation of the external terminations is generally guided by the location of the exposed leading edge of the lead tab of the electrode layer. Such a phenomenon may be referred to as "self-determining" because the formation of the external plated terminations is determined by the configuration of the exposed conductive metal of the electrode layer at a selected peripheral location on the capacitor.

[0124] Other aspects of the above techniques for forming thin film plated terminations are described in U.S. Patent Nos. 7,177,137 and 7,463,474 to Ritter et al., which are incorporated herein by reference for all purposes. It should be understood that additional techniques for forming capacitor terminals may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming terminations by plating, magnetic, masking, electrophoresis / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming thick or thin film conductive layers.

[0125] Example

[0126] Example 1

[0127] The multilayer capacitor as defined herein is manufactured according to the specifications indicated below and in the table below.

[0128] In particular, the chip thickness of the manufactured capacitor is 20 mils, the distance from the active electrode area to the shield area is 2 mils (10% of the total thickness), and the distance from the active electrode area to the surface is 2.7 mils (13.5% of the total thickness). For some examples, the anchor electrode does not include a stepped portion as defined herein.

[0129]

[0130]

[0131] The insertion loss of each capacitor was measured over a wide operating frequency range (i.e., 4 GHz to 40 GHz). This insertion loss was measured using capacitors in both horizontal and vertical configurations, and two samples were tested for each data point. The ranges in the table below represent the maximum and minimum insertion losses over the frequency range.

[0132]

[0133]

[0134] Example 2

[0135] The multilayer capacitor as defined herein is manufactured according to the specifications indicated below and in the table below.

[0136]

[0137]

[0138] The insertion loss of each capacitor was measured over a wide operating frequency range (i.e., 4 GHz to 40 GHz). This insertion loss was measured with the capacitor in a horizontal configuration, so that the electrode layers were parallel to the mounting surface and stacked in a vertical orientation.

[0139]

[0140] Without departing from the spirit and scope of the present invention, those of ordinary skill in the art may practice these and other modifications and variations of the present invention. In addition, it should be understood that the various aspects of the various embodiments may be interchangeable in whole or in part. In addition, those of ordinary skill in the art will appreciate that the above description is merely exemplary and is not intended to limit the present invention further described in the appended claims.

Claims

1. A multilayer ceramic capacitor comprising: a first external terminal disposed along a first end of the capacitor; a second external terminal disposed along a second end of the capacitor, the second end being opposite the first end in a longitudinal direction; an active electrode region comprising alternating dielectric layers and active electrode layers; as well as a shielding electrode region including at least two shielding electrodes, the at least two shielding electrodes being spaced apart in the longitudinal direction by a shielding layer gap; in: A distance from the active electrode region to the shielding electrode region is 4% to 20% of a thickness of the capacitor between a top surface and a bottom surface opposite the top surface.

2. The multilayer ceramic capacitor of claim 1 , wherein the at least two shielding electrodes include a first shielding electrode connected to the first external terminal and a second shielding electrode connected to the second external terminal, and the second shielding electrode is substantially aligned with the first shielding electrode in a Z direction perpendicular to the longitudinal direction, and each of the first shielding electrode and the second shielding electrode has corresponding unconnected ends, which are separated by the shielding layer gap in the longitudinal direction.

3. The multilayer ceramic capacitor of claim 1, wherein a distance from the active electrode region to the top surface ranges from 4% to 20% of a thickness of the capacitor.

4. The multilayer ceramic capacitor of claim 1, wherein a distance from the active electrode area to the top surface is from 1.5 mils to 3.2 mils.

5. The multilayer ceramic capacitor of claim 1, wherein a distance from the active electrode region to the shield electrode region ranges from 1.5 mils to 3.2 mils.

6. The multilayer ceramic capacitor according to claim 1, wherein: The capacitor has an insertion loss from 0.25 dB to 0.55 dB when measured over a frequency range from 33 GHz to 40 GHz.

7. The multilayer ceramic capacitor according to claim 1, wherein: The capacitor has an insertion loss from 0.20 dB to 0.35 dB when measured over a frequency range from 23 GHz to 30 GHz.

8. The multilayer ceramic capacitor according to claim 1, wherein: The capacitor has an insertion loss from 0.15 dB to 0.40 dB when measured over a frequency range from 13 GHz to 20 GHz.

9. The multilayer ceramic capacitor according to claim 1, wherein: The capacitor has an insertion loss from 0.1 dB to 0.25 dB when measured over a frequency range from 4 GHz to 10 GHz.

10. The multilayer ceramic capacitor of claim 1, wherein the active electrode layer comprises a first electrode electrically connected to the first external terminal, the first electrode having a first electrode arm, the first electrode arm including a main body portion having a lateral edge extending from a first end of the multilayer capacitor, and a stepped portion having a lateral edge offset from a lateral edge of the main body portion; and A second electrode is electrically connected to the second external terminal.

11. The multilayer ceramic capacitor of claim 10, wherein the first electrode arm and the second electrode are spaced apart to form a body gap distance between a body portion of the first electrode arm and the second electrode and a step gap distance between a step portion of the first electrode arm and the second electrode. 12 . The multilayer ceramic capacitor of claim 11 , wherein the body gap distance is from 5% to 60% of a length of the capacitor from the first external terminal to the second external terminal.

13. The multilayer ceramic capacitor of claim 11, wherein the body gap distance is more than 50% of the length of the body portion of the first electrode arm.

14. The multilayer ceramic capacitor of claim 11, wherein the step gap distance is from 1% to 30% of a length of the capacitor from the first external terminal to the second external terminal. 15 . The multilayer ceramic capacitor of claim 11 , wherein the step gap distance is from 5% to 50% of the length of the step portion of the first electrode arm.

16. The multilayer ceramic capacitor of claim 11, wherein the step gap distance is from 5% to 70% of the body gap distance.

17. The multilayer ceramic capacitor of claim 10, wherein the stepped portion of the first electrode arm is offset inwardly from a lateral edge of the body portion toward a lateral centerline of at least one of the electrode layers.

18. The multilayer ceramic capacitor of claim 10, wherein the stepped portion of the first electrode arm is offset outwardly from a lateral edge of the body portion away from a lateral centerline of at least one of the electrode layers.

19. The multilayer ceramic capacitor of claim 10, wherein each lateral edge of the step portion is offset from each lateral edge of the body portion.

20. A multilayer ceramic capacitor as described in claim 10, wherein the second electrode includes a second electrode arm, the second electrode arm includes a main body portion and a step portion, the main body portion has a lateral edge extending from the second end of the multilayer capacitor, and the step portion has a lateral edge offset from the lateral edge of the main body portion.

21. A multilayer ceramic capacitor comprising: a first external terminal disposed along a first end of the capacitor; a second external terminal disposed along a second end of the capacitor, the second end being opposite the first end in a longitudinal direction; an active electrode region comprising alternating dielectric layers and active electrode layers; as well as a shielding electrode region including at least two shielding electrodes, wherein the at least two shielding electrodes are separated in the longitudinal direction by a shielding layer gap, Wherein, on at least one of the top surface or the bottom surface, the shielding layer gap ranges from 3% to 60% of the external terminal gap between the first external terminal and the second external terminal in the longitudinal direction.

22. A multilayer ceramic capacitor as described in claim 21, wherein the at least two shielding electrodes include a first shielding electrode connected to the first external terminal and a second shielding electrode connected to the second external terminal, and the second shielding electrode is approximately aligned with the first shielding electrode in a Z direction perpendicular to the longitudinal direction, and each of the first shielding electrode and the second shielding electrode has corresponding unconnected ends, which are separated by the shielding layer gap in the longitudinal direction.

23. The multilayer ceramic capacitor of claim 21, wherein a distance from the active electrode region to the top surface ranges from 4% to 20% of a thickness of the capacitor.

24. The multilayer ceramic capacitor of claim 21 wherein a distance from the active electrode area to the top surface is from 1.5 mils to 3.2 mils.

25. The multilayer ceramic capacitor of claim 21, wherein a distance from the active electrode region to the shield electrode region ranges from 1.5 mils to 3.2 mils.

26. The multilayer ceramic capacitor of claim 21, wherein: The capacitor has an insertion loss from 0.25 dB to 0.55 dB when measured over a frequency range from 33 GHz to 40 GHz.

27. The multilayer ceramic capacitor of claim 21, wherein: The capacitor has an insertion loss from 0.20 dB to 0.35 dB when measured over a frequency range from 23 GHz to 30 GHz.

28. The multilayer ceramic capacitor of claim 21, wherein: The capacitor has an insertion loss from 0.15 dB to 0.40 dB when measured over a frequency range from 13 GHz to 20 GHz.

29. The multilayer ceramic capacitor of claim 21, wherein: The capacitor has an insertion loss from 0.1 dB to 0.25 dB when measured over a frequency range from 4 GHz to 10 GHz.

30. The multilayer ceramic capacitor of claim 21, wherein the shield electrode has a generally rectangular configuration. 31 . The multilayer ceramic capacitor of claim 21 , wherein the shield electrode has a step at an edge of the shield electrode, the edge being opposite to an edge of the shield electrode adjacent to an external terminal.

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