A method of manufacturing a transistor

Abstract

The application discloses a transistor manufacturing method, and relates to the technical field of semiconductors, and is used for improving the working performance of a transistor including a channel when the material of the channel contains germanium. The transistor manufacturing method comprises the following steps: forming a channel included in a transistor and a silicon layer located at least on the channel on a substrate. The material of the channel contains germanium. The silicon layer contains germanium atoms diffused from the channel. The silicon layer is subjected to alternating low-temperature oxidation treatment and annealing treatment until the concentration of the germanium atoms in the silicon layer is reduced to a preset threshold.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a manufacturing method of a transistor. BACKGROUND

[0002] In the field of semiconductor, germanium-silicon or germanium material has higher carrier mobility. Meanwhile, the band gap of germanium is smaller than that of silicon. Based on this, when a transistor including a channel is manufactured by using germanium-silicon or germanium material, it is beneficial for the transistor to have greater drive current, faster switching speed and lower drive voltage, so that germanium-silicon or germanium material becomes one of the main candidates for channel material.

[0003] However, when a transistor including a channel is manufactured by using germanium-silicon or germanium material by using the existing manufacturing method, it is easy to cause the transistor to have poor working performance. SUMMARY

[0004] The present application aims to provide a manufacturing method of a transistor, which is used to improve the working performance of a transistor including a channel when the material of the channel contains germanium.

[0005] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of a transistor, which comprises:

[0006] A channel included in a transistor and a silicon layer at least located on the channel are formed on a substrate. The material of the channel contains germanium. The silicon layer contains germanium atoms diffused from the channel.

[0007] The silicon layer is subjected to alternating low-temperature oxidation treatment and annealing treatment until the concentration of germanium atoms in the silicon layer is reduced to a preset threshold.

[0008] Compared with the prior art, the transistor manufactured by the transistor manufacturing method provided by the application comprises a channel material containing germanium. After the channel is formed on the substrate, a silicon layer is formed on at least the channel. At this time, the silicon layer can isolate the channel from the external environment, thereby solving the problem that the interface state of the channel is high due to the direct exposure of germanium atoms in the channel to the external environment to form unstable and easily hydrolyzed germanium oxide in the manufacturing process. In addition, in the actual manufacturing process, when the silicon layer is formed on the channel, the germanium atoms in the channel will diffuse into the silicon layer due to factors such as high formation temperature, and the part of germanium atoms is still easy to react with water vapor in the air to form the above-mentioned germanium oxide and cause poor interface state. In this case, the manufacturing method provided by the application further comprises alternating low-temperature oxidation treatment and annealing treatment on the silicon layer after the silicon layer is formed. Specifically, the concentration of germanium atoms in the silicon layer is reduced to a preset threshold value by reacting part of germanium atoms and silicon atoms in the silicon layer with oxygen atoms through low-temperature oxidation treatment, and volatilizing the germanium atoms reacted with oxygen atoms through annealing treatment, so as to obtain high-quality interface characteristics, improve the electrical performance of the transistor, and further improve the working performance of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0010] Figure 1 A flow chart of the transistor manufacturing method provided by the embodiment of the application;

[0011] Figure 2 A structure sectional view of the channel and the silicon layer formed on the substrate in the case that the transistor manufactured in the embodiment of the application is a planar transistor;

[0012] Figure 3 A structure sectional view of the channel and the silicon layer formed on the substrate in the case that the transistor manufactured in the embodiment of the application is a fin field effect transistor along the length direction of the channel;

[0013] Figure 4 A structure sectional view of the channel and the silicon layer formed on the substrate in the case that the transistor manufactured in the embodiment of the application is a fin field effect transistor perpendicular to the channel direction;

[0014] Figure 5 A structure sectional view of the channel and the silicon layer formed on the substrate in the case that the transistor manufactured in the embodiment of the application is a ring gate transistor along the length direction of the channel;

[0015] Figure 6A cross-sectional view of a structure perpendicular to a channel direction after forming a channel and a silicon layer on a substrate in the case where a transistor manufactured in the embodiment of the present application is a ring gate transistor;

[0016] Figure 7 A cross-sectional view of a structure after performing a low-temperature oxidation process on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a planar transistor;

[0017] Figure 8 A cross-sectional view of a structure perpendicular to a channel direction after performing a low-temperature oxidation process on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a fin field effect transistor;

[0018] Figure 9 A cross-sectional view of a structure perpendicular to a channel direction after performing a low-temperature oxidation process on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a ring gate transistor;

[0019] Figure 10 A cross-sectional view of a structure after performing an annealing process on a silicon layer on which an oxide mixed layer is formed in the case where a transistor manufactured in the embodiment of the present application is a planar transistor;

[0020] Figure 11 A cross-sectional view of a structure perpendicular to a channel direction after performing an annealing process on a silicon layer on which an oxide mixed layer is formed in the case where a transistor manufactured in the embodiment of the present application is a fin field effect transistor;

[0021] Figure 12 A cross-sectional view of a structure perpendicular to a channel direction after performing an annealing process on a silicon layer on which an oxide mixed layer is formed in the case where a transistor manufactured in the embodiment of the present application is a ring gate transistor;

[0022] Figure 13 A cross-sectional view of a structure after performing an annealing process and a low-temperature oxidation process alternately on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a planar transistor;

[0023] Figure 14 A cross-sectional view of a structure perpendicular to a channel direction after performing an annealing process and a low-temperature oxidation process alternately on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a fin field effect transistor;

[0024] Figure 15 A cross-sectional view of a structure perpendicular to a channel direction after performing an annealing process and a low-temperature oxidation process alternately on a silicon layer in the case where a transistor manufactured in the embodiment of the present application is a ring gate transistor;

[0025] Figure 16A cross-sectional view of a structure after forming the interface layer on the silicon layer in the case where the transistor manufactured in the embodiment of the present application is a planar transistor;

[0026] Figure 17 A cross-sectional view of a structure perpendicular to the channel direction after forming the interface layer on the silicon layer in the case where the transistor manufactured in the embodiment of the present application is a fin field effect transistor;

[0027] Figure 18 A cross-sectional view of a structure perpendicular to the channel direction after forming the interface layer on the silicon layer in the case where the transistor manufactured in the embodiment of the present application is a ring gate transistor.

[0028] Reference numerals: 11 is a substrate, 12 is a channel, 13 is a silicon layer, 14 is an oxide mixed layer, 15 is a second oxide layer, 151 is a first oxide layer, 16 is an interface layer, 17 is a shallow trench isolation, 18 is a source region, 19 is a drain region, 20 is a dielectric layer, and 21 is a side wall. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0030] In the drawings, various structural schematic diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details can be omitted. The shapes of various regions, layers shown in the drawings, and their relative sizes, positional relationships are merely exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, relative positions can be additionally designed by those skilled in the art according to actual needs.

[0031] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application, and are not intended to limit the present application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] In the semiconductor field, germanium-silicon or germanium materials exhibit high carrier mobility. Furthermore, germanium has a smaller bandgap than silicon. Therefore, when using germanium-silicon or germanium materials to fabricate the channels of transistors, it is advantageous for the transistors to have larger drive currents, faster switching speeds, and lower drive voltages, making germanium-silicon or germanium materials one of the leading candidates for channel materials.

[0035] However, in practical applications, when using existing manufacturing methods and using germanium-silicon or germanium materials to manufacture the channels of transistors, an unstable and easily hydrolyzed germanium oxide (GeO) layer is easily formed on the surface of the channels made of germanium-silicon or germanium materials. This increases the dangling bonds at the interface, resulting in a higher interface state in the channel, which leads to a decrease in the carrier mobility in the channel and consequently a poor transistor performance.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a transistor. In this method, after forming a channel for the transistor and a silicon layer at least on the channel on a substrate, the silicon layer is subjected to alternating cycles of low-temperature oxidation and annealing until the concentration of germanium atoms in the silicon layer decreases to a preset threshold, thereby obtaining superior interface characteristics and improving the transistor's operating performance.

[0037] like Figure 1 As shown, this embodiment of the invention provides a method for manufacturing a transistor. The device structure type of the transistor manufactured by this method can be selected according to actual needs. For example, the transistor manufactured by this method can be a planar transistor, a fin field-effect transistor, or a gate-around transistor.

[0038] The following will be based on Figures 2 to 18 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this transistor includes the following steps:

[0039] like Figures 2 to 6 As shown, a transistor including a channel 12 and a silicon layer 13 at least located on the channel 12 are formed on the substrate 11. The channel 12 is made of germanium. The silicon layer 13 contains germanium atoms diffused from the channel 12.

[0040] Specifically, the aforementioned substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, or other semiconductor substrates without any structures formed thereon, or it can be a semiconductor substrate with some structures formed thereon. Specifically, the material and structure of the substrate can be set according to actual needs. For example, if the manufactured transistor is a transistor located in the second or higher layer of an integrated circuit, the aforementioned substrate can include a semiconductor substrate, at least one transistor layer formed on the semiconductor substrate, and an interlayer dielectric layer separating adjacent layers, etc. In some cases, such as... Figures 2 to 6 As shown, a shallow trench isolation 17, sidewalls 21, a source region 18, a drain region 19, and a dielectric layer 20 can also be formed on the aforementioned substrate. Specifically, the shallow trench isolation 17 is used to define the active region of the substrate 11. The material contained in the shallow trench isolation 17 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The source region 18 and drain region 19 are respectively formed on both sides of the channel 12 along its length direction. The material of the source region 18 and drain region 19 can be a semiconductor material such as silicon, germanium silicon, or germanium. The dielectric layer 20 covers the substrate, and the top height of the dielectric layer 20 is equal to the maximum top height of the sidewall 21. The sidewall 21 is formed between the dielectric layer 20, the silicon layer 13, and the gate formation region. The gate formation region is the region where the gate stack of the transistor is formed. The material of the sidewall 21 and the dielectric layer 20 can be an insulating material such as silicon dioxide or silicon nitride.

[0041] As for the material of the aforementioned channel, it can specifically be Si. 1-x Ge x Semiconductor materials containing germanium, where 0 < x ≤ 1. For example, the channel material can be Si. 0.2 Ge 0.8 Si 0.5 Ge 0.5 Or Ge, etc.

[0042] The thickness of the silicon layer can be set according to the actual application scenario, and no specific limitation is made here. For example, the thickness of the silicon layer can be greater than or equal to 1 nm and less than or equal to 3 nm. In this case, the silicon layer formed on the channel is relatively thin. Based on this, since the bandgap of germanium is smaller than that of silicon, when the silicon layer is relatively thin, the channel containing germanium can act as a carrier-binding structure. That is to say, when the transistor is in operation, the source and drain regions will only conduct through the germanium-containing channel, and not through the silicon layer formed on the channel. Thus, the silicon layer can isolate the germanium-containing channel from the external environment while preventing the formation of parasitic channels, further improving the electrical performance of the manufactured transistor.

[0043] Understandably, the specific structure of the channels included in the transistors will vary depending on the type of transistor device structure. Correspondingly, the manufacturing processes for forming the channels on the substrate and the silicon layer on the channels will also differ.

[0044] For example: Figure 2 As shown, when the transistor is a planar transistor, the channel 12 can be formed on the surface of the substrate 11 or on the substrate 11. The silicon layer 13 is located on the surface of the channel 12 facing away from the substrate 11. Specifically, the exact location of the channel 12 on the substrate 11 can be set according to actual needs, and is not specifically limited here.

[0045] In practical applications, taking a substrate without other structures as an example, and the channel being formed on the surface of the substrate, the formation of a planar transistor on the substrate, including the channel and silicon layer, can be briefly explained. First, processes such as deposition and selective etching can be used to form a sacrificial gate and sidewalls on the portion of the substrate located in the channel formation region. The sidewalls are located at least on both sides of the sacrificial gate along its width. Next, processes such as plasma implantation are used to form the source and drain regions on the portions of the substrate located on both sides of the sacrificial gate along its width, at which point the portion of the substrate located in the channel formation region forms the channel. Then, a dielectric layer is formed covering the substrate. The top of this dielectric layer is flush with the top of the sacrificial gate. The sacrificial gate is then removed, exposing the surface of the channel facing away from the substrate. Finally, a silicon layer can be formed on the surface of the channel facing away from the substrate using processes such as chemical vapor deposition or molecular beam epitaxy.

[0046] For example: Figure 3 and Figure 4 As shown, when the transistor is a fin field-effect transistor, the channel 12 is a fin-shaped structure formed on the substrate 11. A silicon layer 13 covers the outer periphery of the channel 12.

[0047] In actual application, in the case that the substrate is a substrate without other structures formed thereon and the substrate is made of the same material as the channel, the substrate can be etched by photolithography and dry etching to form a first fin on the substrate. Then, a shallow trench isolation is formed on the substrate exposed outside the first fin. The part of the first fin exposed outside the shallow trench isolation is a second fin. The second fin has a source region forming area, a drain region forming area, and a transition area between the source region forming area and the drain region forming area. Then, a sacrificial gate and a sidewall covering at least the outer periphery of the transition area are formed. The sidewall is formed at least on both sides of the sacrificial gate in the width direction. After removing the part of the second fin in the source region forming area and the drain region forming area, a source region and a drain region included in a fin field effect transistor are formed in the area where the source region forming area and the drain region forming area are located, respectively. Then, the dielectric layer is formed by the process described above, and the sacrificial gate is removed to expose the top and both sides of the channel in the width direction. Finally, a silicon layer covering the outer periphery of the channel can be formed by chemical vapor deposition or molecular beam epitaxy.

[0048] For another example, as shown in FIGS. 1A and 1B, in the case that the transistor is a ring gate transistor, the channel 12 includes at least one layer of nanowire or sheet formed above the substrate 11. The silicon layer 13 at least surrounds the outer periphery of each layer of nanowire or sheet. Among them, the silicon layer can only surround the outer periphery of each layer of nanowire or sheet. Alternatively, as shown in FIGS. 2A and 2B, the silicon layer 13 not only surrounds the outer periphery of each layer of nanowire or sheet but also is formed on the part of the substrate 11 located below the channel 12. In addition, the number of layers of nanowire or sheet included in the channel 12 can be set according to actual needs, as long as it can be applied to the manufacturing method of the transistor provided in the embodiments of the present application. Figure 5 Figure 6 Specifically, how to form the channel of the ring gate transistor on the substrate can refer to the manufacturing process of the channel of the fin field effect transistor described above. The difference is that the channel of the ring gate transistor needs to form a stack with a number of layers equal to the number of layers of nanowire or sheet on the substrate, and etch the stack and the substrate to obtain a first fin. Each layer of the stack includes a sacrificial layer and a channel layer on the sacrificial layer. In addition, after removing the sacrificial gate, the part of the sacrificial layer in the transition area also needs to be removed, so that the part of the channel layer in the transition area forms a nanowire or sheet. Figure 5 Figure 6

[0049] In actual application, in the case that the substrate is a substrate without other structures formed thereon and the substrate is made of the same material as the channel, the substrate can be etched by photolithography and dry etching to form a first fin on the substrate. Then, a shallow trench isolation is formed on the substrate exposed outside the first fin. The part of the first fin exposed outside the shallow trench isolation is a second fin. The second fin has a source region forming area, a drain region forming area, and a transition area between the source region forming area and the drain region forming area. Then, a sacrificial gate and a sidewall covering at least the outer periphery of the transition area are formed. The sidewall is formed at least on both sides of the sacrificial gate in the width direction. After removing the part of the second fin in the source region forming area and the drain region forming area, a source region and a drain region included in a fin field effect transistor are formed in the area where the source region forming area and the drain region forming area are located, respectively. Then, the dielectric layer is formed by the process described above, and the sacrificial gate is removed to expose the top and both sides of the channel in the width direction. Finally, a silicon layer covering the outer periphery of the channel can be formed by chemical vapor deposition or molecular beam epitaxy.

[0050] ​​​It is worth noting that, as described above, the transistor manufactured by the transistor manufacturing method provided in this embodiment of the invention includes a channel made of germanium. Furthermore, after the channel is formed on the substrate, a silicon layer is formed at least on the channel. In this case, the silicon layer can isolate the channel from the external environment, thereby solving the problem of high interface states in the channel caused by germanium atoms in the channel being directly exposed to the external environment during the manufacturing process, forming unstable and easily hydrolyzed germanium oxide.

[0051] It should be noted that in the above-described channel formation process, a post-gate process is used to pre-form a sacrificial gate so that a high-dielectric-constant gate dielectric layer and a metal gate can be sequentially formed in the gate formation region after appropriate processing. It should be understood that a gate-first process can also be used to form the gate stack of the transistor after performing the corresponding operations. Furthermore, the above-described channels and silicon layers can be formed in various ways. How these structures are formed is not the main feature of this invention; therefore, only a brief description is given in this specification to enable those skilled in the art to easily implement the invention. Those skilled in the art can readily conceive of other methods for fabricating the above structures.

[0052] like Figures 7 to 15 As shown, the silicon layer 13 is subjected to alternating cycles of low-temperature oxidation and annealing until the concentration of germanium atoms in the silicon layer 13 is reduced to a preset threshold.

[0053] It is understandable that during the actual manufacturing process, when the silicon layer is formed on the aforementioned channel, factors such as the high formation temperature can cause germanium atoms in the channel to diffuse into the silicon layer. These germanium atoms are still prone to reacting with water vapor in the air to form germanium oxide, resulting in poor interface states. In this case, the manufacturing method provided in this embodiment of the invention, after forming the silicon layer, also performs alternating low-temperature oxidation and annealing treatments on the silicon layer to reduce the concentration of germanium atoms in the silicon layer to a preset threshold, preventing the remaining germanium atoms in the silicon layer from affecting the electrical performance of the transistor. Based on this, the magnitude of the preset threshold varies depending on factors such as the initial concentration of germanium diffused into the silicon layer during the manufacturing process and the concentration of reactants such as water vapor in the manufacturing environment that easily react with germanium atoms to form germanium oxide. For example, when the concentration of the aforementioned reactants such as water vapor in the manufacturing environment is very low, the magnitude of the preset threshold can be appropriately increased.

[0054] For example, the aforementioned preset threshold can be equal to one millionth of the silicon atom content in the silicon layer.

[0055] Furthermore, the processing conditions for the aforementioned low-temperature oxidation and annealing processes can be set according to the initial concentration of germanium in the silicon layer and actual requirements, and are not specifically limited here. For example, the processing temperature for the aforementioned low-temperature oxidation process can be greater than 0 and less than or equal to 400°C. In this case, the concentration of germanium atoms in the silicon layer can be reduced through low-temperature oxidation, while preventing germanium atoms in the channel from continuing to diffuse into the silicon layer due to excessively high temperatures, thereby improving the manufacturing efficiency and reliability of the transistor manufacturing method provided in this embodiment of the invention. Additionally, the low-temperature oxidation process on the silicon layer can be performed in an ozone gas atmosphere. The aforementioned ozone gas can be ozone gas. Alternatively, the aforementioned ozone gas can be a mixture of ozone and oxygen.

[0056] For example, the silicon layer can be annealed in a vacuum environment or a protective gas atmosphere. The annealing temperature can be between 450°C and 650°C. The protective gas is nitrogen or an inert gas. Preferably, the annealing temperature is 500°C.

[0057] In one example, such as Figures 7 to 15 As shown, the alternating low-temperature oxidation and annealing processes performed on the silicon layer 13 described above may include the following steps: Figures 7 to 9 As shown, the silicon layer 13 undergoes a low-temperature oxidation process to reduce the concentration of germanium atoms in the silicon layer 13, and an oxide mixture layer 14 is formed on the surface of the silicon layer 13. The oxide mixture layer 14 is made of germanium oxide and silicon oxide. Figures 10 to 12 As shown, the silicon layer 13, on which the oxide mixed layer 14 is formed, is annealed to form a first oxide layer 151, and to move at least a portion of the remaining germanium atoms in the silicon layer 13 to the surface of the silicon layer 13 near the first oxide layer 151. The first oxide layer 151 is made of silicon oxide. Figures 13 to 15 As shown, the above operation is repeated until the concentration of germanium atoms in the silicon layer 13 decreases to a preset threshold. After the above-described alternating cycle of low-temperature oxidation and annealing, a second oxide layer 15 is formed on the silicon layer 13. The second oxide layer 15 includes at least one first oxide layer 151.

[0058] Specifically, the germanium oxide in the aforementioned oxide mixed layer can be germanium oxide and / or germanium dioxide. The silicon oxide in the oxide mixed layer and the first oxide layer can be silicon oxide and / or silicon dioxide. Furthermore, in practical applications, the number of times the above operations are performed needs to be determined based on the relationship between the concentration of germanium atoms in the silicon layer and a preset threshold after sequentially performing one low-temperature oxidation treatment and one annealing treatment. For example, if the concentration of germanium atoms in the silicon layer is lower than the preset threshold after sequentially performing a second low-temperature oxidation treatment and a second annealing treatment, only two operations are required.

[0059] It is understood that if the above operation only needs to be performed once, the second oxide layer consists of only one first oxide layer. If the above operation needs to be performed at least twice, the second oxide layer can be a silicon oxide film formed on a silicon layer by alternating cycles of low-temperature oxidation and annealing. In this case, the second oxide layer consists of at least two first oxide layers.

[0060] As mentioned above, Figures 13 to 15 As shown, since a first oxide layer 151 is formed on silicon layer 13 after each cycle of low-temperature oxidation and annealing, if the above operation is performed more than or equal to 2 times, a first oxide layer 151 with more than or equal to 2 layers will be formed on silicon layer 13 (i.e., the second oxide layer 15 includes at least two first oxide layers 151). In this case, the thickness of the second oxide layer 15 on silicon layer 13 is relatively large. Based on this, as... Figures 2 to 6 As shown, when the above operation is performed twice or more, the transistor manufacturing method further includes the step of removing the first oxide layer before performing low-temperature oxidation on the silicon layer 13. That is, the first oxide layer on the silicon layer 13 is removed before each subsequent operation to facilitate contact and reaction between the silicon layer 13 and ozone gas, etc., to form an oxide mixture layer during the next low-temperature oxidation process, reducing the reaction difficulty and improving reaction efficiency. In this case, even if the above operation is performed twice or more, the second oxide layer finally formed on the silicon layer 13 consists of only one layer of the first oxide layer.

[0061] For example, after alternating cycles of low-temperature oxidation and annealing treatments on the silicon layer, the above-mentioned transistor manufacturing method may further include the steps of: Figures 2 to 6 As shown, the second oxide layer is removed. Figures 16 to 18 As shown, an interface layer 16 is formed on the silicon layer 13 to further improve the interface state of the silicon layer 13 and enhance the electrical performance of the transistor.

[0062] Specifically, the processes and conditions for removing the second oxide layer and forming the interface layer can be set according to actual needs, and no specific limitations are made here.

[0063] For example, such as Figures 16 to 18 As shown, when the thickness of the second oxide layer is greater than 0 and less than or equal to 0.7 nm, the second oxide layer is an interface layer 16 located on the silicon layer 13.

[0064] In actual application, if the thickness of the second oxide layer formed on the silicon layer after the above operation meets the thickness requirement of the interface layer in the actual application scenario, the second oxide layer can be directly used as the interface layer to simplify the manufacturing process of the transistor and improve the manufacturing efficiency. The thickness of the interface layer can also be other suitable values, and is not limited to the above range.

[0065] In addition, after forming the silicon layer or after forming the interface layer, a gate stack included in the transistor can be formed on the silicon layer or the interface layer by using a process such as atomic layer deposition. The gate stack includes a gate dielectric layer made of an insulating material such as HfO2, ZrO2, TiO2, or Al2O3, and a gate electrode made of a conductive material such as TiN, TaN, or TiSiN, to obtain the transistor.

[0066] From the above, in the manufacturing method of the transistor provided by the embodiments of the present application, part of the germanium atoms and silicon atoms in the silicon layer can be reacted with oxygen atoms by low-temperature oxidation treatment to form an oxide mixed layer. Then, the Ge-O bond is broken by annealing treatment. The O in the original Ge-O bond further reacts with Si in the silicon layer or Si in the silicon oxide of the oxide mixed layer, which enhances the oxide strength of silicon and is more likely to form high-quality Si 4+ The Ge in the original Ge-O bond is volatilized into the reaction environment, so that the concentration of germanium atoms in the silicon layer is reduced to a preset threshold, thereby reducing or eliminating the precipitation of Ge atoms in the silicon layer. In other words, the problem of poor interface state caused by the reaction of germanium atoms in the silicon layer with water vapor in the external environment can be solved, thereby improving the electrical performance of the transistor and improving the working performance of the transistor.

[0067] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, and the like with the desired shape. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0068] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method of manufacturing a transistor, characterized by, include: The transistor includes a channel and a silicon layer at least located on the channel, formed on a substrate; the channel is made of germanium; the silicon layer contains germanium atoms diffused from the channel; the thickness of the silicon layer is greater than or equal to 1 nm and less than or equal to 3 nm; The silicon layer is subjected to alternating cycles of low-temperature oxidation and annealing until the concentration of germanium atoms in the silicon layer decreases to a preset threshold. The low-temperature oxidation process is performed at a temperature greater than 0°C and less than or equal to 400°C in an ozone gas atmosphere. The annealing process is then performed on the silicon layer in a vacuum environment or a protective gas atmosphere at a temperature of 450°C to 650°C. The alternating low-temperature oxidation and annealing treatment of the silicon layer includes: The silicon layer is subjected to the low-temperature oxidation treatment to reduce the concentration of germanium atoms in the silicon layer and to form an oxide mixture layer on the surface of the silicon layer; the oxide mixture layer is made of germanium oxide and silicon oxide. The silicon layer on which the oxide mixture layer is formed is subjected to the annealing treatment to break the Ge-O bonds in the germanium oxide; after the annealing treatment, the oxide mixture layer forms a first oxide layer, and at least some of the remaining germanium atoms in the silicon layer move to the surface of the silicon layer near the first oxide layer and volatilize; the material of the first oxide layer is the silicon oxide; Repeat the above operation until the concentration of germanium atoms in the silicon layer decreases to the preset threshold; after alternating cycles of the low-temperature oxidation treatment and the annealing treatment, a second oxide layer is formed on the silicon layer; the second oxide layer includes at least one first oxide layer.

2. The method of manufacturing a transistor according to claim 1, wherein If the above operation is performed more than or equal to 2 times, the method for manufacturing the transistor further includes removing the first oxide layer before performing the low-temperature oxidation treatment on the silicon layer.

3. The method of manufacturing a transistor according to claim 1 or 2, wherein The method for manufacturing the transistor, after alternating cycles of low-temperature oxidation and annealing of the silicon layer, further includes: Remove the second oxide layer; An interface layer is formed on the silicon layer.

4. The method of manufacturing a transistor according to claim 1 or 2, wherein When the thickness of the second oxide layer is greater than 0 and less than or equal to 0.7 nm, the second oxide layer is an interface layer located on the silicon layer.

5. The method of manufacturing a transistor according to claim 1 or 2, wherein The ozone gas is ozone gas; or, the ozone gas is a mixture of ozone and oxygen gas.

6. The method of manufacturing a transistor according to claim 1 or 2, wherein The protective gas is nitrogen or an inert gas.

7. The method of manufacturing a transistor according to claim 1 or 2, wherein The transistor is a planar transistor, a fin field-effect transistor, or a gate-around transistor.

8. The method of manufacturing a transistor according to claim 1 or 2, wherein When the transistor is a planar transistor, the channel is formed on the surface of the substrate or on the substrate, and the silicon layer is located on the surface of the channel away from the substrate; or, When the transistor is a fin field-effect transistor, the channel is a fin-shaped structure formed on the substrate; the silicon layer covers the outer periphery of the channel; or, In the case where the transistor is a gate-around transistor, the channel includes at least one layer of nanowires or sheets formed over the substrate; the silicon layer at least surrounds the outer periphery of each layer of nanowires or sheets.

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