Electroluminescent display devices

Abstract

An electroluminescent display device is provided. The electroluminescent display device includes: a substrate including a display area and a non-display area disposed around the display area; a gate driver disposed on the non-display area; and a plurality of pixels disposed on the display area, the pixels being configured to receive a driving signal. Each pixel includes: an electroluminescent diode; a driving transistor connected to the electroluminescent diode and providing current to the electroluminescent diode; and at least one switching transistor disposed in each pixel. The channel region of the driving transistor and the channel region of the at least one switching transistor are formed by patterning a semiconductor layer. The size of the channel region of the driving transistor differs from the size of the channel region of the at least one switching transistor, and the deviation between the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the at least one switching transistor is less than or equal to 10°.

Description

[0001] This application is a divisional application of the invention patent application filed on June 6, 2017, with application number 201710419260.6 and entitled "Electronic Light Emitting Display Device and Preparation Method Thereof".

[0002] Cross-reference to related applications

[0003] This application claims priority to Korean Application No. 10-2016-0182953, filed on December 29, 2016, which is incorporated herein by reference in its entirety. Technical Field

[0004] This disclosure relates to a display device, and more particularly, to an electroluminescent display device and a method for manufacturing the same. Background Technology

[0005] An electroluminescent element is a self-emissive element that includes an anode, a cathode, and an electroluminescent layer formed between the anode and cathode. The electroluminescent layer comprises a hole transport layer (HTL), an emissive layer (EML), and an electron transport layer (ETL). When a voltage is applied to the anode and cathode, excitons are generated by combining holes transported via the HTL and electrons transported via the ETL, thereby producing visible light in the EML. Active matrix electroluminescent display devices, which include a matrix of self-emissive electroluminescent elements, offer advantages such as fast response time, luminous efficiency, brightness, and wide viewing angle. For these reasons, electroluminescent display devices are widely used.

[0006] An electroluminescent display device comprises multiple pixels (P) arranged in a matrix, each pixel including an electroluminescent diode (ELD) that controls the brightness of the multiple pixels based on the grayscale levels of video data. Each pixel further includes a driving transistor and at least one switching transistor. The driving transistor controls the driving current supplied to the electroluminescent diode based on the potential difference between its gate and source, while the switching transistor controls the potential difference between the gate and source of the driving transistor. The driving current is determined based on the potential difference between the gate and source of the driving transistor and the threshold voltage of the driving transistor. The pixel brightness is proportional to the amount of driving current supplied to the electroluminescent diode.

[0007] Therefore, the potential difference between the gate and source of the driving transistor must be maintained in a precise and stable manner to display pixels according to the desired brightness value. However, due to various reasons, undesirable deviations may exist in the voltage of each electrode.

[0008] For example, there will be transistor threshold voltage (Vth) deviation. Furthermore, gate lines, light-emitting lines, and data lines will generate parasitic capacitances with any adjacent electrodes. As a result, when the gate signal, light-emitting signal, and data signal are changed, kickback voltages are generated at adjacent electrodes. At this time, for the adjacent electrodes that generate kickback voltages, the kickback voltages will be generated in a non-uniform manner according to their positional relationship.

[0009] Attempts have been made to compensate for this threshold voltage deviation (ΔVth) by implementing internal or external compensation circuitry. Summary of the Invention

[0010] Therefore, this disclosure relates to an electroluminescent display device and a method for manufacturing the same, which substantially avoids one or more problems caused by the limitations and defects of the prior art.

[0011] One aspect of this disclosure provides an electroluminescent display device comprising pixels having driving transistors and switching transistors, the two types of transistors having different channel region sizes and reducing tilt angle deviation.

[0012] Other features and aspects are set forth in the description below, and some of these features and aspects are obvious from the description below, or may be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept may be recognized or obtained from the structures specifically pointed out or implied in the written description, as well as from the claims and the accompanying drawings.

[0013] To achieve these or other aspects of the inventive concept, as embodied and broadly described, an electroluminescent display device may include: a pixel, the pixel comprising: an electroluminescent diode, a driving transistor configured to provide current to the electroluminescent diode, and a switching transistor configured to switch a signal provided to the driving transistor, wherein the channel region size of the driving transistor is different from the channel region size of the switching transistor, and wherein the tilt angle deviation between the edges of the channel regions of the driving transistor and the switching transistor is less than or equal to 10°.

[0014] Furthermore, in a method for manufacturing an electroluminescent display device, the method may include: providing a semiconductor layer on a substrate for forming a channel region of a driving transistor and a channel region of a switching transistor; patterning a photoresist on the semiconductor layer by a photolithography process; and patterning the channel regions of the driving transistor and the switching transistor by using a dry etching process with an O2 gas flow ratio of at least 30%, such that the edges of the channel regions of the driving transistor and the channel regions of the switching transistor each have a tilt angle.

[0015] Other systems, methods, features, and advantages will become apparent to those skilled in the art upon review of the following figures and detailed description. It is intended that all such other systems, methods, features, and advantages are included in this description, or within the scope of this disclosure, and protected by the following claims. None of the foregoing portions are intended to limit the scope of the claims. Other aspects and advantages will be discussed hereinafter in conjunction with embodiments of this disclosure. It will be understood that the general description above and the specific description below are illustrative and intended to provide further explanation of this disclosure as claimed. Attached Figure Description

[0016] This document includes accompanying drawings to provide a further understanding of the disclosure, and the drawings are incorporated in and form a part of the specification. The drawings illustrate embodiments of the disclosure and, together with the textual description, serve to explain the principles of the disclosure.

[0017] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure.

[0018] Figure 2 It is shown Figure 1 The circuit diagram of the pixels of the display panel.

[0019] Figure 3 This is a schematic waveform diagram showing the scan signal used to drive the pixel and the corresponding node voltage of the pixel.

[0020] Figure 4A This is the pixel circuit diagram during the initialization period.

[0021] Figure 4B It is a pixel circuit diagram during the sampling period.

[0022] Figure 4C This is a pixel circuit diagram during the light emission cycle.

[0023] Figure 5 This is a circuit diagram showing the parasitic capacitance generated by the gate of the driving transistor and another electrode (or signal line) during the transition time between the sampling period and the emission period.

[0024] Figure 6A This is a plan view showing the driving transistor DT of a pixel in an electroluminescent display device according to an embodiment of the present disclosure.

[0025] Figure 6B Indicates along Figure 6A The cross-sectional view obtained from line A-A' in the diagram.

[0026] Figure 7A This is a plan view showing the switching transistors of a pixel in an electroluminescent display device according to an embodiment of the present disclosure.

[0027] Figure 7B It is along Figure 7A The cross-sectional view obtained by line B-B'.

[0028] In all accompanying drawings and detailed descriptions, unless otherwise stated, the same reference numerals should be understood to represent the same elements, features, and structures. The relative dimensions and descriptions of these elements may be enlarged for clarity, illustration, and simplicity. Detailed Implementation

[0029] Reference will now be made specifically to some embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, specific descriptions of well-known functions or structures relating to this document will be omitted where it is determined that such specific descriptions would obscure the essential points of the inventive concept. The described process steps or operational sequences are exemplary; however, the order of steps and / or operations is not limited to those listed herein and may be varied as is known in the art, except for steps and / or operations that must be performed in a specific order. Similar reference numerals throughout the document denote similar elements. The names of the elements used in the following description have been chosen solely for ease of writing and may differ from those used in actual products.

[0030] When describing an embodiment, if a structure is described as being "above" or "below" or "under" another structure, the description should be interpreted to include cases where the structures are in contact with each other and cases where a third structure is disposed therebetween.

[0031] Although the transistors in the embodiments of this disclosure are shown as P-type, the technical concept of this disclosure is not limited thereto and the transistors can be considered as N-type.

[0032] The inventors of this disclosure have studied a structure for an electroluminescent display device and a method for manufacturing the same, which can provide excellent image quality.

[0033] In particular, the inventors of this disclosure recognized that the tilt angle deviation of the channel regions of multiple transistors in a pixel of an electroluminescent display device affects the image quality of the electroluminescent display device. Furthermore, they recognized that this tilt angle tends to vary depending on the channel region size of the transistor. In other words, they discovered that as the channel region size decreases, the tilt angle increases. Moreover, they discovered that the greater the size difference between the channel regions, the greater the tilt angle deviation.

[0034] Furthermore, the inventors of this disclosure recognized that as the tilt angle deviation increases, the threshold voltage deviation of the transistor tends to increase. Therefore, the retrace voltage of the pixel increases, resulting in an image retention problem.

[0035] Furthermore, the inventors of this disclosure recognize that the compensation performance of conventional compensation circuits deteriorates when there is a threshold voltage deviation between the driving transistor and the switching transistor.

[0036] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure.

[0037] refer to Figure 1 The electroluminescent display device 100 according to an exemplary embodiment of the present disclosure is described. The electroluminescent display device 100 according to an embodiment of the present disclosure may include: a display panel 10 on which a plurality of pixels P are formed; a data driver 12 for driving a plurality of data lines (DL(1) to DL(m)); a gate driver 13 for driving a plurality of gate lines, such as EL(1) to EL(n), SL1(1) to SL1(n) and SL2(1) to SL2(n); and a timing controller 11 for controlling the data driver 12 and the gate driver 13.

[0038] The multiple pixels P of the display panel 10 can be configured to display images. Pixel P on the nth horizontal line can be electrically connected to the nth light-emitting line EL, the nth first scan line SL1, and the nth second scan line SL2. Pixel P in each column can be electrically connected to the corresponding data line DL. The transistor TFT constituting the pixel P can be formed of polysilicon (poly-Si).

[0039] Multiple pixels P in the pixel region can be configured to receive a high-potential voltage ELVDD, a low-potential voltage ELVSS, and an initial voltage Vini from the power supply unit. The initial voltage can be selected from a range sufficiently lower than the operating voltage of the electroluminescent diode (ELD), thereby suppressing unnecessary luminescence of the ELD during the initialization and sampling periods. That is, the initial voltage Vini can be set to be equal to or lower than the low-potential voltage ELVSS. Therefore, the initial voltage Vini can be lower than the low-potential voltage ELVSS, thereby extending the lifetime of the ELD.

[0040] The timing controller 11 can rearrange the digital video data RGB received from an external system to be compatible with the resolution of the display panel 10, and then provide the rearranged digital video data RGB to the data driver 12. Furthermore, the timing controller 11 can generate signals such as a data control signal DDC for controlling the operating timing of the data driver 12 and a gate control signal GDC for controlling the operating timing of the gate driver 13, which can be generated based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE.

[0041] The data driver 12 can convert digital video data (RGB) received from the timing controller 11 into analog data voltage based on the data control signal DCC. The gate driver 13 can generate scan and emission signals based on the gate control signal GDC. The gate driver 13 may include a scan driver and an emission driver. The scan driver can provide a first scan signal SCAN1 to a first scan line SL1 and a second scan signal SCAN2 to a second scan line SL2. The emission driver can provide an emission signal EM to an emission line EL. The gate driver 13 can be directly formed in the peripheral area of ​​the display panel 10 using in-plane gate driver (GIP) technology. However, the embodiments of this disclosure are not limited to the above-described components, but are merely examples.

[0042] Figure 2 It is shown Figure 1 The circuit diagram of the pixels of the display panel.

[0043] Reference Figure 2 The present disclosure describes pixels P of a display panel 10 of an electroluminescent display device 100 according to an exemplary embodiment. Each pixel P may include an electroluminescent diode ELD, a driving transistor DT, first to sixth transistors (T1 to T6), and a capacitor Cst. However, embodiments of the present disclosure are not limited to the above-described components, but are merely examples. The first to sixth transistors (T1 to T6) are referred to as "switching transistors ST".

[0044] An electroluminescent diode (ELD) emits light due to the drive current provided by the driving transistor DT. An ELD may include an anode, a cathode, and a functional layer formed between the anode and cathode. The functional layer may include at least one of a hole transport layer (HTL), an electron transport layer (ETL), and an emissive layer (EML).

[0045] A hole transport layer is a layer used for injecting or transporting holes. For example, hole injection layer (HIL), hole transport layer (HTL), and electron blocking layer (EBL) can be considered "hole transport layers".

[0046] An electron transport layer is a layer used to inject or transport electrons from the cathode or anode into the electron transport layer (EML). For example, electron transport layers (ETL), electron injection layers (EIL), and hole blocking layers (HBL) can be considered "electron transport layers".

[0047] The anode of the electroluminescent diode (ELD) can be connected to the fourth node N4. The cathode of the electroluminescent diode (ELD) can be connected to the input of the low potential voltage ELVSS, which can be ground.

[0048] The driving transistor DT can control the driving current supplied to the electroluminescent diode ELD based on the potential difference between its gate and source. The source of the driving transistor DT can be connected to the first node N1, the gate can be connected to the second node N2, and the drain can be connected to the third node N3.

[0049] The first transistor T1 may include a source connected to the third node N3, a drain connected to the second node N2, and a gate connected to the nth first scan line SL1(N). In response to the nth first scan signal SCAN1(N), the first transistor T1 may have a diode connection for short-circuiting the gate and source of the electrically short-circuited drive transistor DT to function as a diode.

[0050] The second transistor T2 may include a source connected to a data line DL (e.g., DL2), a drain connected to a first node N1, and a gate connected to the nth first scan line SL1(N). As a result, in response to the first scan signal SCAN1(N), the second transistor T2 can provide the data voltage Vdata from the data line (e.g., data line DL2) to the first node N1.

[0051] The third transistor T3 may include a source connected to the high potential line VDD, a drain connected to the first node N1, and a gate connected to the light-emitting line EL(N). As a result, in response to the light-emitting signal EM (e.g., the light-emitting signal EM(N)), the third transistor T3 may provide a high potential voltage ELVDD (e.g., VDD) to the first node N1.

[0052] The fourth transistor T4 may include a source connected to the third node N3, a drain connected to the fourth node N4, and a gate connected to the light-emitting line EL(N). In response to the light-emitting signal EM(N), the fourth transistor T4 may provide a current path between the third node N3 and the fourth node N4.

[0053] The fifth transistor T5 may include a drain connected to the second node N2, a source connected to the input of the initial voltage Vini, and a gate connected to the (N-1)th second scan line SL2(N-1). In response to the (N-1)th second scan signal SCAN2(N-1), the fifth transistor T5 may provide the initial voltage Vini to the second node N2.

[0054] The sixth transistor T6 may include a drain connected to the fourth node N4, a source connected to the input of the initial voltage Vini, and a gate connected to the nth second scan line SL2(N). In response to the nth second scan signal SCAN2(N), the sixth transistor T6 may provide the initial voltage Vini to the fourth node N4.

[0055] The storage capacitor Cst may include a first electrode connected to the second node N2 and a second electrode connected to the high-voltage line VDD. Embodiments of this disclosure are not limited to the examples described above.

[0056] Figure 3 It is a waveform diagram showing the scan signal used to drive the pixel and the corresponding node voltage of the pixel. Figure 4A This is the circuit diagram of pixel P during the initialization period. Figure 4B This is the circuit diagram of pixel P during the sampling period. Figure 4C It is a circuit diagram of a pixel during the light emission cycle.

[0057] Reference Figures 2 to 4C The operation of an electroluminescent display device 100 according to an exemplary embodiment of the present disclosure is described. In the electroluminescent display device 100 according to an exemplary embodiment of the present disclosure, the frame period can be divided into an initial period Ti, a sampling period Ts, and an emission period Te. However, the embodiments of the present disclosure are not limited thereto.

[0058] The initial period Ti is the period used to initialize the gate of the driving transistor. The sampling period Ts is the period used to sample the threshold voltage Vth of the driving transistor DT after initializing the anode voltage of the electroluminescent diode ELD and to store the threshold voltage Vth in the second node N2. The emission period Te is the period used to cause the electroluminescent diode ELD to emit light through a driving current determined by the programmed potential difference between the gate and source of the driving transistor DT, including the sampled threshold voltage Vth.

[0059] The initial period Ti of the nth horizontal line can overlap with the sampling period Ts of the (N-1)th horizontal line. That is, the sampling period Ts can be sufficiently guaranteed, thus allowing for more accurate compensation of the threshold voltage Vth. It should be noted that as the threshold voltage deviation (ΔVth) between the switching transistor ST and the driving transistor DT increases, the accuracy of the threshold voltage Vth compensation decreases.

[0060] During the initial period Ti, in response to the nth second scan signal SCAN2(N), the fifth transistor T5 can provide the initial voltage Vini to the second node N2. Thus, the gate of the driving transistor DT can be initialized to the initial voltage Vini. The initial voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the electroluminescent diode ELD, and the initial voltage Vini can be set to be equal to or lower than the low potential voltage ELVSS. During the initial period Ti, the data voltage Vdata of the previous frame is maintained in the first node N1.

[0061] During the sampling period Ts, in response to the nth second scan signal SCAN2(N), the sixth transistor T6 can provide the initial voltage Vini to the fourth node N4. As a result, the anode of the electroluminescent diode ELD can be initialized to the initial voltage Vini.

[0062] In response to the nth first scan signal SCAN1(N), the second transistor T2 can provide a data voltage Vdata, which is supplied from the data line DL2 to the first node N1. In response to the nth first scan signal SCAN1(N), the first transistor T1 is turned on, thereby driving transistor DT to be in diode-connected mode.

[0063] During the sampling period Ts, current flows through the source and drain of the driving transistor DT. Since the gate and drain of the driving transistor DT are in diode-connected mode, the current flowing from the source to the drain causes the voltage of the second node N2 to gradually increase. During the sampling period Ts, the voltage of the second node N2 increases from the initial voltage Vini to the value obtained by subtracting the threshold voltage Vth of the driving transistor DT from the data voltage Vdata (e.g., Vdata(n)) (Vdata(n) - Vth).

[0064] During the light emission cycle Te, in response to the light emission signal EM (e.g., light emission signal EM(N)), the third transistor T3 can provide a high potential voltage VDD to the first node N1. In response to the nth light emission signal EM(N), the fourth transistor T4 can form a current path between the third node N3 and the fourth node N4. Thus, the drive current Ield flowing through the source and drain of the driving transistor DT can be provided to the electroluminescent diode ELD.

[0065] During the light emission period Te, the relationship between the driving current Ield flowing through the electroluminescent diode ELD can be expressed by the following equation 1.

[0066] [Equation 1]

[0067] Ield = (k / 2)(Vgs + |Vth|) 2 = (k / 2)(Vg–Vs+|Vth|) 2 =(k / 2)(Vdata-|Vth|-VDD+|Vth|) 2 = (k / 2)(Vdata-VDD) 2

[0068] In Equation 1, (k / 2) represents a proportionality constant determined by electron mobility, parasitic capacitance, and the width (W) and length (L) of the channel region of the driving transistor DT. The channel region size can be determined based on the width (W) and length (L) of the channel region.

[0069] According to Equation 1, the threshold voltage Vth component of the driving transistor DT can be eliminated from the relationship of the driving current Ield. This means that for an electroluminescent display device according to an embodiment, the driving current Ield will not change. That is, the data voltage of an electroluminescent display device according to an embodiment of this disclosure can be programmed regardless of the deviation of the threshold voltage Vth during the sampling period Ts.

[0070] However, even if the potential difference between the gate and source of the driving transistor DT is programmed to the desired voltage during the sampling period Ts, the target brightness cannot be achieved if the gate voltage of the driving transistor DT changes. The gate of the driving transistor DT can form a parasitic capacitance with adjacent electrodes or signal lines, and the flyback effect caused by the parasitic capacitance results in a voltage change at the second node N2. The voltage change caused by the parasitic capacitance at the second node N2 connected to the gate of the driving transistor will now be described.

[0071] Figure 5 It is a circuit diagram showing the parasitic capacitance generated by the gate of the driving transistor and another electrode (or signal line) during the transient time between the sampling period and the emission period.

[0072] refer to Figure 5 The first parasitic capacitance C1 can be the capacitance between the second node N2 and the light-emitting line EL (N), the second parasitic capacitance C2 can be the capacitance between the second node N2 and the first scan line SL1 (N), and the third parasitic capacitance C3 can be the capacitance between the second node N2 and the data line DL (e.g., data line DL2).

[0073] refer to Figure 4B and Figure 5 During the sampling period Ts, the second node N2 can be programmed with a value (Vdata-Vth), which remains in a floating state during the emission period Te. However, the voltage of the second node N2 in the floating state is affected by parasitic capacitance. Therefore, when the voltage of an adjacent signal line changes at the beginning of the emission period Te, the voltage of the second node N2 also changes due to the flyback effect of each of the first to third parasitic capacitances C1 to C3. For example, as the threshold voltage deviation (ΔVth) between the threshold voltage of the switching transistor ST and the threshold voltage of the driving transistor DT increases, the flyback voltage increases.

[0074] For example, at the start of the emission period Te, the emission signal EM can switch from a high potential voltage to a low potential voltage, and the first scan signal SCAN1(N) can switch from a low potential voltage to a high potential voltage. That is, the voltage at the electrode that can generate parasitic capacitance with the second node N2 will change, thus the voltage at the second node N2 will change due to the retrace effect. The uniformity of the switching transistor ST (e.g., transistors T1 to T6) of pixel P will be described below based on the retrace voltage of the driving transistor DT and the uniformity deviation.

[0075] Figure 6A This is a plan view of the driving transistor DT of the pixel P of an electroluminescent display device 100 according to an embodiment of the present disclosure. Figure 6B It is along Figure 6A The cross-sectional view obtained by the line A-A'. Figure 7A This is a plan view showing the switching transistor ST of pixel P in an electroluminescent display device 100 according to an embodiment of the present disclosure. Figure 7B It is along Figure 7A The cross-sectional view obtained from line B-B' in the diagram.

[0076] refer to Figures 6A to 7B Multiple pixels P can be formed on a substrate SUB. The substrate SUB can be made of, for example, glass or a flexible material. A buffer layer BUF can be formed on the substrate SUB. The buffer layer BUF can be formed of, for example, silicon nitride (SiNx) and / or silicon oxide (SiOx), and can be formed as a single layer or a multilayer structure.

[0077] According to embodiments of this disclosure, the semiconductor layer ACT of the transistors (e.g., DT and ST) of pixel P can be formed, for example, from low-temperature polycrystalline silicon (LTPS), and the semiconductor layer can be crystallized by melting amorphous silicon (a-Si) with a laser. Compared to amorphous semiconductor layers, crystalline semiconductor layers ACT exhibit better current driving capability. Therefore, the crystalline channel region is relatively smaller compared to the amorphous channel region. Consequently, high-resolution display devices can be realized. However, performance deviations can occur depending on the degree of crystallinity of the channel region. That is, compared to amorphous semiconductor layers, crystalline semiconductor layers ACT have difficulty ensuring the uniformity of channel region characteristics.

[0078] The semiconductor layer ACT can be deposited as, for example, to The thickness of the photoresist is determined. A photoresist can be coated onto the deposited semiconductor layer ACT. The photoresist can be patterned using a photolithography process. After the photolithography process, the semiconductor layer ACT can be patterned using a dry etching process. For example, the dry etching process can be performed by selectively using gases such as O2, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), helium (He), hydrochloric acid (HCl), and chlorine (Cl2). O2 gas can be used to adjust the tilt angle of the semiconductor layer ACT. The portion of the semiconductor layer ACT with the photoresist removed can be etched away using a dry etching process to form the channel region and line region of each transistor. After the dry etching process, the photoresist can be removed using a stripping process. As an example, during the dry etching process, for example, CF4 gas and O2 gas can be used to pattern the semiconductor layer ACT of the electroluminescent display device 100 according to an exemplary embodiment of this disclosure.

[0079] The gate insulating layer GI can be disposed on the semiconductor layer ACT. The gate insulating layer GI can be made of silicon nitride (SiNx) and / or silicon oxide (SiOx), and can be formed as a single layer or a multilayer structure.

[0080] A gate (GATE) may be disposed on a gate insulating layer (GI). The gate (GATE) and the semiconductor layer (ACT) may be electrically insulated from each other through the gate insulating layer (GI). The gate (GATE) may be made of a metallic material, for example, and may be formed of a metallic material with low resistance, such as copper (Cu), aluminum (Al), molybdenum (Mo), and / or titanium (Ti). However, embodiments of this disclosure are not limited thereto.

[0081] Furthermore, the region where the semiconductor layer ACT and the gate GATE overlap in their respective transistors can be defined as a "channel region". The region in the semiconductor layer (ACT) other than the channel region can be defined as a "line region". One side of the line region relative to the channel region can be referred to as the "source", and the other side as the "drain". However, embodiments of this disclosure are not limited thereto.

[0082] The line regions of the semiconductor layer ACT can be referred to as "metallization regions," which are formed by incorporating impurities (e.g., dopants) into the semiconductor layer ACT. For example, the channel regions of the semiconductor layer ACT can be shielded from impurities by using a mask. For example, a gate overlapping the channel regions can be used as a mask to block impurities. However, embodiments of this disclosure are not limited thereto. For example, a separate mask can be used to define the regions doped with impurities. The impurity provisioning process can be referred to as a "doping process."

[0083] Through a high-concentration doping process, the line regions of the semiconductor layer ACT are made conductive. The line regions of the semiconductor layer ACT can be doped with group 3 boron (B) as acceptor and / or group 5 phosphorus (P) as donor. However, the embodiments of this disclosure are not limited to the above.

[0084] Furthermore, the channel region of the semiconductor layer ACT can be doped with a low concentration of acceptors, thus the channel region can be P-type. In this case, the transistor is a PMOS transistor. Alternatively, the channel region of the semiconductor layer ACT can be doped with a low concentration of donors, thus the channel region can be N-type. In this case, the transistor is an NMOS transistor. The signal level, source / drain identification, and connections can be adjusted to a manner understood by those skilled in the art based on the transistor type.

[0085] Because the line regions of the semiconductor layer ACT of specific transistors in pixel P have metallic properties, these line regions can be further extended to become part of signal lines and / or nodes. That is, highly doped line regions connecting the channel regions of different transistors in pixel P can be formed as interconnecting lines and / or nodes. Furthermore, a portion of the line region can be configured to be electrically connected to metallic signal lines (e.g., data lines) via contact holes passing through the insulating layer.

[0086] The width W and length L of the semiconductor layer ACT for each transistor in pixel P can be different. The shape of the channel region of each transistor is not limited to... Figure 6A The example is a square shape. For instance, the channel area can be formed in various shapes, such as "S", "L", "C" and curved shapes. Moreover, the width W of the channel area can be formed differently depending on the specific location.

[0087] The performance of a transistor can be determined by the length L and width W of the transistor channel region. The width W and length L of the channel region can be sized appropriately to provide sufficient current Ield to the electroluminescent diode ELD by driving the transistor DT.

[0088] The width W and length L of the channel region of the switching transistor ST can be made relatively shorter than the channel region of the driving transistor DT. Therefore, the channel region of the switching transistor ST can be configured to be relatively smaller than the channel region of the driving transistor DT. That is, the channel region area of ​​the driving transistor can be wider than the channel region area of ​​the switching transistor.

[0089] It should be noted that if a dry etching process is performed without considering the tilt angle characteristics of different channel regions of the transistor, the tilt angles of the semiconductor layer ACT will vary depending on the area of ​​different channel regions of the transistor. That is, to adjust the tilt angle of the electroluminescent display device 100, the following operations can be performed: operations for providing the semiconductor layer ACT on the substrate SUB; operations for patterning the photoresist on the semiconductor layer using a photolithography process; and operations for applying an O2 gas flow rate of at least 30% to the dry etching process to pattern the tilt angles of the channel regions of the driving transistor DT and the switching transistor ST having the semiconductor layer ACT, wherein the tilt angles can be formed to be equal to or less than a specific degree.

[0090] Referring to Table 1 below, the tilt angle of the semiconductor layer ACT of each transistor in pixel P can be varied according to the gas ratio applied in the dry etching process. For example, when dry etching the semiconductor layer ACT, the tilt angle (θ) of the edge of the semiconductor layer ACT can be adjusted by controlling the ratio of CF4 gas and O2 gas. In Table 1, "O2" represents the content (e.g., percentage) of O2 gas in O2 gas and CF4 gas. "(θ1)" represents the tilt angle on one side of the channel region of the driving transistor DT. "(θ2)" represents the tilt angle on the other side of the channel region of the driving transistor DT. "(θ3)" represents the tilt angle on one side of the channel region of the switching transistor ST. "(θ4)" represents the tilt angle on the other side of the channel region of the switching transistor ST.

[0091] As an example, the channel width W of the driving transistor DT can be 5 μm and the length L can be 20 μm. As an example, the channel width W of the switching transistor ST can be 3 μm and the length L can be 3 μm. That is, the channel areas of the driving transistor DT and the switching transistor ST can be different from each other.

[0092] Referring further to Table 1, as the O2 gas flow rate increases, the overall tilt angle of transistors with different channel areas decreases. In other words, the tilt angle of the semiconductor layer can be adjusted according to the O2 gas flow rate.

[0093] [Table 1]

[0094] <![CDATA[O2]]> DT(θ1) DT(θ2) ST(θ3) ST(θ4) 30％ 14° 13° 28° 26° 40％ 10° 9° 18° 18.3° 50％ 6° 6° 7° 7.5°

[0095] The tilt angle deviation (Δθ), threshold voltage deviation (ΔVth) of each transistor, and image lag due to retrace voltage will be described with reference to Table 2 below, based on the different channel area of ​​each transistor.

[0096] In Table 2, "|△θ(DT-ST)|" represents the absolute value of the tilt angle deviation between the driving transistor DT and the switching transistor ST, whose channel areas are different from each other. "|△Vth(DT-ST)|" represents the absolute value of the threshold voltage deviation between the driving transistor DT and the switching transistor ST according to |△θ(DT-ST)|. "Image persistence" represents the duration of image persistence according to |△θ(DT-ST)|.

[0097] Referring to Table 2, as the tilt angle deviation |Δθ(DT-ST)| of transistors with different channel areas decreases, the threshold voltage deviation |ΔVth(DT-ST)| and the flyback voltage also decrease. Therefore, when the electroluminescent display device 100 displays an image, the image persistence characteristics are improved. Further referring to Table 1 above, it is disclosed that as the O2 gas flow ratio increases, the tilt angle deviation |Δθ(DT-ST)| also increases, regardless of the channel area of ​​each transistor.

[0098] [Table 2]

[0099] |△θ(DT-ST)| |△Vth(DT-ST)| Image retention 1° 0.05V 0 seconds 5° 0.7V 20 seconds 10° 1.1V 50 seconds 15° 1.2V 60 seconds

[0100] That is, further referring to Table 2, for example, pixel P may include an electroluminescent diode ELD, a driving transistor DT configured to provide current to the electroluminescent diode, and a switching transistor ST configured to switch the signal provided to the driving transistor, wherein the channel area of ​​the driving transistor DT and the channel area of ​​the switching transistor ST are different from each other, and wherein the tilt angle deviation |Δθ(DT-ST)| between the channel areas of the driving transistor DT and the switching transistor ST may be less than or equal to 10°.

[0101] In one example, the tilt angle deviation |△θ(DT-ST)| of the channel regions of the driving transistor DT and the switching transistor ST can be less than or equal to 5°. In another example, the tilt angle deviation |△θ(DT-ST)| of the channel regions of the driving transistor DT and the switching transistor ST can be less than or equal to 1°.

[0102] In one example, to achieve a tilt angle deviation |Δθ(DT-ST)| between the channel regions of the driving transistor DT and the switching transistor ST of less than or equal to 10°, the O2 gas flow ratio is at least 30%. In another example, to achieve a tilt angle deviation |Δθ(DT-ST)| between the channel regions of the driving transistor DT and the switching transistor ST of less than or equal to 5°, the O2 gas flow ratio is at least 40%.

[0103] In another example, to ensure that the tilt angle deviation |Δθ(DT-ST)| of the channel regions of the driving transistor DT and the switching transistor ST is less than or equal to 1°, the O2 gas flow ratio is at least 50%. For example, the O2 gas flow ratio can be set from 50% to 60%. That is, according to the dry etching process, the pixel P of the electroluminescent display device 100 according to an embodiment of the present disclosure can include a plurality of transistors with different channel region areas and minimize the tilt angle deviation of the channel regions.

[0104] Furthermore, the above configuration offers the advantage of reducing the threshold voltage deviation (ΔVth) of the transistors in multiple pixels P within the pixel region. It also improves image persistence characteristics. Moreover, due to the reduced threshold voltage deviation, it enhances the luminous uniformity of the pixel region.

[0105] Some exemplary embodiments of this disclosure may also be described below. According to one aspect of this disclosure, an electroluminescent display device may include a pixel having an electroluminescent diode, a driving transistor configured to provide current to the electroluminescent diode, and a switching transistor configured to switch a signal provided to the driving transistor. The channel region size of the driving transistor differs from the channel region size of the switching transistor. The tilt angle deviation between the channel regions of the driving transistor and the switching transistor may be less than or equal to 10°.

[0106] During the dry etching process, the tilt angle deviation of the channel regions of the driving transistor and the switching transistor can be adjusted according to the O2 gas flow ratio. The tilt angle deviation can be less than or equal to 5°. The channel regions of the driving transistor and the switching transistor can be dry etched using an O2 gas flow ratio greater than or equal to 40%. The tilt angle deviation can be less than or equal to 1°. The channel regions of the driving transistor and the switching transistor can be dry etched using an O2 gas flow ratio greater than or equal to 50%. The tilt angle of the channel region of the driving transistor and the switching transistor can each be less than or equal to 20°. The tilt angle of the channel region of the driving transistor and the switching transistor can each be less than or equal to 10°. The tilt angle deviation of the channel regions of the driving transistor and the switching transistor can be less than or equal to 5°. The channel region size of the driving transistor can be larger than the channel region size of the switching transistor. The semiconductor layers constituting the driving transistor and the switching transistor include a low-temperature polysilicon layer.

[0107] According to another aspect of this disclosure, a method for manufacturing an electroluminescent display device includes: providing a semiconductor layer on a substrate; patterning a photoresist on the semiconductor layer using a photolithography process; and patterning the tilt angle of the channel region of a driving transistor and the tilt angle of the channel region of a switching transistor using a dry etching process with an O2 gas flow ratio of at least 30%. Both the channel regions of the driving transistor and the switching transistor include the semiconductor layer. The tilt angle may be less than or equal to a specific degree. The semiconductor layer may be a low-temperature polycrystalline silicon layer crystallized by laser.

[0108] A specific degree may be less than or equal to 20°. A specific degree may be less than or equal to 10°. The O2 gas flow ratio may be greater than or equal to 50%. The gas mixture used in the dry etching process may include O2 gas and at least one gas selected from CF4, SF6, He, HCl, and Cl2.

[0109] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its technical concept and scope. Therefore, the embodiments of this disclosure are intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0110] In addition, this disclosure also includes the following configurations.

[0111] (1). An electroluminescent display device, comprising:

[0112] Pixels, the pixels including:

[0113] Electroluminescent diode;

[0114] A driving transistor, configured to provide current to an electroluminescent diode; and

[0115] A switching transistor, configured to switch on a signal provided to a driving transistor.

[0116] The channel region size of the driving transistor is different from the channel region size of the switching transistor, and

[0117] The tilt angle deviation of the edges of the channel regions of the driving transistor and the switching transistor is less than or equal to 10°.

[0118] (2). The electroluminescent display device as described in (1), wherein the tilt angle deviation is adjusted according to the O2 gas flow ratio during a dry etching process for patterning the channel regions of the driving transistor and the switching transistor.

[0119] (3) The electroluminescent display device as described in (1), wherein the tilt angle deviation is less than or equal to 5°.

[0120] (4) The electroluminescent display device as described in (3), wherein the channel regions of the driving transistor and the switching transistor are dry-etched using an O2 gas flow ratio of equal to or greater than 40%.

[0121] (5) The electroluminescent display device as described in (1), wherein the tilt angle deviation is less than or equal to 1°.

[0122] (6) The electroluminescent display device as described in (5), wherein the channel regions of the driving transistor and the switching transistor are dry-etched using an O2 gas flow ratio of greater than or equal to 50%.

[0123] (7) The electroluminescent display device as described in (1), wherein the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the switching transistor are both less than or equal to 20°.

[0124] (8) The electroluminescent display device as described in (7), wherein the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the switching transistor are both less than or equal to 10°.

[0125] (9) The electroluminescent display device as described in (8), wherein the tilt angle deviation is less than or equal to 5°.

[0126] (10) The electroluminescent display device as described in (1), wherein the channel region size of the driving transistor is larger than the channel region size of the switching transistor.

[0127] (11). The electroluminescent display device as described in (1), wherein the channel regions of the driving transistor and the switching transistor comprise a low-temperature polycrystalline silicon layer.

[0128] (12). A method for manufacturing an electroluminescent display device, the method comprising:

[0129] A semiconductor layer is provided on the substrate for forming the channel region of the driving transistor and the channel region of the switching transistor;

[0130] The photoresist on the semiconductor layer is patterned using a photolithography process; and

[0131] The channel regions of the driving transistor and the switching transistor are patterned using a dry etching process with an O2 gas flow ratio of at least 30%, such that the edges of the channel regions of the driving transistor and the switching transistor each have a tilt angle.

[0132] (13). The manufacturing method as described in (12), wherein the semiconductor layer is a laser-crystallized low-temperature polycrystalline silicon layer.

[0133] (14). The manufacturing method as described in (12), wherein the tilt angle is less than or equal to 20°.

[0134] (15). The manufacturing method as described in (14), wherein:

[0135] The tilt angle is less than or equal to 10°; and

[0136] The O2 gas flow ratio is greater than or equal to 50%.

[0137] (16) The manufacturing method as described in (12), wherein the gas mixture used for the dry etching process includes O2 gas and at least one gas selected from CF4, SF6, He, HCl and Cl2.

[0138] (17) The manufacturing method as described in (12), wherein the tilt angle deviation of the edges of the channel regions of the driving transistor and the switching transistor is less than or equal to 5°.

[0139] (18) The manufacturing method as described in (17), wherein the channel regions of the driving transistor and the switching transistor are dry-etched using an O2 gas flow ratio equal to or greater than 40%.

Claims

1. An electroluminescent display device, comprising: A substrate, the substrate including a display area and a non-display area disposed around the display area; A gate driver is disposed on the non-display area; as well as Multiple pixels are disposed on the display area, and the pixels are configured to receive drive signals. Each of the plurality of pixels includes: Electroluminescent diode; A driving transistor, connected to the electroluminescent diode and configured to provide current to the electroluminescent diode; and At least one switching transistor is disposed in each of the plurality of pixels. The channel regions of the driving transistor and the at least one switching transistor are formed by patterning a semiconductor layer, wherein the size of the channel region of the driving transistor is different from the size of the channel region of the at least one switching transistor. The deviation between the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the at least one switching transistor is less than or equal to 10°.

2. The electroluminescent display device as described in claim 1, wherein, The plurality of pixels receive scanning signals and light emission signals.

3. The electroluminescent display device as described in claim 2, wherein, The at least one switching transistor is configured to receive a scan signal or a light emission signal.

4. The electroluminescent display device as described in claim 3, wherein, The deviation between the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the at least one switching transistor receiving the scan signal is less than or equal to 10°.

5. The electroluminescent display device as described in claim 3, wherein, The deviation between the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the at least one switching transistor receiving the light emission signal is less than or equal to 10°.

6. The electroluminescent display device as described in claim 1, wherein, During a dry etching process for patterning the channel regions of the driving transistor and the at least one switching transistor, the deviation between the tilt angle of the driving transistor and the tilt angle of the at least one switching transistor is adjusted according to the O2 gas flow ratio.

7. The electroluminescent display device as described in claim 1, wherein, The deviation between the tilt angle of the driving transistor and the tilt angle of the at least one switching transistor is less than or equal to 5°.

8. The electroluminescent display device as described in claim 7, wherein, The channel regions of the driving transistor and the at least one switching transistor are dry-etched using an O2 gas flow rate of 40% or greater.

9. The electroluminescent display device as described in claim 1, wherein, The deviation between the tilt angle of the driving transistor and the tilt angle of the at least one switching transistor is less than or equal to 1°.

10. The electroluminescent display device as claimed in claim 9, wherein, The channel regions of the driving transistor and the at least one switching transistor are dry-etched using an O2 gas flow rate of 50% or higher.

11. The electroluminescent display device of claim 1, wherein the tilt angle of the edge of the channel region of the driving transistor and the tilt angle of the edge of the channel region of the at least one switching transistor are both less than or equal to 20°.

12. The electroluminescent display device as claimed in claim 1, wherein, The channel region size of the driving transistor is larger than the channel region size of the at least one switching transistor.

13. The electroluminescent display device as claimed in claim 1, wherein, The channel regions of the driving transistor and the at least one switching transistor include a low-temperature polycrystalline silicon layer.

14. The electroluminescent display device as claimed in claim 1, wherein, The gate driver is configured as an in-plane gate driver (GIP).

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