A floating gate power MOSFET and its manufacturing method

Abstract

The present invention provides a suspended gate power MOSFET and a manufacturing method thereof. The structure comprises a multi-unit cell structure formed by periodically arranging unit cells. The unit cells include: a first conductivity type epitaxial layer, a drain, a second conductivity type well region, a first conductivity type source region, a second conductivity type heavily doped region, a source electrode, an insulating dielectric layer located above the second conductivity type well region and covering a portion of the first conductivity type source region, and a suspended gate electrode. The gate electrode is disposed on the insulating dielectric layer, and a passivation protective layer is located above the gate electrode. The gate electrode has at least one window aperture, and neither the gate electrode nor the insulating dielectric layer remains in the window aperture. Compared to conventional power MOSFET structures, the present invention utilizes a sacrificial layer in place of the conventional gate oxide. The sacrificial layer is removed by opening a window aperture in the gate, leaving the gate suspended and employing a non-solid gate dielectric layer.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device and a preparation method thereof in the technical field of semiconductor devices, in particular to a suspended gate structure power MOSFET and a preparation method thereof. Background Art

[0002] Power MOSFETs in aerospace applications can experience significant performance degradation due to total dose effect (TID). Specifically, high-energy particles passing through the gate dielectric generate corresponding electron-hole pairs. Electrons quickly escape, while holes, influenced by the gate electric field, migrate toward the gate oxide interface, where they are trapped by gate oxide defects near the interface, affecting the device's threshold voltage. TID is currently one of the primary causes of MOSFET radiation degradation failure, and aerospace and research institutions worldwide have conducted extensive research on this issue.

[0003] By removing the gate dielectric, MOSFETs can be enhanced for radiation hardening, a feat previously reported in three-dimensional fin field-effect transistors (FinFETs). However, research on three-dimensional power MOSFETs remains limited. Improving power devices towards three-dimensional structures will become a key direction and breakthrough for future power electronics development.

[0004] On the other hand, SiC, a representative of third-generation semiconductors and known for its high breakdown field strength, faces a major bottleneck in the fabrication of power MOSFETs: low channel mobility. For example, while the bulk electron mobility of 4H-SiC material is roughly on par with that of Si devices, the interface states generated during gate oxidation are much higher than those of silicon devices. Even with post-gate oxide annealing using oxynitride, the channel mobility is often less than 1 / 10 of the bulk mobility, severely limiting the performance of SiC MOSFETs.

[0005] Unlike conventional surface-processing, microelectromechanical systems (MEMS) technology, as a bulk process, can achieve various three-dimensional structures through the construction and removal of sacrificial layers. The suspended gate FET (SGFET) is a representative example of MEMS technology. By floating the gate and replacing the gate oxide in the original MOSFET with a non-solid gate dielectric, the SGFET avoids reliability issues caused by gate oxide defects and allows the channel region to achieve higher mobility through processing.

[0006] The earliest known floating-gate discrete device can be traced back to 1966, when the resonant-gate transistor (RGT) was developed primarily for low- and medium-frequency filters. Subsequently, floating-gate devices were widely researched in MEMS applications such as pressure, gas, humidity, and pH sensors. However, because power semiconductors are large, multi-cell discrete devices with large dies, conventional floating-gate processing methods are difficult to transfer. Consequently, no reports on floating-gate power devices have been reported. Summary of the Invention

[0007] In view of the above-mentioned deficiencies in the prior art, the present invention aims to provide a floating gate power MOSFET structure to realize the design of a floating gate power device. Another object of the present invention is to provide a method for manufacturing the floating gate power MOSFET.

[0008] The present invention adopts the following technical solutions:

[0009] A floating gate power MOSFET, wherein the MOSFET is a multi-unit cell structure formed by periodically arranging unit cells, and the unit cells include:

[0010] a first conductivity type epitaxial layer;

[0011] a drain located at the bottom of the first conductivity type epitaxial layer;

[0012] a second conductivity type well region adjacent to the first conductivity type epitaxial layer and distributed on both sides of the first conductivity type epitaxial layer, wherein a JFET region is located between the second conductivity type well regions on both sides;

[0013] a first conductivity type source region located in the second conductivity type well region and close to the JFET region;

[0014] A second conductivity type heavily doped region located in the second conductivity type well region and away from the JFET region;

[0015] a source electrode located on the first conductivity type source region and the second conductivity type heavily doped region;

[0016] an insulating dielectric layer located above the second conductive type well region and covering a portion of the first conductive type source region;

[0017] a suspended gate electrode located above the JFET region and a portion of the first conductivity type source region, wherein the gate electrode is disposed on the insulating dielectric layer;

[0018] a passivation protection layer located on the gate electrode;

[0019] At least one window is formed on the gate electrode, and no gate electrode or insulating dielectric layer remains in the window.

[0020] Preferably, the primitive cells are in the shape of bars.

[0021] Preferably, the doping concentration of the second conductive type heavily doped region is higher than that of the first conductive type epitaxial layer.

[0022] Preferably, the insulating dielectric layer does not completely cover the boundary of the second conductive type well region close to the JFET region.

[0023] Preferably, the gate electrode is metal or doped polysilicon.

[0024] Preferably, the portion between the gate electrode and the first conductive type epitaxial layer and the second conductive type well region is a vacuum or non-solid material.

[0025] Preferably, the ratio of the window hole in contact with the insulating medium to the contact area between the polysilicon gate and the insulating medium is 1:10 to 10:1.

[0026] Preferably, the windows are arranged periodically or non-periodically in the direction along which the strip-shaped unit cells extend, the windows are of uniform or non-uniform sizes, and the windows do not exceed the area directly above the middle of the JFET region.

[0027] The manufacturing method of the above-mentioned floating gate structure power MOSFET includes the following steps: (1) forming a first conductive type epitaxial layer on a first conductive type substrate; (2) preparing a mask medium, preparing an injection mask medium through photolithography and etching processes, and forming a second conductive type well region through ion implantation; (3) removing the mask medium in step (2), preparing an injection mask medium through photolithography and etching processes, and forming a first conductive type source region through ion implantation; (4) removing the mask medium in step (3), re-preparing a mask medium, preparing an injection mask medium through photolithography and etching processes, and forming a second conductive type heavily doped region through ion implantation; (5) Remove the mask dielectric in step (4), oxidize or deposit the device surface to form an insulating dielectric layer; (6) remove the insulating dielectric layer in the area above the JFET in (4) by photolithography and etching; (7) deposit a sacrificial layer, and only retain the sacrificial layer in the area above the JFET and the sacrificial layer on part of the insulating dielectric layer by photolithography and etching, and remove the rest; (8) deposit the gate electrode material, and retain the gate electrode layer in the area above the sacrificial layer and part of the insulating dielectric layer by photolithography and etching, except that the gate electrode material in the gate electrode window is completely removed; (9) remove the sacrificial layer by wet etching; (10) deposit a passivation protective layer and form an electrode.

[0028] Preferably, the dihedral angle formed by the boundary of the sacrificial layer retained in the above manufacturing method (7) and the bottom insulating dielectric layer is not less than 30°.

[0029] The present invention improves the total dose radiation resistance of the power MOSFET by removing the solid-state gate isolation dielectric of the traditional power MOSFET, and provides the feasibility of optimizing the gate dielectric of a material with high gate oxide interface state density such as SiC. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a three-dimensional view of a floating gate power MOSFET cell after the sacrificial layer is removed, according to Example 1 of the present invention.

[0031] Figure 2 This is a three-dimensional schematic diagram of the periodic arrangement of floating gate power MOSFET cells after the sacrificial layer is removed, according to Example 1 of the present invention.

[0032] Figure 3 This is a schematic diagram of the preparation process of Example 1 of a floating gate power MOSFET device described in the present invention.

[0033] Figure 4 This is a partial schematic diagram of the gate electrode photoresist mask described in Example 1.

[0034] Explanation of reference numerals: 1, epitaxial layer; 2, P well; 3, N + Source area; 4. P + Doped region; 5. Insulating dielectric layer; 6. Sacrificial layer; 7. Gate electrode; 8. Drain. DETAILED DESCRIPTION

[0035] The present invention will be described in further detail below in conjunction with the accompanying drawings and a preferred embodiment. However, the present invention can be implemented in many different forms and should not be limited to the embodiments listed in the present invention.

[0036] It should be further explained that all directional indications in the embodiments (such as up, down, left, right, front, back, back...) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0037] It should be noted that the manufacturing process given in the embodiment can be modified or adjusted in sequence according to actual conditions. At the same time, for the sake of convenience, the embodiment is described only with N-channel MOSFET; the same applies to P-channel MOSFET.

[0038] The width described in the embodiment refers to the length along the X-axis direction, and the height or depth described refers to the length along the Y-axis direction.

[0039] The width of the JFET region described in the embodiment refers to the width between adjacent first conductivity type well regions.

[0040] Example 1

[0041] In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. Figure 2 As shown, the floating gate power MOSFET described in the present invention is a multi-unit cell structure formed by periodically arranging strip-shaped units, such as Figure 1 As shown, the cell includes an epitaxial layer 1 and a drain 8 located on the back side of the epitaxial layer 1, wherein the epitaxial layer 1 is an N-type lightly doped drift layer, and the thickness and doping concentration of the N-type lightly doped drift layer can be selected according to the blocking voltage of the device.

[0042] The P-well 2 is adjacent to the epitaxial layer 1 and is distributed on both sides of the epitaxial layer 1 . The width between the P-wells 2 is the width of the JFET region.

[0043] The second conductive type region is located in the JFET region. The doping concentration of the second conductive type region is higher than that of the epitaxial layer 1 , and the bottom thereof is higher than the bottom of the JFET region.

[0044] N + The source region 3 is located in the P well 2, close to the JFET region; + The doped region 4 is located in the P-well 2 and is far away from the JFET region.

[0045] SiO2 insulating dielectric layer 5 is located on the N + The source region 3 covers part N + The source region 3 is in contact with the doped polysilicon gate electrode 7, wherein the silicon electrode can also be metal.

[0046] The doped polysilicon gate electrode 7 is suspended on the JFET region and has no direct contact with the epitaxial layer 1. The space between the doped polysilicon gate electrode 7 and the epitaxial layer 1 on the JFET region can be vacuum without dielectric filling or filled with non-solid material.

[0047] The sidewalls of the doped polysilicon gate electrode 7 form a 70° angle with the epitaxial layer 1. Rectangular windows are formed on the sidewalls of the doped polysilicon gate electrode 7 and in the area where the doped polysilicon gate electrode 7 contacts the SiO2 insulating dielectric layer 5 (as viewed from the top). The ratio of the windows in contact with the insulating dielectric layer to the area where the gate electrode contacts the insulating dielectric layer is 1:10 to 10:1. The windows are arranged periodically or aperiodically along the direction in which the strip-shaped unit cells extend. The windows may be of uniform or non-uniform size and do not extend directly above the center of the JFET region.

[0048] The following will be in N + Source region 3 and P +A source electrode is fabricated on the doped region 4 .

[0049] like Figure 3 a- Figure 3 As shown in g, the preparation method of Example 1 of the present invention is:

[0050] (1) If Figure 3 As shown in a, P well 2, N well 3 and N well 4 are respectively formed in the epitaxial layer 1 through multiple processes such as mask medium preparation, photolithography, etching, implantation and mask medium removal. + Source region 3 and P + doped region 4;

[0051] (2) If Figure 3 As shown in b, a 500Å SiO2 insulating dielectric layer 5 is deposited on the device surface by CVD;

[0052] (3) If Figure 3 As shown in c, all and part of the N above the JFET area are removed by photolithography, etching and other processes. + The SiO2 insulating dielectric layer 5 above the source region 3 and the P-well 2 is removed;

[0053] (4) If Figure 3 As shown in FIG. 5 , 800Å Si3N4 is deposited as a sacrificial layer 6 by CVD, and only the Si3N4 sacrificial layer 6 above the JFET region and on a portion of the SiO2 insulating dielectric layer 5 is retained by processes such as photolithography and etching.

[0054] (5) If Figure 3 As shown in FIG. 5 , a doped polysilicon layer of 8000Å is deposited by CVD as a gate electrode 7;

[0055] (6) If Figure 3 As shown in f, using Figure 4 The photoresist used for the positive photoresist material is subjected to photolithography, etching and other processes to remove a portion of the gate electrode 7 on the insulating dielectric layer 5, and at the same time, a window is etched on the gate electrode 7;

[0056] (7) If Figure 3 As shown in step g, the Si3N4 sacrificial layer 6 under the gate electrode 7 is removed by wet etching. After the sacrificial layer is etched, the dihedral angle formed between the boundary of the sacrificial layer and the bottom insulating dielectric layer is not less than 30°.

[0057] (8) Subsequent passivation protection medium and electrode production.

[0058] By removing the traditional gate oxide layer, this invention avoids gate reliability issues caused by gate oxide defects and provides excellent gate radiation hardening. Furthermore, for materials with low gate oxide interface mobility, such as SiC, higher mobility can be achieved through channel region processing. This novel structure holds great promise for specialized applications in aerospace and other fields.

Claims

1. A floating gate structure power MOSFET, characterized in that: The MOSFET is a multi-unit cell structure formed by periodically arranging units, and the units include: a first conductivity type epitaxial layer; a drain located at the bottom of the first conductivity type epitaxial layer; a second conductivity type well region adjacent to the first conductivity type epitaxial layer and distributed on both sides of the first conductivity type epitaxial layer, wherein a JFET region is located between the second conductivity type well regions on both sides; a first conductivity type source region located in the second conductivity type well region and close to the JFET region; A second conductivity type heavily doped region located in the second conductivity type well region and away from the JFET region; a source electrode located on the first conductivity type source region and the second conductivity type heavily doped region; an insulating dielectric layer located above the second conductive type well region and covering a portion of the first conductive type source region, wherein the insulating dielectric layer does not completely cover a boundary of the second conductive type well region near the JFET region; a suspended gate electrode located above the JFET region and a portion of the first conductive type source region, the gate electrode being disposed on the insulating dielectric layer, and a portion between the gate electrode and the first conductive type epitaxial layer and the second conductive type well region being a vacuum or non-solid material; a passivation protection layer located on the gate electrode; At least one window is formed on the gate electrode, no gate electrode and no insulating dielectric layer remain in the window, and the window does not exceed the center of the JFET region.

2. The floating gate structure power MOSFET according to claim 1, wherein: The primitive cell is in the shape of a bar.

3. The floating gate structure power MOSFET according to claim 1, wherein: The second conductive type heavily doped region has a doping concentration higher than that of the first conductive type epitaxial layer.

4. The floating gate structure power MOSFET according to claim 1, wherein: The gate electrode is metal or doped polysilicon.

5. The floating gate structure power MOSFET according to claim 1, wherein: The ratio of the window hole in contact with the insulating dielectric layer to the contact area between the gate electrode and the insulating dielectric layer is 1:10 to 10:

1.

6. The floating gate structure power MOSFET according to claim 1, wherein: The windows are arranged periodically or non-periodically in the direction of extension of the unit cell, the sizes of the windows are consistent or inconsistent, and the windows do not exceed the center of the JFET region.

7. A method for manufacturing a floating gate structure power MOSFET according to claim 1, characterized in that: The following steps are involved: (1) forming a first conductive type epitaxial layer on a first conductive type substrate; (2) preparing a mask medium, preparing an implantation mask medium through photolithography and etching processes, and forming a second conductive type well region through ion implantation; (3) removing the mask medium in step (2), preparing an implantation mask medium through photolithography and etching processes, and forming a first conductive type source region through ion implantation; (4) removing the mask medium in step (3), re-preparing the mask medium, preparing the implantation mask medium through photolithography and etching processes, and forming the second conductive type heavily doped region through ion implantation; (5) removing the mask dielectric in step (4), performing an oxidation or deposition process on the device surface to form an insulating dielectric layer; (6) removing the region of the insulating dielectric layer above the JFET in (4) by photolithography and etching processes; (7) Depositing a sacrificial layer, and retaining only the sacrificial layer in the area above the JFET and part of the sacrificial layer on the insulating dielectric layer through photolithography and etching processes, and removing the rest; (8) Depositing gate electrode material, and through photolithography and etching processes, completely removing the gate electrode material in the gate electrode window, retaining the gate electrode layer above the sacrificial layer and part of the insulating dielectric layer; (9) Removing the sacrificial layer by wet etching process; (10) Deposit a passivation protective layer and fabricate electrodes.

8. The method for manufacturing a floating gate structure power MOSFET according to claim 7, wherein: The dihedral angle formed by the boundary of the sacrificial layer retained in step (7) and the bottom insulating dielectric layer is not less than 30°.

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