An Inverted Light-Emitting Diode Chip and Preparation Method

Abstract

The present invention discloses an inverted light-emitting diode chip and a preparation method thereof. The chip includes: a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a current transmission metal layer, a Bragg reflection layer, a reflection metal layer, an insulating layer, and a bonding metal layer; the reflection metal layer includes a first reflection metal layer and a second reflection metal layer, the insulating layer includes a first insulating layer and a second insulating layer, the first reflection metal layer and the second reflection metal layer are staggered from each other in the stacking height of the chip, one of the first insulating layer and the second insulating layer is disposed between the first reflection metal layer and the second reflection metal layer, and the other of the first insulating layer and the second insulating layer is disposed between the first reflection metal layer or the second reflection metal layer and the bonding metal layer. The aim is to solve the problems that the N-type reflection metal layer and the P-type reflection metal layer of the existing inverted chip are in the same plane, it is easy to short-circuit between the N-type reflection metal layer and the P-type reflection metal layer, and the chip fails rapidly after long-term aging.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly relates to a flip-chip light-emitting diode chip and a preparation method thereof. Background Art

[0002] Light-emitting diodes are widely used in general lighting, special lighting, landscape lighting, plant lighting, outdoor display, indoor display, liquid crystal display, vehicle-mounted lighting, vehicle-mounted display and other fields due to their advantages of energy saving, high brightness, high durability, long life, light weight, etc. At present, flip-chip LEDs can be stably used at high power, have a high external quantum efficiency, and the application is gradually mature. The reflector of the flip-chip has also changed from the original Bragg reflector layer to a double-layer reflection structure of a Bragg reflector layer plus metal, thereby improving the brightness of the chip.

[0003] However, the N-type reflective metal layer and the P-type reflective metal layer of the existing flip-chip are in the same plane. If the brightness of the chip is to be improved, it is necessary to increase the area of the reflective metal layer or shorten the distance between the N-type reflective metal layer and the P-type reflective metal layer. In this way, the risk of short circuit between the N-type reflective metal layer and the P-type reflective metal layer and the failure of the chip after long-term aging is increased, and it is difficult to achieve both high chip brightness and high reliability. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a flip-chip light-emitting diode chip and a preparation method thereof, aiming to solve the problems that the N-type reflective metal layer and the P-type reflective metal layer of the existing flip-chip are in the same plane, and it is easy to short-circuit between the N-type reflective metal layer and the P-type reflective metal layer and the chip fails quickly after long-term aging.

[0005] The first aspect of the present invention is to provide a flip-chip light-emitting diode chip, and the chip includes:

[0006] A substrate and an epitaxial layer provided on the substrate, the epitaxial layer includes a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence, wherein, a MESA step is provided on the epitaxial layer to expose the N-type semiconductor layer, and an isolation groove is provided on the MESA step to expose the substrate;

[0007] The chip further includes a current blocking layer, a current spreading layer, a current transmission metal layer, a Bragg reflector layer, a reflective metal layer, an insulating layer and a bonding metal layer;

[0008] Among them, the reflective metal layer includes a first reflective metal layer and a second reflective metal layer, the insulating layer includes a first insulating layer and a second insulating layer, the first reflective metal layer and the second reflective metal layer are staggered in the stacking height of the chip, one of the first insulating layer and the second insulating layer is disposed between the first reflective metal layer and the second reflective metal layer, and correspondingly, the other of the first insulating layer and the second insulating layer is disposed between the first reflective metal layer or the second reflective metal layer and the bonding metal layer.

[0009] According to one aspect of the above technical solution, the current transmission metal layer includes an N-type current transmission metal layer and a P-type current transmission metal layer;

[0010] Among them, the first reflective metal layer is an N-type reflective metal layer, the second reflective metal layer is a P-type reflective metal layer, the first reflective metal layer is in contact with the N-type current transmission metal layer, and the second reflective metal layer is in contact with the P-type current transmission metal layer;

[0011] Or, the first reflective metal layer is a P-type reflective metal layer, the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer is in contact with the P-type current transmission metal layer, and the second reflective metal layer is in contact with the N-type current transmission metal layer.

[0012] According to one aspect of the above technical solution, when the first reflective metal layer is an N-type reflective metal layer and the second reflective metal layer is a P-type reflective metal layer, the first reflective metal layer is in contact with the N-type current transmission metal layer through a preset N-type reflective through hole on the Bragg reflection layer to form an electrical connection, and the second reflective metal layer is in contact with the P-type current transmission metal layer through the first insulating layer and a preset P-type reflective through hole on the Bragg reflection layer to form an electrical connection.

[0013] According to one aspect of the above technical solution, the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer;

[0014] Among them, the N-type bonding metal layer is in contact with the first reflective metal layer through an insulating layer through hole preset on the second insulating layer and the first insulating layer to form an electrical connection, and the P-type bonding metal layer separately passes through an insulating layer through hole preset on the second insulating layer to be in contact with the second reflective metal layer to form an electrical connection.

[0015] According to one aspect of the above technical solution, when the first reflective metal layer is a P-type reflective metal layer and the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer contacts and forms an electrical connection with the P-type current transmission metal layer through a P-type reflective via hole preset on the first insulating layer and the Bragg reflective layer. The second reflective metal layer contacts and forms an electrical connection with the N-type current transmission metal layer through an N-type reflective via hole preset on the Bragg reflective layer.

[0016] According to one aspect of the above technical solution, the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer;

[0017] Among them, the N-type bonding metal layer individually passes through an insulating layer via hole preset on the second insulating layer to contact the first reflective metal layer and form an electrical connection. The P-type bonding metal layer contacts the second reflective metal layer through the second insulating layer and an insulating layer via hole preset on the first insulating layer to form an electrical connection.

[0018] According to one aspect of the above technical solution, the P-type current transmission metal layer is densely arranged around the periphery of the N-type current transmission metal layer to reduce the lateral current transmission distance between the P-type current transmission metal layer and the N-type current transmission metal layer.

[0019] According to one aspect of the above technical solution, the depth of the MESA step is 15%-30% of the thickness of the epitaxial layer.

[0020] According to one aspect of the above technical solution, the angle of the isolation groove is 30°-80°.

[0021] The second aspect of the present invention also provides a method for manufacturing a flip-chip light-emitting diode chip for manufacturing the flip-chip light-emitting diode chip in the above technical solution. The manufacturing method includes:

[0022] Provide a substrate;

[0023] Fabricate an epitaxial layer on the substrate. The epitaxial layer includes a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence;

[0024] Fabricate a MESA step on the epitaxial layer to expose the N-type semiconductor layer;

[0025] Fabricate a current blocking layer on the MESA step and the P-type semiconductor layer;

[0026] Fabricate a current spreading layer on the P-type semiconductor layer and the current blocking layer;

[0027] Etch the MESA step to remove the N-type semiconductor layer and the buffer layer at the MESA step to fabricate isolation grooves;

[0028] Fabricate an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the extended layer respectively;

[0029] Fabricate a Bragg reflection layer on the surfaces of the MESA step, P-type semiconductor layer, current spreading layer, and current transmission metal layer;

[0030] Fabricate a first reflective metal layer on the Bragg reflection layer, fabricate a first insulating layer on the first reflective metal layer, fabricate a second reflective metal layer on the first insulating layer, fabricate a second insulating layer on the second reflective metal layer, and fabricate a bonding metal layer on the second insulating layer;

[0031] Alternatively, fabricate a second reflective metal layer on the Bragg reflection layer, fabricate a second insulating layer on the second reflective metal layer, fabricate a first reflective metal layer on the second insulating layer, fabricate a first reflective layer on the first reflective metal layer, and fabricate a bonding metal layer on the first reflective layer.

[0032] Compared with the prior art, the flip-chip light-emitting diode chip and the preparation method thereof shown in the present invention have the beneficial effects that:

[0033] By staggering the first reflective metal layer and the second reflective metal layer in the stacking height of the chip, that is, arranging them in layers in space, and adding an insulating layer between the first reflective metal layer and the second reflective metal layer, the problems in the prior art that when the N-type reflective metal layer and the P-type reflective metal layer are in the same plane, due to the too short distance between the N-type reflective metal layer and the P-type reflective metal layer, short circuit is likely to occur and the chip fails rapidly after long-term aging can be completely solved.

[0034] The additional aspects and advantages of the present invention will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein:

[0036] Figure 1 is a schematic structural diagram of a flip-chip light-emitting diode chip in the first embodiment of the present invention;

[0037] Figure 2 is a schematic top view of the structure of the flip-chip light-emitting diode chip in the first embodiment of the present invention;

[0038] Figure 3Schematic structural diagram of an inverted light-emitting diode chip in the second embodiment of the present invention;

[0039] Figure 4 Top view schematic structural diagram of an inverted light-emitting diode chip in the second embodiment of the present invention;

[0040] Figure 5 Top view schematic structural diagram of an inverted light-emitting diode chip in the third embodiment of the present invention;

[0041] Figure 6 Schematic flow chart of a method for manufacturing an inverted light-emitting diode chip in the fourth embodiment of the present invention;

[0042] Figure 7 Schematic flow chart of another method for manufacturing an inverted light-emitting diode chip in the fourth embodiment of the present invention;

[0043] Explanation of reference numerals:

[0044] 11 - Substrate, 12 - Epitaxial layer, 121 - Buffer layer, 122 - N-type semiconductor layer, 123 - Active layer, 124 - P-type semiconductor layer, 13 - MESA step, 14 - Current blocking layer, 15 - Current spreading layer, 16 - Isolation groove, 171 - P-type current transmission metal layer, 172 - N-type current transmission metal layer, 18 - Bragg reflector, 181 - Preset N-type reflection through hole on the Bragg reflector, 19 - First reflection metal layer, 20 - First insulating layer, 201 - Preset P-type reflection through hole on the first insulating layer and the Bragg reflector, 21 - Second reflection metal layer, 22 - Second insulating layer, 221 - Insulating layer through hole preset on the second insulating layer, 222 - Preset P-type reflection through hole on the second insulating layer and the first insulating layer, 231 - P-type bonding metal layer, 232 - N-type bonding metal layer. Detailed description of the specific embodiment

[0045] In order to make the objectives, features, and advantages of the present invention more obvious and understandable, the following provides a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0046] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions used in this article are only for the purpose of illustration, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0047] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "joined", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The term "and / or" used in this article includes any and all combinations of one or more of the related listed items.

[0048] Embodiment 1

[0049] Please refer to Figure 1 and Figure 2 , the first embodiment of the present invention provides a flip-chip light-emitting diode chip, which includes: a substrate 11 and an epitaxial layer 12 provided on the substrate 11; the chip further includes a current blocking layer 14, a current spreading layer 15, a current transmission metal layer, a Bragg reflection layer 18, a reflective metal layer, an insulating layer and a bonding metal layer.

[0050] It is easy for those skilled in the art to understand that the epitaxial layer 12 includes a buffer layer 121, an N-type semiconductor layer 122, an active layer 123 and a P-type semiconductor layer 124 stacked in sequence; among them, a MESA step 13 is provided on the epitaxial layer 12 to expose the N-type semiconductor layer 122, and an isolation groove 16 is provided on the MESA step 13 to expose the substrate 11.

[0051] Among them, the current transmission metal layer includes an N-type current transmission metal layer 172 and a P-type current transmission metal layer 171, and the bonding metal layer includes an N-type bonding metal layer 232 and a P-type bonding metal layer 231.

[0052] Furthermore, the reflective metal layer includes a first reflective metal layer 19 and a second reflective metal layer 21, and the insulating layer includes a first insulating layer 20 and a second insulating layer 22. The first reflective metal layer 19 and the second reflective metal layer 21 are staggered from each other in the stacking height of the chip. The first insulating layer 20 is disposed between the first reflective metal layer 19 and the second reflective metal layer 21. Correspondingly, the second insulating layer 22 is disposed between the second reflective metal layer 21 and the bonding metal layer.

[0053] In this embodiment, the first reflective metal layer 19 is an N-type reflective metal layer, and the second reflective metal layer 21 is a P-type reflective metal layer. The first reflective metal layer 19 is lower than the second reflective metal layer 21 in the stacking height of the chip. The first reflective metal layer 19 is in contact with the N-type current transmission metal layer 172, and the second reflective metal layer 21 is in contact with the P-type current transmission metal layer 171.

[0054] Specifically, in order to make the first reflective metal layer 19 in contact with the N-type current transmission metal layer 172 to form an electrical connection, the first reflective metal layer 19 is in contact with the N-type current transmission metal layer 172 through an N-type reflective through hole 181 preset on the Bragg reflection layer 18 to form an electrical connection. The second reflective metal layer 21, which is higher than the first reflective metal layer 19 in the stacking height of the chip, needs to be in contact with the P-type current transmission metal layer 171 through a P-type reflective through hole 201 preset on the first insulating layer 20 and the Bragg reflection layer 18 to form an electrical connection; that is, the second reflective metal layer 21 needs to pass through not only the Bragg reflection layer 18 but also the first insulating layer 20 disposed above the first reflective metal layer 19 to be in contact with the P-type current transmission metal layer 171.

[0055] Furthermore, the N-type bonding metal layer 232 is in contact with the first reflective metal layer 19 through an insulating layer through hole 222 (a through hole formed by the two insulating layers being connected to each other) preset on the second insulating layer 22 and the first insulating layer 20 to form an electrical connection; that is, the N-type bonding metal layer 232 needs to pass through not only the second insulating layer 22 with a higher setting height but also the first insulating layer 20 disposed below the second insulating layer 22 to be in contact with the first reflective metal layer 19 to form an electrical connection. The P-type bonding metal layer 231 passes through an insulating layer through hole 221 (a through hole independently set on the second insulating layer 22) preset on the second insulating layer 22 alone to be in contact with the second reflective metal layer 21 to form an electrical connection; that is, the P-type bonding metal layer 231 only needs to pass through the second insulating layer 22 to be in contact with the second reflective metal layer 21 to form an electrical connection.

[0056] In summary, by staggering the first reflective metal layer 19 and the second reflective metal layer 21 in the stacking height of the chip, that is, setting them in layers spatially, and adding a first insulating layer 20 between the first reflective metal layer 19 and the second reflective metal layer 21, the problem in the prior art that when the N-type reflective metal layer and the P-type reflective metal layer of a flip-chip are in the same plane, due to the short distance between the N-type reflective metal layer and the P-type reflective metal layer, short circuits are likely to occur and the chip fails rapidly after long-term aging can be completely solved.

[0057] In this embodiment, the depth of the MESA step 13 is 15%-30% of the thickness of the epitaxial layer 12, and the angle of the isolation groove 16 is 30°-80°.

[0058] In this embodiment, the material for preparing the current transmission metal layer includes one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a stack of combinations of these metals; the total thickness of the Bragg reflection layer 18 is The materials for preparing the first reflective metal layer 19 and the second reflective metal layer 21 are a stack of one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a combination of these metals; the materials for preparing the first insulating layer 20 and the second insulating layer 22 are SiO2 or SiN, and the thickness is The material for preparing the bonding metal layer is a stack of one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a combination of these metals.

[0059] Embodiment 2

[0060] Please refer to Figure 3 and Figure 4 , the second embodiment of the present invention provides a flip-chip light-emitting diode chip, which includes: a substrate 11 and an epitaxial layer 12 provided on the substrate 11; the chip further includes a current blocking layer 14, a current spreading layer 15, a current transmission metal layer, a Bragg reflection layer 18, a reflective metal layer, an insulating layer and a bonding metal layer.

[0061] It is easy for those skilled in the art to understand that the epitaxial layer 12 includes a buffer layer 121, an N-type semiconductor layer 122, an active layer 123 and a P-type semiconductor layer 124 stacked in sequence; among them, a MESA step 13 is provided on the epitaxial layer 12 to expose the N-type semiconductor layer 122, and an isolation groove 16 is provided on the MESA step 13 to expose the substrate 11.

[0062] Among them, the current transmission metal layer includes an N-type current transmission metal layer 172 and a P-type current transmission metal layer 171, and the bonding metal layer includes an N-type bonding metal layer 232 and a P-type bonding metal layer 231.

[0063] Further, the reflective metal layer includes a first reflective metal layer 19 and a second reflective metal layer 21, and the insulating layer includes a first insulating layer 20 and a second insulating layer 22. The first reflective metal layer 19 and the second reflective metal layer 21 are staggered from each other in the stacking height of the chip. The second insulating layer 22 is disposed between the first reflective metal layer 19 and the second reflective metal layer 21. Correspondingly, the first insulating layer 20 is disposed between the first reflective metal layer 19 and the bonding metal layer.

[0064] In this embodiment, the first reflective metal layer 19 is a P-type reflective metal layer, and the second reflective metal layer 21 is an N-type reflective metal layer. The first reflective metal layer 19 is higher than the second reflective metal layer 21 in the stacking height of the chip. The first reflective metal layer 19 is in contact with the P-type current transmission metal layer 172, and the second reflective metal layer 21 is in contact with the N-type current transmission metal layer 171.

[0065] Specifically, in order to make the second reflective metal layer 21 in contact with the N-type current transmission metal layer 171 to form an electrical connection, the second reflective metal layer 21 is in contact with the N-type current transmission metal layer 171 through an N-type reflective via 181 preset on the Bragg reflection layer 18 to form an electrical connection. And the first reflective metal layer 19, which is higher than the second reflective metal layer 21 in the stacking height of the chip, needs to be in contact with the P-type current transmission metal layer 172 through the first insulating layer 20 and an N-type reflective via 201 preset on the Bragg reflection layer 18 to form an electrical connection; that is, the first reflective metal layer 19 needs to pass through not only the Bragg reflection layer 18 but also the first insulating layer 20 disposed above the second reflective metal layer 21 to be in contact with the P-type current transmission metal layer 172.

[0066] Further, the P-type bonding metal layer 231 is in contact with the second reflective metal layer 21 through an insulating layer via 222 (a through hole formed by the two insulating layers being connected to each other) preset on the second insulating layer 22 and the first insulating layer 20 to form an electrical connection; that is, the P-type bonding metal layer 231 needs to pass through not only the second insulating layer 22 with a higher setting height but also the first insulating layer 20 disposed below the second insulating layer 22 to be in contact with the second reflective metal layer 21 to form an electrical connection. The N-type bonding metal layer 232 is in contact with the first reflective metal layer 19 by passing through an insulating layer via 221 (a through hole separately provided on the second insulating layer 22) preset on the second insulating layer 22 to form an electrical connection; that is, the N-type bonding metal layer 232 only needs to pass through the second insulating layer 22 to be in contact with the first reflective metal layer 19 to form an electrical connection.

[0067] In summary, by staggering the first reflective metal layer 19 and the second reflective metal layer 21 in the stacking height of the chip, that is, setting them in different layers spatially, and adding a second insulating layer 22 between the first reflective metal layer 19 and the second reflective metal layer 21, it is possible to completely solve the problems in the prior art that when the N-type reflective metal layer and the P-type reflective metal layer of a flip-chip are in the same plane, due to the too short distance between the N-type reflective metal layer and the P-type reflective metal layer, short circuits are likely to occur and the chip fails rapidly after long-term aging.

[0068] In this embodiment, the depth of the MESA step 13 is 15%-30% of the thickness of the epitaxial layer 12, and the angle of the isolation groove 16 is 30°-80°.

[0069] In this embodiment, the material for preparing the current-carrying metal layer includes one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a stack of combinations of these metals; the total thickness of the Bragg reflection layer 18 is The materials for preparing the first reflective metal layer 19 and the second reflective metal layer 21 are a stack of one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a combination of these metals; the materials for preparing the first insulating layer 20 and the second insulating layer 22 are SiO2 or SiN, and the thickness is The material for preparing the bonding metal layer is a stack of one or more of the above metals such as Cr, Al, Ti, Ni, Pt, Au, Ag or a combination of these metals.

[0070] Embodiment Three

[0071] Please refer to Figure 5 , the third embodiment of the present invention provides a flip-chip light-emitting diode chip. Compared with the second embodiment, in this embodiment, the P-type current-carrying metal layer 171 is densely arranged around the periphery of the N-type current-carrying metal layer 172.

[0072] Combined with the second embodiment, by staggering the first reflective metal layer and the second reflective metal layer in the stacking height of the chip, the corresponding P-type current-carrying metal layer and N-type current-carrying metal layer are also staggered in the stacking height of the chip, effectively reducing the lateral current transmission distance, thereby reducing the operating voltage of the chip.

[0073] Embodiment Four

[0074] Please refer to Figure 6 , the fourth embodiment of the present invention provides a method for manufacturing a flip-chip light-emitting diode chip for manufacturing the flip-chip light-emitting diode chip in the above first embodiment. The manufacturing method includes steps S10-S90:

[0075] Step S10, providing a substrate;

[0076] Step S20: fabricate an epitaxial layer on the substrate, where the epitaxial layer includes a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence.

[0077] Step S30: fabricate a MESA step on the epitaxial layer to expose the N-type semiconductor layer.

[0078] Step S40: fabricate a current blocking layer on the MESA step and the P-type semiconductor layer.

[0079] Step S50: fabricate a current spreading layer on the P-type semiconductor layer and the current blocking layer.

[0080] Step S60: etch the MESA step to remove the N-type semiconductor layer and the buffer layer at the MESA step to form an isolation groove.

[0081] Step S70: fabricate an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the spreading layer respectively.

[0082] Step S80: fabricate a Bragg reflector on the surfaces of the MESA step, the P-type semiconductor layer, the current spreading layer, and the current transmission metal layer.

[0083] Step S90: fabricate a first reflective metal layer on the Bragg reflector, a first insulating layer on the first reflective metal layer, a second reflective metal layer on the first insulating layer, a second insulating layer on the second reflective metal layer, and a bonding metal layer on the second insulating layer.

[0084] Specifically, the preparation method includes the following steps:

[0085] First, provide a substrate.

[0086] Next, grow an epitaxial layer on the substrate; the epitaxial layer from bottom to top is a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer 124 in sequence.

[0087] Next, prepare the MESA step; form a pattern on the surface of the P-type semiconductor layer through a photolithography process, and then through an ICP (Inductively Coupled Plasma) etching process, remove part of the P-type semiconductor layer 124, the active layer, and the N-type semiconductor layer to expose the MESA step, and then remove the photoresist; the depth of the MESA step is 15%-30% of the epitaxial layer.

[0088] Next, prepare the current blocking layer; deposit SiO2 on the surface of the P-type semiconductor layer 124 and the MESA step by PECVD (Physical Vapor Deposition with Chemical Reaction) process, then form a pattern by photolithography, then remove part of the SiO2 with a SiO2 etching solution, and then remove the photoresist; the material of the current blocking layer is SiO2 or SiN, and the thickness is

[0089] Next, prepare the current spreading layer; deposit ITO (indium tin oxide) on the MESA step, the surface of the P-type semiconductor layer 124, and the surface of the current blocking layer by magnetron sputtering, then form a pattern by photolithography, then remove part of the ITO with ITO etchant, and then remove the photoresist; the material of the current spreading layer is ITO (indium tin oxide) or Ag, and the thickness is

[0090] Next, prepare the isolation groove. Through photolithography, expose the part to be etched on the MESA step, and then use ICP etching to remove part of the N-type semiconductor layer and the buffer layer at the MESA step to expose the substrate and form the isolation groove; the angle of the isolation groove is 30° - 80°;

[0091] Next, prepare the current-transporting metal layer; first form a pattern by photolithography, then evaporate the metal, then use the blue film stripping technique to remove part of the metal layer, and then remove the photoresist; the material of the metal layer is a stack of one or more of the above metals selected from Cr, Al, Ti, Ni, Pt, Au, Ag; the current-transporting metal layer is divided into an N-type current-transporting metal layer and a P-type current-transporting metal layer;

[0092] Next, prepare the Bragg reflector; deposit a stack of SiO2 and Ti3O5 on the MESA step, the P-type semiconductor layer 124, the current spreading layer, and the current-output metal layer by evaporation, and then form a pattern by photolithography; then use the ICP etching process to remove part of the Bragg reflector to form a through hole in the Bragg reflector, and then remove the photoresist; the total thickness of the Bragg reflector is

[0093] Next, prepare the first reflective metal layer. First form a pattern by photolithography, then evaporate the metal, then use the blue film stripping technique to remove part of the metal layer, and then remove the photoresist; the material of the first reflective metal layer is a stack of one or more of the above metals selected from Cr, Al, Ti, Ni, Pt, Au, Ag;

[0094] Next, prepare the first insulating layer. Deposit SiO2 on the Bragg reflector and the first reflective metal layer by PECVD (physical chemical vapor deposition), then form a pattern by photolithography, and then use the ICP etching process to remove part of the SiO2 and the Bragg reflector under the SiO2 to form the first insulating layer and the through hole in the Bragg reflector; the material of the first insulating layer is SiO2 or SiN, and the thickness is

[0095] Next, prepare the second reflective metal layer. First, form a pattern by photolithography, then deposit metal by evaporation, then remove part of the metal layer using the blue film stripping technique, and then remove the photoresist; the material of the second reflective metal layer is a stack of one or more of the above metals selected from Cr, Al, Ti, Ni, Pt, Au, and Ag.

[0096] Next, prepare the second insulating layer. Deposit SiO2 on the surface of the first insulating layer and the second reflective metal layer using the PECVD (Physical Vapor Deposition) process, then form a pattern by photolithography, and then use the ICP etching process to remove part of the SiO2 to form the second insulating layer, the through-hole of the first insulating layer, and the separate through-hole of the second insulating layer, and then remove the photoresist; the material of the second insulating layer is SiO2 or SiN, and the thickness is

[0097] Next, prepare the bonding metal layer; first, form a pattern by photolithography, then deposit metal by evaporation, then remove part of the metal layer using the blue film stripping technique, and then remove the photoresist; the material of the bonding metal layer is a stack of one or more of the above metals selected from Cr, Al, Ti, Ni, Pt, Au, and Ag; the bonding metal layer is divided into an N-type bonding metal layer and a P-type bonding metal layer.

[0098] Among them, the first reflective metal layer is an N-type reflective metal layer, the second reflective metal layer is a P-type reflective metal layer, the N-type reflective metal layer is electrically connected to the N-type current transmission metal layer through the through-hole of the Bragg reflection layer, the P-type reflective metal layer is electrically connected to the P-type current transmission metal layer through the first insulating layer and the through-hole of the Bragg reflection layer, the N-type bonding metal layer is electrically connected to the N-type reflective metal layer through the second insulating layer and the through-hole of the first insulating layer, and the P-type bonding metal layer is electrically connected to the P-type reflective metal layer through the separate through-hole of the second insulating layer.

[0099] Please refer to Figure 7 , in another embodiment, this preparation method is used to prepare the flip-chip light-emitting diode chip in the above second embodiment, and this preparation method directly goes from step S80 to step S91:

[0100] Step S91, fabricate a second reflective metal layer on the Bragg reflection layer, fabricate a second insulating layer on the second reflective metal layer, fabricate a first reflective metal layer on the second insulating layer, fabricate a first insulating layer on the first reflective metal layer, and fabricate a bonding metal layer on the first insulating layer.

[0101] Among them, the first reflective metal layer is a P-type reflective metal layer, and the second reflective metal layer is an N-type reflective metal layer. The P-type reflective metal layer is electrically connected to the P-type current transmission metal layer through the Bragg reflection layer via hole. The N-type reflective metal layer is electrically connected to the N-type current transmission metal layer through the first insulating layer and the Bragg reflection layer via hole. The P-type bonding metal layer is electrically connected to the P-type reflective metal layer through the second insulating layer and the first insulating layer via hole. The N-type bonding metal layer is electrically connected to the N-type reflective metal layer through a separate second insulating layer via hole.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0103] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. An inverted light-emitting diode chip, characterized in that, The chip includes: a substrate and an epitaxial layer disposed on the substrate, the epitaxial layer including a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence. Wherein, a MESA step is provided on the epitaxial layer to expose the N-type semiconductor layer, and an isolation groove is provided on the MESA step to expose the substrate; the chip further includes a current blocking layer, a current spreading layer, a current transmission metal layer, a Bragg reflection layer, a reflection metal layer, an insulating layer, and a bonding metal layer; wherein, the reflection metal layer includes a first reflection metal layer and a second reflection metal layer, the insulating layer includes a first insulating layer and a second insulating layer, the first reflection metal layer and the second reflection metal layer are staggered in the stacking height of the chip, and one of the first insulating layer and the second insulating layer is disposed between the first reflection metal layer and the second reflection metal layer. Correspondingly, the other of the first insulating layer and the second insulating layer is disposed between the first reflection metal layer or the second reflection metal layer and the bonding metal layer.

2. The flip-chip light-emitting diode chip according to claim 1, wherein the current transmission metal layer includes an N-type current transmission metal layer and a P-type current transmission metal layer; wherein, the first reflection metal layer is an N-type reflection metal layer, the second reflection metal layer is a P-type reflection metal layer, the first reflection metal layer contacts the N-type current transmission metal layer, and the second reflection metal layer contacts the P-type current transmission metal layer; alternatively, the first reflection metal layer is a P-type reflection metal layer, the second reflection metal layer is an N-type reflection metal layer, the first reflection metal layer contacts the P-type current transmission metal layer, and the second reflection metal layer contacts the N-type current transmission metal layer.

3. The flip-chip light-emitting diode chip according to claim 2, wherein, When the first reflection metal layer is an N-type reflection metal layer and the second reflection metal layer is a P-type reflection metal layer, the first reflection metal layer contacts the N-type current transmission metal layer through a preset N-type reflection through hole on the Bragg reflection layer to form an electrical connection, and the second reflection metal layer contacts the P-type current transmission metal layer through the first insulating layer and a preset P-type reflection through hole on the Bragg reflection layer to form an electrical connection.

4. The flip-chip light-emitting diode chip according to claim 3, wherein the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer; wherein, the N-type bonding metal layer contacts the first reflection metal layer through an insulating layer through hole preset on the second insulating layer and the first insulating layer to form an electrical connection, and the P-type bonding metal layer separately passes through an insulating layer through hole preset on the second insulating layer to contact the second reflection metal layer to form an electrical connection.

5. The flip-chip light-emitting diode chip according to claim 2, characterized in that, When the first reflection metal layer is a P-type reflection metal layer and the second reflection metal layer is an N-type reflection metal layer, the first reflection metal layer contacts the P-type current transmission metal layer through the first insulating layer and a preset P-type reflection through hole on the Bragg reflection layer to form an electrical connection, and the second reflection metal layer contacts the N-type current transmission metal layer through a preset N-type reflection through hole on the Bragg reflection layer to form an electrical connection.

6. The flip-chip light-emitting diode chip according to claim 5, wherein, the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer; Wherein, the N-type bonding metal layer separately passes through a preset insulating layer through hole on the second insulating layer to contact the first reflective metal layer to form an electrical connection, and the P-type bonding metal layer passes through the second insulating layer and a preset insulating layer through hole on the first insulating layer to contact the second reflective metal layer to form an electrical connection.

7. The flip-chip light-emitting diode chip according to claim 6, characterized in that, The P-type current transmission metal layer is densely arranged around the periphery of the N-type current transmission metal layer to reduce the lateral current transmission distance between the P-type current transmission metal layer and the N-type current transmission metal layer.

8. The flip-chip light-emitting diode chip according to any one of claims 1-7, characterized in that, The depth of the MESA step is 15%-30% of the thickness of the epitaxial layer.

9. The flip-chip light-emitting diode chip according to claim 8, wherein, The angle of the isolation groove is 30°-80°.

10. A method for preparing an inverted light-emitting diode chip, characterized in that, For fabricating the flip-chip light-emitting diode chip according to any one of claims 1-9, the fabrication method includes: Providing a substrate; Fabricating an epitaxial layer on the substrate, the epitaxial layer including a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence; Fabricating a MESA step on the epitaxial layer to expose the N-type semiconductor layer; Fabricating a current blocking layer on the MESA step and the P-type semiconductor layer; Fabricating a current spreading layer on the P-type semiconductor layer and the current blocking layer; Etching the MESA step to remove the N-type semiconductor layer and the buffer layer at the MESA step to fabricate an isolation groove; Fabricating an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the spreading layer respectively; Fabricating a Bragg reflection layer on the surfaces of the MESA step, the P-type semiconductor layer, the current spreading layer, and the current transmission metal layer; Fabricating a first reflective metal layer on the Bragg reflection layer, fabricating a first insulating layer on the first reflective metal layer, fabricating a second reflective metal layer on the first insulating layer, fabricating a second insulating layer on the second reflective metal layer, and fabricating a bonding metal layer on the second insulating layer; Alternatively, fabricating a second reflective metal layer on the Bragg reflection layer, fabricating a second insulating layer on the second reflective metal layer, fabricating a first reflective metal layer on the second insulating layer, fabricating a first reflective layer on the first reflective metal layer, and fabricating a bonding metal layer on the first reflective layer.

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