Device and method for measuring dynamic characteristics of wide bandgap power semiconductor field effect transistor

Abstract

The present invention proposes a device and method for measuring dynamic characteristics of a wide bandgap power semiconductor field effect transistor. The device comprises a dynamic characteristics measurement circuit module and a data acquisition module; wherein the dynamic characteristics measurement circuit module is used to apply voltage stress to a device under test to perform dynamic characteristics measurement; the data acquisition module is used to acquire electrical parameters of the device under test; the dynamic characteristics measurement circuit module comprises a control signal output circuit, a voltage stress application circuit and a clamping circuit; wherein the control signal output circuit is used to generate a driving signal to control the working state of the voltage stress application circuit; the voltage stress application circuit is used to apply gate voltage stress and drain voltage stress to the device under test; the clamping circuit is used for the data acquisition module to sample the on-state voltage drop between the drain and source of the device under test to obtain the dynamic on-state resistance of the device under test.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a device and method for measuring dynamic characteristics of a wide bandgap power semiconductor field effect transistor. Background Art

[0002] Power semiconductor electronic devices are the core components of power electronics technology. Their main function is to achieve power conversion and circuit control of power equipment by switching on and off. They are widely used in energy systems, computer systems, aerospace and other fields, and are closely related to people's lives. At present, power semiconductor electronic devices are mainly Si-based devices, but due to the switching speed and power consumption of Si-based devices, Si-based devices can no longer meet the needs of increasing power density and improving power conversion efficiency. Compared with Si-based devices, wide bandgap power semiconductor devices (GaN devices and SiC devices) have higher voltage resistance, smaller on-resistance, and faster switching speed, which can further improve the power density and efficiency of power supply systems. They have replaced some Si-based devices and are widely used in high-voltage, medium-to-high-power, and high-switching frequency applications.

[0003] However, the dynamic characteristics of GaN and SiC field effect transistors have poor stability, which is specifically manifested in two aspects: First, after a period of off-state drain voltage stress, the on-resistance of the GaN field effect transistor will increase, resulting in higher power consumption of the device in actual applications; on the other hand, after a period of gate voltage stress or off-state drain voltage stress, the threshold voltage of the GaN and SiC field effect transistors will drift, and the drift of the threshold voltage will change the on-state of the device, thereby affecting the long-term stability of the device. The unstable characteristics of the device will lead to instability in the operation of the system, and in severe cases, the system will not work properly. Therefore, in order to quantitatively evaluate the power consumption and performance of wide bandgap power semiconductor devices in actual applications, it is necessary to characterize and measure the dynamic characteristics of the device.

[0004] However, the traditional threshold voltage and on-resistance measurement method belongs to static measurement, that is, the threshold voltage and on-resistance of the device are obtained by measuring the static characteristic curve of the device through a power device analyzer. Since there is a time lag from the device being subjected to external stress to the measurement of the dynamic characteristics of the device, and wide bandgap power devices are usually under dynamic working conditions of high-speed switching, conventional static measurement methods cannot timely and accurately reflect the actual performance of the device. Therefore, it is necessary to use a dynamic measurement method that is more accurate and appropriate.

[0005] Furthermore, as shown in the Chinese invention patent published on June 15, 2021: A wide-bandgap semiconductor power device parameter testing platform and method, existing dynamic characteristics measurement devices can only measure the dynamic threshold voltage or the dynamic on-resistance separately, and their functions are not comprehensive. There is a lack of dynamic characteristics testing devices that can measure both the dynamic threshold voltage and the dynamic on-resistance. Therefore, it is not conducive to quickly measuring the dynamic characteristics of the device and evaluating the performance of the device, which limits the efficiency of the test work. Summary of the invention

[0006] In view of the limitations of the prior art, the present invention proposes a device for measuring dynamic characteristics of a wide bandgap power semiconductor field effect transistor. The technical solution adopted by the present invention is:

[0007] A device for measuring dynamic characteristics of a wide bandgap power semiconductor field effect transistor comprises a dynamic characteristics measurement circuit module and a data acquisition module; wherein the dynamic characteristics measurement circuit module is used to apply voltage stress to a device under test to measure dynamic characteristics; and the data acquisition module is used to collect electrical parameters of the device under test;

[0008] The dynamic characteristic measurement circuit module includes a control signal output circuit, a voltage stress application circuit and a clamping circuit; wherein the control signal output circuit is used to generate a drive signal to control the working state of the voltage stress application circuit; the voltage stress application circuit is used to apply gate voltage stress and drain voltage stress to the device under test; the clamping circuit is used for the data acquisition module to sample the on-state voltage drop between the drain and source of the device under test to obtain the dynamic on-state resistance of the device under test.

[0009] Compared with the prior art, the present invention provides a solution for measuring the dynamic characteristics of wide bandgap power semiconductor power devices, which has the function of measuring dynamic threshold voltage and dynamic on-resistance, overcoming the problem that the existing dynamic characteristics measurement devices have a single function and do not have the two functions of measuring the dynamic threshold voltage and dynamic on-resistance of wide bandgap devices at the same time, thereby achieving more efficient and comprehensive evaluation of the performance of wide bandgap field effect transistors and improving test efficiency.

[0010] As a preferred solution, the control signal output circuit is a field programmable gate array circuit.

[0011] As a preferred solution, the voltage stress application circuit includes a programmable power supply, a single-pole double-throw analog switch chip S1, a single-pole double-throw analog switch chip S2, a transistor Q1, an inductor L, a diode D, a resistor R, a capacitor C1 and a high-voltage power supply VBUS; wherein:

[0012] The "2" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the output end of the programmable power supply, the "3" port of the signal input end is connected to the output pin of the control signal output circuit, and the "1" port of the signal output end is connected to the gate of the device under test DUT;

[0013] The "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the source of the transistor Q1, the "3" port of the signal input end is connected to the output end of the programmable power supply, and the "1" port of the signal output end is connected to the drain of the device under test DUT;

[0014] The left end of the inductor L is connected to the drain of the transistor Q1, and the right end is connected to the positive electrode of the high voltage power supply VBUS;

[0015] The anode of the diode D is connected to the left end of the inductor L, and the cathode is connected to the right end of the inductor L;

[0016] The left end of the resistor R is connected to the source of the device under test DUT, and the right end is connected to the negative electrode of the high voltage power supply VBUS;

[0017] The upper end of the capacitor C1 is connected to the positive electrode of the high-voltage power supply VBUS, and the lower end is connected to the negative electrode of the high-voltage power supply VBUS.

[0018] Furthermore, the programmable power supply includes two switchable operating modes: a voltage source mode and a current source mode; when the programmable power supply operates in the voltage source mode, the output voltage value can be adjusted to a positive voltage with a level higher than GND or a negative voltage with a level lower than GND; when the programmable power supply operates in the current source mode, the output current value can be adjusted.

[0019] Furthermore, the control signal output circuit is provided with 5 output pins for connecting to the voltage stress applying circuit for signal transmission, and in the control signal output circuit:

[0020] The output pin 1 is connected to the gate of the transistor Q1 to control the on and off of the transistor Q1;

[0021] The output pin 2 is connected to the signal input terminal of the programmable power supply to control the output and stop the output of the programmable power supply;

[0022] The output pin 3 is connected to the control end of the single-pole double-throw analog switch chip S2 to control the connection state of the "2", "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S2;

[0023] The output pin 4 is connected to the control end of the single-pole double-throw analog switch chip S1 to control the connection states of the "2" and "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S1;

[0024] The output pin 5 is connected to the "3" port of the signal input end of the single-pole double-throw analog switch chip S1 to control the on and off of the device under test DUT.

[0025] Furthermore, the clamping circuit obtains the dynamic on-resistance of the device under test DUT by dividing the on-voltage drop between the drain and source of the device under test DUT by the current flowing through the resistor R.

[0026] As a preferred solution, the clamping circuit includes diodes D1, D2, D3, D4, a resistor R5 and an auxiliary power supply V1; wherein:

[0027] The anode of the diode D1 is connected to the cathode of the diode D2, and the cathode of the diode D1 is connected to the drain of the device under test DUT;

[0028] The anode of the diode D2 is connected to the left end of the resistor R5, and the cathode of the diode D2 is connected to the anode of the diode D3;

[0029] The anode of the diode D3 is connected to the cathode of the diode D4, and the cathode of the diode D3 is connected to the right end of the resistor R5;

[0030] The anode of the diode D4 is connected to the source of the device under test DUT;

[0031] The positive electrode of the auxiliary power supply V1 is connected to the cathode of the diode D3 , and the negative electrode of the auxiliary power supply V1 is connected to the source of the device under test DUT.

[0032] As a preferred solution, the data acquisition module is an oscilloscope.

[0033] The present invention also includes the following contents:

[0034] A measurement method based on the aforementioned wide bandgap power semiconductor field effect transistor dynamic characteristic measurement device measures the dynamic threshold voltage of the device under test by the following steps:

[0035] S11, applying gate voltage stress to the device under test;

[0036] S12, applying drain voltage stress to the device under test;

[0037] S13, applying gate voltage stress and drain voltage stress to the device under test simultaneously;

[0038] S2, collecting the voltage difference between the gate and the source of the device under test according to the results of steps S11, S12 and S13, and obtaining the dynamic threshold voltage of the device under test.

[0039] Furthermore, the dynamic on-resistance of the device under test can be measured by the following steps:

[0040] S3, put the device under test into the on state;

[0041] S4, obtaining the current IR across the resistor R, the voltage Va between the diode D1 and the resistor R5 in the clamping circuit, and the voltage Vb between the diode D1 and D;

[0042] S5, according to the formula: Ron = (2*Vb-Va) / IR, obtain the dynamic on-resistance Ron of the device under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a dynamic characteristic measurement device for a wide bandgap power semiconductor field effect transistor provided by an embodiment of the present invention;

[0044] Figure 2 This is an example of applying voltage stress to the gate of a device under test by a test circuit according to an embodiment of the present invention;

[0045] Figure 3 This is an example of measuring the dynamic threshold voltage of a device under test after a test circuit according to an embodiment of the present invention applies voltage stress to a gate of the device under test;

[0046] Figure 4 For the embodiment of the present invention Figure 3 , 4 The switching waveform timing diagram of the circuit components in the example below;

[0047] Figure 5 This is an example of applying voltage stress to the drain of a device under test according to an embodiment of the present invention;

[0048] Figure 6 This is an example of measuring the dynamic threshold voltage of a device under test after applying voltage stress to the drain of the device under test according to an embodiment of the present invention;

[0049] Figure 7 For the embodiment of the present invention Figure 5 , 6 The switching waveform timing diagram of the circuit components in the example below;

[0050] Figure 8 This is an example of applying voltage stress to the drain and gate of a device under test according to an embodiment of the present invention;

[0051] Fig. 9This is an example of measuring the dynamic threshold voltage of a device under test after applying voltage stress to the drain and gate of the device under test according to an embodiment of the present invention;

[0052] Fig.10 For the embodiment of the present invention Figure 8 , 9 The switching waveform timing diagram of the circuit components in the example below;

[0053] Fig.11 This is an example of applying voltage stress to the drain of a device under test and measuring the dynamic on-resistance of the device under test according to an embodiment of the present invention;

[0054] Fig.12 For the embodiment of the present invention Fig.11 The following is an example of a timing diagram of the switching waveforms of some circuit components. DETAILED DESCRIPTION

[0055] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0056] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0057] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0058] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0059] In addition, in the description of this application, unless otherwise specified, "multiple" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0060] In order to solve the limitations of the prior art, this embodiment provides a technical solution, and the technical solution of the present invention is further described below in conjunction with the drawings and embodiments.

[0061] Example 1

[0062] See also Figure 1 , a wide bandgap power semiconductor field effect transistor dynamic characteristic measurement device, comprising a dynamic characteristic measurement circuit module 1 and a data acquisition module 2; wherein the dynamic characteristic measurement circuit module 1 is used to apply voltage stress to the device under test to perform dynamic characteristic measurement; the data acquisition module 2 is used to collect electrical parameters of the device under test;

[0063] The dynamic characteristic measurement circuit module 1 includes a control signal output circuit 11, a voltage stress applying circuit 12 and a clamping circuit 13; wherein the control signal output circuit 11 is used to generate a drive signal to control the working state of the voltage stress applying circuit 12; the voltage stress applying circuit 12 is used to apply gate voltage stress and drain voltage stress to the device under test; the clamping circuit 13 is used for the data acquisition module 2 to sample the on-state voltage drop between the drain and source of the device under test to obtain the dynamic on-state resistance of the device under test.

[0064] Compared with the prior art, the present invention provides a solution for measuring the dynamic characteristics of wide bandgap power semiconductor power devices, which has the function of measuring dynamic threshold voltage and dynamic on-resistance, overcoming the problem that the existing dynamic characteristics measurement devices have a single function and do not have the two functions of measuring the dynamic threshold voltage and dynamic on-resistance of wide bandgap devices at the same time, thereby achieving more efficient and comprehensive evaluation of the performance of wide bandgap field effect transistors and improving test efficiency.

[0065] Example 2

[0066] See also Figure 1 , a wide bandgap power semiconductor field effect transistor dynamic characteristic measurement device, comprising a dynamic characteristic measurement circuit module 1 and a data acquisition module 2; wherein the dynamic characteristic measurement circuit module 1 is used to apply voltage stress to the device under test to perform dynamic characteristic measurement; the data acquisition module 2 is used to collect electrical parameters of the device under test;

[0067] The dynamic characteristic measurement circuit module 1 includes a control signal output circuit 11, a voltage stress applying circuit 12 and a clamping circuit 13; wherein the control signal output circuit 11 is used to generate a drive signal to control the working state of the voltage stress applying circuit 12; the voltage stress applying circuit 12 is used to apply gate voltage stress and drain voltage stress to the device under test; the clamping circuit 13 is used for the data acquisition module 2 to sample the on-state voltage drop between the drain and source of the device under test, and obtain the dynamic on-state resistance of the device under test;

[0068] As a preferred embodiment, the voltage stress applying circuit 12 includes a programmable power supply, a single-pole double-throw analog switch chip S1, a single-pole double-throw analog switch chip S2, a transistor Q1, an inductor L, a diode D, a resistor R, a capacitor C1 and a high-voltage power supply VBUS; wherein:

[0069] The "2" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the output end of the programmable power supply, the "3" port of the signal input end is connected to the output pin of the control signal output circuit, and the "1" port of the signal output end is connected to the gate of the device under test DUT;

[0070] The "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the source of the transistor Q1, the "3" port of the signal input end is connected to the output end of the programmable power supply, and the "1" port of the signal output end is connected to the drain of the device under test DUT;

[0071] The left end of the inductor L is connected to the drain of the transistor Q1, and the right end is connected to the positive electrode of the high voltage power supply VBUS;

[0072] The anode of the diode D is connected to the left end of the inductor L, and the cathode is connected to the right end of the inductor L;

[0073] The left end of the resistor R is connected to the source of the device under test DUT, and the right end is connected to the negative electrode of the high voltage power supply VBUS;

[0074] The upper end of the capacitor C1 is connected to the positive electrode of the high-voltage power supply VBUS, and the lower end is connected to the negative electrode of the high-voltage power supply VBUS.

[0075] Furthermore, the programmable power supply includes two switchable operating modes: a voltage source mode and a current source mode; when the programmable power supply operates in the voltage source mode, the output voltage value can be adjusted to a positive voltage with a level higher than GND or a negative voltage with a level lower than GND; when the programmable power supply operates in the current source mode, the output current value can be adjusted.

[0076] As a preferred embodiment, the control signal output circuit 11 is a field programmable gate array circuit.

[0077] Furthermore, the control signal output circuit 11 is provided with 5 output pins for connecting to the voltage stress applying circuit 12 for signal transmission. In the control signal output circuit 11:

[0078] The output pin 1 is connected to the gate of the transistor Q1 to control the on and off of the transistor Q1;

[0079] The output pin 2 is connected to the signal input terminal of the programmable power supply to control the output and stop the output of the programmable power supply;

[0080] The output pin 3 is connected to the control end of the single-pole double-throw analog switch chip S2 to control the connection state of the "2", "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S2;

[0081] The output pin 4 is connected to the control end of the single-pole double-throw analog switch chip S1 to control the connection states of the "2" and "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S1;

[0082] The output pin 5 is connected to the "3" port of the signal input end of the single-pole double-throw analog switch chip S1 to control the on and off of the device under test DUT.

[0083] Therefore, the present invention can switch between the two modes of applying gate voltage stress and applying drain voltage stress to the device under test by switching the working mode of the programmable power supply and switching the connection status of the single-pole double-throw analog switch chips S1 and S2, and can also simultaneously apply gate voltage stress and drain voltage stress to the device under test, thereby achieving a more comprehensive evaluation of the impact of external voltage stress on the dynamic characteristics of the wide bandgap device.

[0084] Furthermore, the clamping circuit 13 obtains the dynamic on-resistance of the device under test DUT by dividing the on-voltage drop between the drain and source of the device under test DUT by the current flowing through the resistor R.

[0085] As a preferred embodiment, the clamping circuit 13 includes diodes D1, D2, D3, D4, a resistor R5 and an auxiliary power supply V1; wherein:

[0086] The anode of the diode D1 is connected to the cathode of the diode D2, and the cathode of the diode D1 is connected to the drain of the device under test DUT;

[0087] The anode of the diode D2 is connected to the left end of the resistor R5, and the cathode of the diode D2 is connected to the anode of the diode D3;

[0088] The anode of the diode D3 is connected to the cathode of the diode D4, and the cathode of the diode D3 is connected to the right end of the resistor R5;

[0089] The anode of the diode D4 is connected to the source of the device under test DUT;

[0090] The positive electrode of the auxiliary power supply V1 is connected to the cathode of the diode D3 , and the negative electrode of the auxiliary power supply V1 is connected to the source of the device under test DUT.

[0091] As a preferred embodiment, the data acquisition module 2 is an oscilloscope, which can acquire electrical parameters of the device under test in the test circuit through a probe to achieve data acquisition.

[0092] Example 3

[0093] A measurement method implemented by the wide bandgap power semiconductor field effect transistor dynamic characteristic measurement device according to embodiment 1 or 2, measuring the dynamic threshold voltage of the device under test by the following steps:

[0094] S11, applying gate voltage stress to the device under test;

[0095] S12, applying drain voltage stress to the device under test;

[0096] S13, applying gate voltage stress and drain voltage stress to the device under test simultaneously;

[0097] S2, collecting the voltage difference between the gate and the source of the device under test according to the results of steps S11, S12 and S13, and obtaining the dynamic threshold voltage of the device under test.

[0098] Specifically, for a measurement cycle for measuring the dynamic threshold voltage of the device under test after being subjected to gate voltage stress, the measurement content is to measure the dynamic threshold voltage of the device under test after being subjected to gate voltage stress, which specifically includes a stress application stage and a dynamic characteristic measurement stage; the dynamic characteristic measurement stage is mainly to measure the dynamic threshold voltage; in the stage of applying voltage stress to the gate of the device under test, such as Figure 2 As shown, the "2" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the "1" port of the signal output end, the "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the "1" port of the signal output, the transistor Q1 works in the off state, the programmable power supply is in the voltage source mode, and is in the output voltage state. At this time, the gate of the device under test is subjected to voltage;

[0099] After completing the stage of applying voltage stress to the gate of the device under test, the stage of measuring the dynamic threshold voltage of the device under test can be immediately entered, such as Figure 3As shown, the programmable power supply is switched to the constant current source mode and is in the output current state. The "2" port of the signal input end of the single-pole double-throw analog switch chip S1 remains connected to the "1" port of the signal output end. The "1" port of the signal output of the single-pole double-throw analog switch chip S2 is switched to be connected to the "3" port of the input end. The transistor Q1 is maintained in the off state. At this time, the voltage difference between the gate and the source of the device under test is collected by an oscilloscope probe, and the obtained value is the dynamic threshold voltage of the device under test.

[0100] Figure 4 For the corresponding Figure 2 , Figure 3 The switching waveform timing diagram of the gate-source voltage of the transistor Q1 and the gate-source voltage of the device under test; At this point, a complete dynamic threshold voltage measurement cycle is completed. According to actual needs, multiple cycle tests can be continued and multiple sets of data can be recorded for comparative analysis.

[0101] Specifically, for a measurement cycle for measuring the dynamic threshold voltage of the device under test after being subjected to drain voltage stress, the measurement content is to measure the dynamic threshold voltage of the device under test after being subjected to drain voltage stress, which specifically includes a stress application stage and a dynamic characteristic measurement stage. The stress application stage is specifically a stage of applying voltage stress to the drain of the device under test, and the dynamic characteristic measurement stage is specifically a stage of measuring the dynamic threshold voltage. In the stage of applying voltage stress to the drain of the device under test, if Figure 5 As shown, the "3" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the "1" port of the signal output end, and the "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the "1" port of the signal output end. The transistor Q1 is in the on state. At this time, the drain of the device under test is subjected to voltage, and the programmable power supply is in the current source mode and is in the output current state;

[0102] After completing the stage of applying voltage stress to the drain of the device under test, the stage of measuring the dynamic threshold voltage of the device under test can be immediately entered, such as Figure 6 As shown, the transistor Q1 is switched to the off state, the programmable power supply remains in the current source mode and is in the output current state, the "1" port of the signal output end of the single-pole double-throw analog switch chip S1 is switched to be connected to the "2" port of the signal input end, and the "1" port of the signal output end of the single-pole double-throw analog switch chip S2 is switched to be connected to the "3" port of the signal input end. At this time, the voltage difference between the gate and the source of the device under test is collected by an oscilloscope probe, and the obtained value is the dynamic threshold voltage of the device under test;

[0103] Figure 7 For Figure 5 , 6The switching waveform timing diagram of the gate-source voltage of transistor Q1 and the gate-source voltage of the device under test. At this point, a complete dynamic threshold voltage measurement cycle is completed. According to actual needs, multiple cycle tests can be continued and multiple sets of data can be recorded for comparative analysis.

[0104] Specifically, for a measurement cycle for measuring the dynamic threshold voltage of the device under test after being subjected to gate and drain voltage stress at the same time, the measurement content is to measure the dynamic threshold voltage of the device under test after being subjected to gate and drain voltage stress at the same time, which specifically includes a stress application stage and a dynamic characteristic measurement stage; the stress application stage is specifically a stage of applying voltage stress to the gate and drain of the device under test at the same time, and the dynamic characteristic measurement stage is specifically a stage of measuring the dynamic threshold voltage; in the stage of applying voltage stress to the gate and drain of the device under test at the same time, if Figure 8 As shown, the "2" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the "1" port of the signal output end, and the "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the "1" port of the signal output end. The transistor Q1 is in the on state. At this time, the gate and drain of the device under test are subjected to voltage at the same time, and the programmable power supply is in the voltage source mode and is in the output voltage state;

[0105] After completing the voltage stress stage of the device under test, the dynamic threshold voltage measurement stage of the device under test is immediately entered, such as Fig. 9 As shown, the transistor Q1 is switched to the off state, the programmable power supply is switched to the current source mode and is in the output current state, the "1" port of the signal output end of the single-pole double-throw analog switch chip S1 remains connected to the "2" port of the signal input end, and the "1" port of the signal output end of the single-pole double-throw analog switch chip S2 is switched to be connected to the "3" port of the signal input end. At this time, the voltage difference between the gate and the source of the device under test is collected by an oscilloscope probe, and the obtained value is the dynamic threshold voltage of the device under test;

[0106] Fig.10 For Figure 8 , 9 The switching waveform timing diagram of the gate-source voltage of transistor Q1 and the gate-source voltage of the device under test. At this point, a complete dynamic threshold voltage measurement cycle is completed. According to actual needs, multiple cycle tests can be continued and multiple sets of data can be recorded for comparative analysis.

[0107] Furthermore, the dynamic on-resistance of the device under test can be measured by the following steps:

[0108] S3, put the device under test into the on state;

[0109] S4, obtaining the current IR across the resistor R, the voltage Va between the diode D1 and the resistor R5 in the clamping circuit 13, and the voltage Vb between the diode D1 and D;

[0110] S5, according to the formula: Ron = (2*Vb-Va) / IR, obtain the dynamic on-resistance Ron of the device under test.

[0111] Specifically, for a measurement cycle of measuring the dynamic on-resistance of the device under test after being subjected to drain voltage stress, the measurement content is to measure the dynamic on-resistance of the device under test after being subjected to drain voltage stress, which specifically includes a stress application stage and a dynamic characteristic measurement stage. Fig.11 , the stress application stage is specifically a stage of applying voltage stress to the drain of the device under test, corresponding to the stage where the gate-source voltage VGS_DUT of the device under test is at a low level, and the dynamic characteristic measurement stage is specifically a stage of measuring the dynamic on-resistance, corresponding to the stage where the gate-source voltage VGS_DUT of the device under test is at a high level; in a complete dynamic on-resistance measurement cycle, the transistor Q1 remains turned on, the "3" port of the signal input end of the single-pole double-throw analog switch chip S1 remains connected to the "1" port of the signal output end, the "2" port of the signal input end of the single-pole double-throw analog switch chip S2 remains connected to the "1" port of the signal output end, the voltage source VBUS is in a working state, and the programmable power supply is in a closed state;

[0112] When the output pin 5 of the control signal output circuit starts to output a high level, the measurement cycle starts, and the device under test is turned on twice. During the turn-on period, the drain current and drain-source voltage drop of the device under test during the second turn-on period are collected, and the dynamic on-resistance of the device under test can be obtained by dividing the drain-source voltage drop Vds by the drain current Id; wherein the drain current Id is equal to the current IR flowing through the resistor R, so by collecting the voltage drop across the resistor R, the current flowing through the resistor R can be obtained by Ohm's law, and then the drain current of the device under test can be obtained. On the other hand, the drain-source voltage drop of the device under test is obtained by collecting the voltage at point Va in the clamping circuit and then subtracting the conduction voltage drop of the diode D1. wherein, since the current flowing through the diode D2 and the current flowing through the diode D1 can be regarded as the same, the conduction voltage drop of the diode D1 is equal to Va-Vb, so the drain-source voltage drop Vds of the device under test is Vb*2-Va.

[0113] When the second pulse outputted by the output pin 5 of the control signal output circuit reaches a low level, a complete measurement cycle ends. The switching waveform timing diagram of some circuit components in the above process can be found in Fig.12 . According to actual needs, multiple cycle tests can be continued and multiple sets of data can be recorded for comparative analysis.

[0114] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A device for measuring dynamic characteristics of a wide bandgap power semiconductor field effect transistor, characterized in that: It comprises a dynamic characteristic measurement circuit module (1) and a data acquisition module (2); wherein the dynamic characteristic measurement circuit module (1) is used to apply voltage stress to the device under test to perform dynamic characteristic measurement; and the data acquisition module (2) is used to acquire electrical parameters of the device under test; The dynamic characteristic measurement circuit module (1) comprises a control signal output circuit (11), a voltage stress applying circuit (12) and a clamping circuit (13); wherein the control signal output circuit (11) is used to generate a drive signal to control the working state of the voltage stress applying circuit (12); the voltage stress applying circuit (12) is used to apply gate voltage stress and drain voltage stress to the device under test; the voltage stress applying circuit (12) comprises a programmable power supply, a single-pole double-throw analog switch chip S1, a single-pole double-throw analog switch chip S2, a transistor Q1, an inductor L, a diode D, a resistor R, a capacitor C1 and a high-voltage power supply VBUS; wherein: The "2" port of the signal input end of the single-pole double-throw analog switch chip S1 is connected to the output end of the programmable power supply, the "3" port of the signal input end is connected to the output pin of the control signal output circuit, and the "1" port of the signal output end is connected to the gate of the device under test DUT; The "2" port of the signal input end of the single-pole double-throw analog switch chip S2 is connected to the source of the transistor Q1, the "3" port of the signal input end is connected to the output end of the programmable power supply, and the "1" port of the signal output end is connected to the drain of the device under test DUT; The left end of the inductor L is connected to the drain of the transistor Q1, and the right end is connected to the positive electrode of the high voltage power supply VBUS; The anode of the diode D is connected to the left end of the inductor L, and the cathode is connected to the right end of the inductor L; The left end of the resistor R is connected to the source of the device under test DUT, and the right end is connected to the negative electrode of the high voltage power supply VBUS; The upper end of the capacitor C1 is connected to the positive electrode of the high-voltage power supply VBUS, and the lower end is connected to the negative electrode of the high-voltage power supply VBUS; The clamp circuit (13) is used for the data acquisition module (2) to sample the on-state voltage drop between the drain and source of the device under test, so as to obtain the dynamic on-state resistance of the device under test.

2. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The control signal output circuit (11) is a field programmable gate array circuit.

3. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The programmable power supply includes two switchable operating modes: a voltage source mode and a current source mode; when the programmable power supply operates in the voltage source mode, the output voltage value can be adjusted to a positive voltage with a level higher than GND or a negative voltage with a level lower than GND; when the programmable power supply operates in the current source mode, the output current value can be adjusted.

4. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The control signal output circuit (11) is provided with 5 output pins for connecting to the voltage stress applying circuit (12) for signal transmission, wherein: The output pin 1 is connected to the gate of the transistor Q1 to control the on and off of the transistor Q1; The output pin 2 is connected to the signal input terminal of the programmable power supply to control the output and stop the output of the programmable power supply; The output pin 3 is connected to the control end of the single-pole double-throw analog switch chip S2 to control the connection state of the "2" and "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S2; The output pin 4 is connected to the control end of the single-pole double-throw analog switch chip S1 to control the connection state of the "2" and "3" ports of the signal input end and the "1" port of the signal output end of the single-pole double-throw analog switch chip S1; The output pin 5 is connected to the "3" port of the signal input end of the single-pole double-throw analog switch chip S1 to control the opening and closing of the device under test DUT.

5. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The clamp circuit (13) obtains the dynamic on-resistance of the device under test DUT by dividing the on-voltage drop between the drain and source of the device under test DUT by the current flowing through the resistor R.

6. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The clamping circuit (13) comprises diodes D1, D2, D3, D4, a resistor R5 and an auxiliary power supply V1; wherein: The anode of the diode D1 is connected to the cathode of the diode D2, and the cathode of the diode D1 is connected to the drain of the device under test DUT; The anode of the diode D2 is connected to the left end of the resistor R5, and the cathode of the diode D2 is connected to the anode of the diode D3; The anode of the diode D3 is connected to the cathode of the diode D4, and the cathode of the diode D3 is connected to the right end of the resistor R5; The anode of the diode D4 is connected to the source of the device under test DUT; The positive electrode of the auxiliary power supply V1 is connected to the cathode of the diode D3 , and the negative electrode of the auxiliary power supply V1 is connected to the source of the device under test DUT.

7. The wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to claim 1, characterized in that: The data acquisition module (2) is an oscilloscope.

8. A measurement method implemented based on the wide bandgap power semiconductor field effect transistor dynamic characteristics measurement device according to any one of claims 1 to 7, characterized in that: To measure the dynamic threshold voltage of the device under test, follow these steps: S11, applying gate voltage stress to the device under test; S12, applying drain voltage stress to the device under test; S13, applying gate voltage stress and drain voltage stress to the device under test simultaneously; S2, collecting the voltage difference between the gate and the source of the device under test according to the results of steps S11, S12 and S13, and obtaining the dynamic threshold voltage of the device under test.

9. A measurement method implemented by the wide bandgap power semiconductor field effect transistor dynamic characteristic measurement device according to any one of claims 3 to 5, measuring the dynamic on-resistance of the device under test by the following steps: S3, putting the device under test in a conducting state and applying a drain voltage stress to the device under test; S4, obtaining the current IR at both ends of the resistor R, the voltage Va between the diode D1 and the resistor R5 in the clamping circuit (13), and the voltage Vb between the diode D1 and D; S5, according to the formula: Ron = (2*Vb-Va) / IR, obtain the dynamic on-resistance Ron of the device under test.

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