Method, apparatus, and device for testing a semiconductor structure
By determining parasitic resistance information in the semiconductor structure and calculating the terminal voltage, the problem of inaccurate test results is solved, resulting in more accurate test results and simplified layout design, thus improving test accuracy and design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-11
- Publication Date
- 2026-07-03
AI Technical Summary
Existing semiconductor structure testing methods often result in inaccurate test results and inconvenient structural design. In particular, the influence of parasitic resistance leads to inaccurate test results, making it difficult to accurately evaluate device characteristics and design layout.
By determining the parasitic resistance information within the semiconductor structure, and combining it with the test voltage and current of the test pads, the terminal voltage information is calculated, eliminating the influence of parasitic resistance, obtaining accurate target test results, and simplifying layout design.
It improves the testing accuracy of semiconductor structures, simplifies test structure and layout design, and ensures the accuracy of device characteristic evaluation and model accuracy.
Smart Images
Figure CN114720840B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of testing technology, and in particular to a method, apparatus, and equipment for testing semiconductor structures. Background Technology
[0002] During the development and production of semiconductor structures, various tests are required to verify whether their electrical performance meets expectations. This is typically achieved by placing test pads on the semiconductor structure, which are then connected to the semiconductor devices inside the structure, allowing for testing of the semiconductor structure.
[0003] However, the above testing methods have problems such as inaccurate test results and inconvenient structural design. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in this disclosure.
[0005] This disclosure provides a method, apparatus, and device for testing semiconductor structures.
[0006] According to a first aspect of the present disclosure, a method for testing a semiconductor structure is provided. The semiconductor structure is located on a dicing track and includes a plurality of semiconductor devices and test pads electrically connected to the semiconductor devices. The method comprises:
[0007] Determine the parasitic resistance information between the semiconductor device and the test pad;
[0008] A test voltage is applied to the test pad to test the semiconductor structure and obtain the original test results;
[0009] Based on the parasitic resistance information and the original test results, the target test result is determined.
[0010] According to some embodiments of this disclosure, the step of testing the semiconductor structure to obtain raw test results includes:
[0011] Obtain the test current of the test pad, and use the test voltage and the test current as the original test results.
[0012] According to some embodiments of this disclosure, determining the target test result based on the parasitic resistance information and the original test result includes:
[0013] Based on the test voltage, the test current, and the parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and the test current are used as the target test result.
[0014] According to some embodiments of this disclosure, the semiconductor device includes a transistor, and the test pad includes a first test pad electrically connected to the source of the transistor, a second test pad electrically connected to the drain of the transistor, a third test pad electrically connected to the gate of the transistor, and a fourth test pad electrically connected to the substrate corresponding to the transistor. The parasitic resistance information includes a first parasitic resistance between the source and the first test pad, a second parasitic resistance between the drain and the second test pad, a third parasitic resistance between the gate and the third test pad, and a fourth parasitic resistance between the bottom of the substrate corresponding to the transistor and the fourth test pad.
[0015] Applying a test voltage to the test pad includes:
[0016] A first test voltage is applied to the first test pad, a second test voltage is applied to the second test pad, a third test voltage is applied to the third test pad, and a fourth test voltage is applied to the fourth test pad.
[0017] The step of obtaining the test current of the test pad includes: obtaining the first test current of the first test pad, the second test current of the second test pad, the third test current of the third test pad, and the fourth test current of the fourth test pad, respectively.
[0018] According to some embodiments of this disclosure, determining the transistor's terminal voltage information based on the test voltage, the test current, and the parasitic resistance information includes:
[0019] The source terminal voltage Vs' of the transistor is determined according to the formula Vs'=Vs+Is*Rs, where Vs is the first test voltage applied to the source, Is is the first test current, and Rs is the first parasitic resistance;
[0020] The drain voltage Vd' of the transistor is determined according to the formula Vd'=Vd-Id*Rd, where Vd is the second test voltage applied to the drain, Id is the second test current, and Rd is the second parasitic resistance;
[0021] The gate voltage Vg' of the transistor is determined according to the formula Vg'=Vg+Ig*Rg, where Vg is the third test voltage applied to the gate, Ig is the third test current, and Rg is the third parasitic resistance;
[0022] The substrate voltage Vb' of the transistor is determined according to the formula Vb'=Vb+Ib*Rb, where Vb is the fourth test voltage applied to the substrate, Ib is the fourth test current, and Rb is the fourth parasitic resistance.
[0023] The source terminal voltage, the drain terminal voltage, the gate terminal voltage, and the substrate terminal voltage are used as the terminal voltage information.
[0024] According to some embodiments of this disclosure, the semiconductor structure includes a plurality of transistors, each of which shares the first test pad, the third test pad, and / or the fourth test pad.
[0025] According to some embodiments of this disclosure, determining the parasitic resistance information between the semiconductor device and the test pad includes:
[0026] Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line;
[0027] Based on the length information and the unit resistance value, the parasitic resistance information between the semiconductor device and the test pad is determined.
[0028] According to some embodiments of this disclosure, obtaining the length information of the connection line between the semiconductor device and the test pad includes:
[0029] Obtain the layout information of the semiconductor structure;
[0030] Extract the pattern information between the semiconductor device and the test pad from the layout information;
[0031] The length information is determined based on the pattern information.
[0032] A second aspect of this disclosure provides a testing apparatus for a semiconductor structure located on a dicing track, comprising a plurality of semiconductor devices and test pads electrically connected to the semiconductor devices, characterized in that the testing apparatus comprises:
[0033] A parasitic resistance information determination module is configured to determine parasitic resistance information between the semiconductor device and the test pad;
[0034] The raw test result acquisition module is configured to apply a test voltage to the test pad to test the semiconductor structure and obtain raw test results.
[0035] The target test result determination module is configured to determine the target test result based on the parasitic resistance information and the original test result.
[0036] According to some embodiments of this disclosure, the original test result acquisition module is configured to:
[0037] Obtain the test current of the test pad, and use the test voltage and the test current as the original test results.
[0038] According to some embodiments of this disclosure, the target test result determination module is configured to:
[0039] Based on the test voltage, the test current, and the parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and the test current are used as the target test result.
[0040] According to some embodiments of this disclosure, the semiconductor device includes a transistor, and the test pad includes a first test pad electrically connected to the source of the transistor, a second test pad electrically connected to the drain of the transistor, a third test pad electrically connected to the gate of the transistor, and a fourth test pad electrically connected to the bottom of the substrate corresponding to the transistor. The parasitic resistance information includes a first parasitic resistance between the source and the first test pad, a second parasitic resistance between the drain and the second test pad, a third parasitic resistance between the gate and the third test pad, and a fourth parasitic resistance between the bottom of the substrate corresponding to the transistor and the fourth test pad.
[0041] The original test result acquisition module is configured to:
[0042] A first test voltage is applied to the first test pad, a second test voltage is applied to the second test pad, a third test voltage is applied to the third test pad, and a fourth test voltage is applied to the fourth test pad.
[0043] The first test current of the first test pad, the second test current of the second test pad, the third test current of the third test pad, and the fourth test current of the fourth test pad are obtained respectively.
[0044] According to some embodiments of this disclosure, the target test result determination module is configured to:
[0045] The source terminal voltage Vs' of the transistor is determined according to the formula Vs'=Vs+Is*Rs, where Vs is the first test voltage applied to the source, Is is the first test current, and Rs is the first parasitic resistance;
[0046] The drain voltage Vd' of the transistor is determined according to the formula Vd'=Vd-Id*Rd, where Vd is the second test voltage applied to the drain, Id is the second test current, and Rd is the second parasitic resistance;
[0047] The gate voltage Vg' of the transistor is determined according to the formula Vg'=Vg+Ig*Rg, where Vg is the third test voltage applied to the gate, Ig is the third test current, and Rg is the third parasitic resistance;
[0048] The substrate voltage Vb' of the transistor is determined according to the formula Vb'=Vb+Ib*Rb, where Vb is the fourth test voltage applied to the substrate, Ib is the fourth test current, and Rb is the fourth parasitic resistance.
[0049] The source terminal voltage, the drain terminal voltage, the gate terminal voltage, and the substrate terminal voltage are used as the terminal voltage information.
[0050] According to some embodiments of this disclosure, the semiconductor structure includes a plurality of transistors, each of which shares the first test pad, the third test pad, and / or the fourth test pad.
[0051] According to some embodiments of this disclosure, the parasitic resistance information determination module is configured to:
[0052] Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line;
[0053] Based on the length information and the unit resistance value, the parasitic resistance information between the semiconductor device and the test pad is determined.
[0054] According to some embodiments of this disclosure, the parasitic resistance information determination module is configured to:
[0055] Obtain the layout information of the semiconductor structure;
[0056] Extract the pattern information between the semiconductor device and the test pad from the layout information;
[0057] The length information is determined based on the pattern information.
[0058] A third aspect of this disclosure provides a test apparatus for semiconductor structures, the test apparatus comprising:
[0059] processor;
[0060] Memory used to store processor-executable instructions;
[0061] The processor is configured to execute:
[0062] Determine the parasitic resistance information between the semiconductor device and the test pad;
[0063] A test voltage is applied to the test pad to test the semiconductor structure and obtain the original test results;
[0064] Based on the parasitic resistance information and the original test results, the target test result is determined.
[0065] In the semiconductor structure testing method, apparatus, and equipment provided in this disclosure, the parasitic resistance information between the semiconductor device and the test pad within the semiconductor structure is first determined. Then, the semiconductor structure is tested through the test pad to obtain the original test result. Finally, the target test result is determined based on the parasitic resistance information and the original test result. Since parasitic resistance information is introduced in the process of determining the target test result, accurate test results of the semiconductor device can be obtained, thereby improving the testing accuracy of the semiconductor structure. Furthermore, when designing the test structure and layout, there is no need to consider the parasitic resistance factor, which facilitates the design of the test structure and layout and improves design efficiency.
[0066] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0067] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.
[0068] Figure 1 This is a schematic diagram illustrating the connection between a transistor and a test pad, as shown in the example.
[0069] Figure 2 This is a flowchart illustrating a test method for a semiconductor structure according to an exemplary embodiment;
[0070] Figure 3 This is a schematic diagram illustrating the connection between a transistor and a test pad according to an exemplary embodiment;
[0071] Figure 4 This is a schematic diagram illustrating the connection of multiple transistors to test pads according to an exemplary embodiment;
[0072] Figure 5 This is a flowchart illustrating a test method for a semiconductor structure according to an exemplary embodiment;
[0073] Figure 6 This is a flowchart illustrating a test method for a semiconductor structure according to an exemplary embodiment;
[0074] Figure 7 This is a flowchart illustrating a test method for a semiconductor structure according to an exemplary embodiment;
[0075] Figure 8 This is a block diagram illustrating a test apparatus for a semiconductor structure according to an exemplary embodiment;
[0076] Figure 9 This is a block diagram illustrating a test apparatus for a semiconductor structure according to an exemplary embodiment.
[0077] 10. Transistor; 11. Source; 12. Drain; 13. Gate; 21. First metal line; 22. Second metal line; 23. Third metal line; 24. Fourth metal line; 31. First test pad; 32. Second test pad; 33. Third test pad; 34. Fourth test pad; 41. Gate connection line; 42. Drain connection line; 43. Source main connection line; 44. Substrate main connection line; 45. Source connection branch line; 46. Substrate connection branch line;
[0078] 301. Parasitic resistance information determination module; 302. Raw test result acquisition module; 303. Target test result determination module;
[0079] 400. Computer equipment; 401. Processor; 402. Memory. Detailed Implementation
[0080] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0081] When testing semiconductor structures, test pads are typically placed on the semiconductor structure to perform testing. However, inaccurate test results can occur. Research has shown that a wafer consists of a chip and dicing channels. Individual bare chips are obtained by cutting the dicing channels. To accurately monitor the electrical performance of the semiconductor structure within the chip, identical test structures are arranged along the dicing channels to test whether the electrical performance of the semiconductor structure meets design expectations. To save space along the dicing channels, multiple repetitive semiconductor devices are often designed on a single dicing channel, and these identically designed devices can share test pads. Test pads are typically electrically connected to the semiconductor devices within the semiconductor structure via metal interconnects. During testing, the signal at the test pad is detected. Because of the metal interconnects between the test pad and the semiconductor device, parasitic resistance is generated by the metal interconnects, causing the signal at the test pad to not reflect the true signal at the semiconductor device, thus affecting the accuracy of the test. In particular, as semiconductor structures become more compact, the aforementioned metal interconnects need to be laid out in a smaller area. This requires the metal interconnects to be narrower, which further increases their parasitic resistance and consequently reduces the accuracy of the test results.
[0082] Taking the testing of transistors in a semiconductor structure as an example, such as Figure 1 As shown, the source 11 of transistor 10 is connected to the first test pad 31 via a first metal line 21, the drain 12 of transistor 10 is connected to the second test pad 32 via a second metal line 22, the gate 13 of transistor 10 is connected to the third test pad 33 via a third metal line 23, and the bottom of the substrate corresponding to transistor 10 is connected to the fourth test pad 34 via a fourth metal line 24. During testing, test voltages can be applied to the first test pad 31, second test pad 32, third test pad 33, and fourth test pad 34 respectively, and the current at each pad can be collected as the test result. Because parasitic resistance is generated on the first metal line 21, the test voltage applied to the first test pad 31 will experience a voltage drop when passing through the first metal line 21. Therefore, the voltage actually applied to the source 11 of transistor 10 is not a test voltage, resulting in inaccurate test results. Similarly, parasitic resistance is also generated on the second metal line 22, third metal line 23, and fourth metal line 24, which also causes inaccurate test results.
[0083] In addition, semiconductor devices with the same design share test pads, but the distance between different semiconductor devices and the connection to the test pads is different, resulting in different parasitic resistances.
[0084] Based on this, this disclosure provides a method for testing semiconductor structures. First, the parasitic resistance information between the semiconductor device and the test pad within the semiconductor structure is determined. Then, the semiconductor structure is tested through the test pad to obtain the original test results. Finally, the target test result is determined based on the parasitic resistance information and the original test results. Since parasitic resistance information is introduced in the process of determining the target test result, accurate test results of the semiconductor device can be obtained, thereby improving the testing accuracy of the semiconductor structure. Furthermore, when designing the test structure and layout, there is no need to consider the parasitic resistance factor, which facilitates the design of the test structure and layout and improves design efficiency.
[0085] This disclosure provides an exemplary embodiment of a method for testing a semiconductor structure located on a dicing track. Exemplarily, the semiconductor structure includes a plurality of semiconductor devices and test pads electrically connected to the semiconductor devices. The semiconductor devices can be, for example, transistors, resistors, etc. The test pads are electrically connected to the semiconductor devices, thereby enabling the transmission of test signals to the semiconductor devices via the test pads. Figure 2 As shown, the testing method for this semiconductor structure includes the following steps:
[0086] S100, Determine the parasitic resistance information between the semiconductor device and the test pad.
[0087] In this step, the parasitic resistance information between the semiconductor device and the test pad is first determined. For example, when there is only one test pad, the parasitic resistance value between the test pad and the semiconductor device is determined, and this parasitic resistance value is used as the parasitic resistance information. When there are multiple test pads, the parasitic resistance value between each test pad and the semiconductor device is determined, and these multiple parasitic resistance values are used as the parasitic resistance information.
[0088] Parasitic resistance information can be pre-set or measured and calculated based on the connection structure between the semiconductor device and the test pad.
[0089] S200: Apply a test voltage to the test pad to test the semiconductor structure and obtain the original test results.
[0090] This step is the specific testing process for the semiconductor structure. By applying a test voltage to the test pad, the semiconductor structure is tested, thereby obtaining the original test results without introducing parasitic resistance information.
[0091] S300: Based on parasitic resistance information and original test results, determine the target test result.
[0092] In this step, the target test result is determined by combining the parasitic resistance information and the original test results. The resulting target test result can eliminate the influence of the parasitic resistance information.
[0093] The semiconductor structure testing method provided in this embodiment first determines the parasitic resistance information between the semiconductor device and the test pad within the semiconductor structure. Then, the semiconductor structure is tested through the test pad to obtain the original test results. Finally, the target test result is determined based on the parasitic resistance information and the original test results. Because parasitic resistance information is introduced in the determination of the target test result, accurate test results for the semiconductor device can be obtained, thereby improving the testing accuracy of the semiconductor structure. Furthermore, when designing the test structure and layout, there is no need to consider parasitic resistance factors, which facilitates the design of the test structure and layout and improves design efficiency. The improved accuracy of the test results provides a strong guarantee for accurately evaluating device characteristics and generating accurate device models.
[0094] In an exemplary embodiment of this disclosure, step S200 specifically includes:
[0095] Obtain the test current of the test pad, and use the test voltage and test current as the raw test results.
[0096] In this embodiment, the test current of the test pad is obtained so that the actual voltage of the semiconductor device can be determined in the subsequent test based on the test voltage, test current and parasitic resistance information determined in step S100.
[0097] In one embodiment, step S300 specifically includes:
[0098] Based on the test voltage, test current, and parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and test current are used as the target test results.
[0099] In this embodiment, the test voltage applied to the test pad and the parasitic resistance information between the test pad and the semiconductor device are both known. In step S200, the test current of the test pad is obtained, thus determining the actual terminal voltage information of the semiconductor device. For example, when the semiconductor device has one connection terminal to the test pad, the terminal voltage value of that connection terminal is determined and used as the terminal voltage information. When the semiconductor device has multiple connection terminals to the test pad, the terminal voltage values of each connection terminal are determined, and the multiple terminal voltage values are used as the terminal voltage information.
[0100] In an exemplary embodiment of this disclosure, such as Figure 3As shown, the semiconductor device includes a transistor 10, which has a source 11, a drain 12, and a gate 13. The test pads include a first test pad 31 electrically connected to the source 11 of the transistor 10, a second test pad 32 electrically connected to the drain 12 of the transistor 10, a third test pad 33 electrically connected to the gate 13 of the transistor 10, and a fourth test pad 34 electrically connected to the bottom of the substrate corresponding to the transistor 10. Accordingly, the parasitic resistance information includes a first parasitic resistance Rs between the source 11 and the first test pad 31, a second parasitic resistance Rd between the drain 12 and the second test pad 32, a third parasitic resistance Rg between the gate 13 and the third test pad 33, and a fourth parasitic resistance Rb between the bottom of the substrate corresponding to the transistor 10 and the fourth test pad 34.
[0101] In this embodiment, applying test voltages to the test pads includes applying a first test voltage Vs, a second test voltage Vd, a third test voltage Vg, and a fourth test voltage Vb to the first test pad 31, the second test pad 32, the third test pad 33, and the fourth test pad 34, respectively.
[0102] Accordingly, the test current of the test pads is obtained, including: obtaining the first test current Is of the first test pad 31, the second test current Id of the second test pad 32, the third test current Ig of the third test pad 33, and the fourth test current Ib of the fourth test pad 34, respectively.
[0103] Thus, based on the test voltage, test current, and parasitic resistance information, the terminal voltage information of transistor 10 is determined, including:
[0104] The source voltage Vs' of transistor 10 is determined based on the first test voltage Vs, the first test current Is, and the first parasitic resistance Rs. For example, the source voltage Vs' of transistor 10 is calculated according to the formula: Vs'=Vs+Is*Rs. Usually, the first test voltage Vs is 0, then Vs'=Is*Rs. Of course, it is understood that in other embodiments, the first test voltage Vs can also be a bias voltage.
[0105] The drain voltage of transistor 10 is determined based on the second test voltage Vd, the second test current Id, and the second parasitic resistance Rd. For example, the drain voltage Vd' of transistor 10 can be calculated using the formula: Vd'=Vd-Id*Rd.
[0106] Based on the third test voltage Vg, the third test current Ig, and the third parasitic resistance Rg, the gate voltage Vg' of transistor 10 is determined. For example, the gate voltage Vg' of transistor 10 can be calculated according to the formula: Vg'=Vg+Ig*Rg. Usually, the gate test current Ig can be ignored as 0 (on the order of Pa), then Vg'=Vg.
[0107] The fourth terminal voltage Vb' of transistor 10 is determined based on the fourth test voltage Vb, the fourth test current Ib, and the fourth parasitic resistance Rb. For example, the substrate terminal voltage Vb' of transistor 10 is calculated according to the formula: Vb'=Vb+Ib*Rb. Usually, the fourth test voltage Vb is set to 0, then Vb'=Ib*Rb. Of course, it is understood that in other embodiments, the fourth test voltage Vb can also be a bias voltage.
[0108] Thus, the calculated source voltage Vs', drain voltage Vd', gate voltage Vg', and substrate voltage Vb' are used as terminal voltage information. Then, the source voltage Vs', drain voltage Vd', gate voltage Vg', substrate voltage Vb', first test current Is, second test current Id, third test current Ig, and fourth test current Ib are determined as the target test results and output.
[0109] In some embodiments, the semiconductor structure includes a single transistor 10, which can be directly tested using the methods described in the above embodiments. In other embodiments, the semiconductor structure typically includes multiple transistors 10, in which case multiple transistors 10 need to be tested. Each transistor 10 shares a first test pad 31, allowing the source of each transistor 10 to be set to a voltage of 0 (e.g., grounded) or a bias voltage. Each transistor 10 may also share a fourth test pad 34, allowing the substrate of each transistor to be set to a voltage of 0 (e.g., grounded) or a bias voltage. By providing shared test pads for each transistor 10, the structure of the test circuit and the testing process can be simplified. It is understood that in other embodiments, each transistor 10 may also share a third test pad 33.
[0110] For example, such as Figure 4 As shown, the semiconductor structure includes a plurality of transistors 10 arranged at intervals along a first direction. The gate 13 of each transistor 10 is respectively provided with a third test pad 33. For example, the gate 13 of each transistor 10 is connected to the third test pad 33 via a gate connection line 41. The drain 12 of each transistor 10 is respectively provided with a second test pad 32. For example, the drain 12 of each transistor 10 is connected to the second test pad 32 via a drain connection line 42. Figure 4As shown, on one side of a row of transistors 10, the test pads are arranged at intervals in the manner of third test pad 33, second test pad 32, third test pad 33, second test pad 32...
[0111] Each transistor 10 has its source 11 connected to a first test pad 31, and each transistor 10's corresponding substrate is connected to a fourth test pad 34. For example, continue to refer to Figure 4 On the side where the third test pad 33 and the second test pad 32 are located, the first test pad 31 and the fourth test pad 34 are located in the gap area between the second test pad 32 and the third test pad 33 of two transistors 10. On the opposite side where the third test pad 33 and the second test pad 32 are located, a source interconnect line 43 and a substrate interconnect line 44 are respectively provided. The source 11 of each transistor 10 is connected to the source interconnect line 43 through a source interconnect branch line 45, and the bottom of the corresponding substrate of each transistor 10 is connected to the substrate interconnect line 44 through a substrate interconnect branch line 46. The source interconnect line 43 is connected to the first test pad 31, and the substrate interconnect line 44 is connected to the fourth test pad 34.
[0112] In step S100, the parasitic resistance information between the semiconductor device and the test pad can be detected in advance by manual measurement, or the parasitic resistance information can be calculated with the assistance of EDA (Electronic Design Automation) tools. In an exemplary embodiment of this disclosure, as... Figure 5 As shown, step S100 includes the following steps:
[0113] S110. Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line;
[0114] S120. Based on the length information and unit resistance value, determine the parasitic resistance information between the semiconductor device and the test pad.
[0115] When laying out the connection lines between semiconductor devices and test pads, the width of the connection lines is usually fixed. Given a fixed material, the length of the connection line is directly proportional to its resistance. Therefore, in this embodiment, the resistance of the connection line can be determined based on its information and unit resistance value. This resistance value is also the parasitic resistance between the semiconductor device and the test pads. The unit resistance value mentioned here refers to the resistance per unit length of the connection line. This unit resistance value is related to the material of the connection line and can be obtained through prior measurement.
[0116] In some embodiments, the connection line between the semiconductor device and the test pad comprises multiple segments, each with a different width and / or material. The different widths and materials result in different unit resistance values for the connection line. In these embodiments, such as... Figure 6 As shown, the unit resistance of the connecting wire can be determined in the following way:
[0117] S111a. Determine the configuration information, which is used to characterize the relationship between the width, material, and unit resistance of the connecting wire.
[0118] Configuration information can be in the form of tables, mappings, etc. This information can be preset or added to, deleting from, and modified according to actual needs. For example, when the parasitic resistance of a material decreases due to optimized processing technology, the unit resistance value corresponding to that material in the configuration information can be updated. As another example, if the width of the connecting wire can be further reduced due to process optimization, new width values, along with the corresponding material and unit resistance value for each width value, can be added to the configuration information.
[0119] S112a. Based on the width, material, and defined configuration information of the connecting wire, determine the unit resistance value of the connecting wire.
[0120] For example, the width and material of each segment of the connecting line are obtained respectively, and the unit resistance value of each segment of the connecting line is determined by searching in the configuration information based on the width and material of each segment of the connecting line.
[0121] In this embodiment, after determining the unit resistance value of each connecting line segment, the parasitic resistance value of each connecting line segment can be determined based on the length of each connecting line segment and the unit resistance value of each connecting line segment. The parasitic resistance value of the entire connecting line segment is obtained by adding the parasitic resistance values of each connecting line segment.
[0122] In an exemplary embodiment of this disclosure, such as Figure 7 As shown, the method for obtaining the length information of the connection line between the semiconductor device and the test pad includes the following steps:
[0123] S111b: Obtain the layout information of the semiconductor structure.
[0124] When designing a semiconductor structure, a layout design is performed. The layout includes pattern information of each layer in the semiconductor structure. This step involves obtaining the layout information of the semiconductor structure so that relevant information about the subsequent interconnect lines can be extracted.
[0125] S112b: Extract the pattern information between the semiconductor device and the test pad from the layout information.
[0126] In this step, the pattern information between the semiconductor device and the test pad is extracted from the layout information. The extracted pattern information is the pattern information of the connection lines between the semiconductor device and the test pad. For example, the semiconductor device includes a transistor, and the pattern information between the transistor and the test pad includes the pattern information of the connection line between the source of the transistor and the first test pad, the pattern information of the connection line between the drain and the second test pad, the pattern information of the connection line between the gate and the third test pad, and the pattern information of the connection line between the bottom of the substrate corresponding to the transistor and the fourth test pad.
[0127] S113b. Determine the length information based on the pattern information.
[0128] After extracting the pattern information between the semiconductor device and the test pads, the length information of the connection lines can be obtained from this pattern information. For example, the length information of the connection line between the source of the transistor and the first test pad, the length information of the connection line between the drain and the second test pad, the length information of the connection line between the gate and the third test pad, and the length information of the connection line between the bottom of the substrate corresponding to the transistor and the fourth test pad can be obtained.
[0129] Figure 8 A block diagram of a test apparatus for a semiconductor structure is shown according to an exemplary embodiment. Figure 8 As shown, the device includes at least a parasitic resistance information determination module 301, a raw test result acquisition module 302, and a target test result determination module 303.
[0130] Parasitic resistance information determination module 301 is configured to determine parasitic resistance information between the semiconductor device and the test pad;
[0131] The raw test result acquisition module 302 is configured to apply a test voltage to the test pad to test the semiconductor structure and obtain the raw test result.
[0132] The target test result determination module 303 is configured to determine the target test result based on parasitic resistance information and the original test result.
[0133] In one exemplary embodiment, the original test result acquisition module 302 is configured to:
[0134] Obtain the test current of the test pad, and use the test voltage and test current as the raw test results.
[0135] In one exemplary embodiment, the target test result determination module 303 is configured to:
[0136] Based on the test voltage, test current, and parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and test current are used as the target test results.
[0137] In one exemplary embodiment, the semiconductor device includes a transistor, and the test pads include a first test pad electrically connected to the source of the transistor, a second test pad electrically connected to the drain of the transistor, a third test pad electrically connected to the gate of the transistor, and a fourth test pad electrically connected to the bottom of a substrate corresponding to the transistor. The parasitic resistance information includes a first parasitic resistance between the source and the first test pad, a second parasitic resistance between the drain and the second test pad, a third parasitic resistance between the gate and the third test pad, and a fourth parasitic resistance between the bottom of the substrate corresponding to the transistor and the fourth test pad.
[0138] The raw test result acquisition module 302 is configured to be used for:
[0139] A first test voltage is applied to the first test pad, a second test voltage is applied to the second test pad, a third test voltage is applied to the third test pad, and a fourth test voltage is applied to the fourth test pad.
[0140] The first test current of the first test pad, the second test current of the second test pad, the third test current of the third test pad, and the fourth test current of the fourth test pad are obtained respectively.
[0141] The target test result determination module 303 is configured to:
[0142] The source terminal voltage Vs' of the transistor is determined according to the formula Vs'=Vs+Is*Rs, where Vs is the first test voltage applied to the source, Is is the first test current, and Rs is the first parasitic resistance;
[0143] The drain voltage Vd' of the transistor is determined according to the formula Vd'=Vd-Id*Rd, where Vd is the second test voltage applied to the drain, Id is the second test current, and Rd is the second parasitic resistance;
[0144] The gate voltage Vg' of the transistor is determined according to the formula Vg'=Vg+Ig*Rg, where Vg is the third test voltage applied to the gate, Ig is the third test current, and Rg is the third parasitic resistance;
[0145] The substrate voltage Vb' of the transistor is determined according to the formula Vb'=Vb+Ib*Rb, where Vb is the fourth test voltage applied to the substrate, Ib is the fourth test current, and Rb is the fourth parasitic resistance.
[0146] The source terminal voltage, the drain terminal voltage, the gate terminal voltage, and the substrate terminal voltage are used as the terminal voltage information.
[0147] In one exemplary embodiment, the semiconductor structure includes a plurality of said transistors, each transistor sharing a first test pad, a third test pad, and / or a fourth test pad.
[0148] In one exemplary embodiment, the parasitic resistance information determination module 301 is configured to:
[0149] Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line;
[0150] Based on the length information and unit resistance value, determine the parasitic resistance information between the semiconductor device and the test pad.
[0151] In one exemplary embodiment, the parasitic resistance information determination module 301 is configured to:
[0152] Obtain the layout information of the semiconductor structure;
[0153] Extract the pattern information between semiconductor devices and test pads from the layout information;
[0154] Determine the length information based on the pattern information.
[0155] Figure 9 This is a block diagram illustrating a semiconductor structure testing apparatus, namely a computer device 400, according to an exemplary embodiment. For example, the computer device 400 can be provided as a terminal device. (Refer to...) Figure 9 The computer device 400 includes a processor 401, the number of which can be set to one or more as needed. The computer device 400 also includes a memory 402 for storing instructions executable by the processor 401, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 401 is configured to execute instructions to perform the methods described above.
[0156] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.
[0157] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0158] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0159] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0160] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.
[0161] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0162] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.
Claims
1. A method for testing a semiconductor structure, said semiconductor structure being located on a dicing track, comprising a plurality of semiconductor devices and test pads electrically connected to said semiconductor devices, characterized in that, The semiconductor device and the test pads are located on the dicing track. The semiconductor device includes a plurality of transistors. The test pads include: a first test pad electrically connected to the source of each transistor, a second test pad electrically connected to the drain of each transistor, a third test pad electrically connected to the gate of each transistor, and a fourth test pad electrically connected to the substrate corresponding to each transistor. The first test pad, the third test pad, and / or the fourth test pad are shared test pads for all the transistors. A plurality of said semiconductor devices are connected to at least one said common test pad via a connection line, said connection line including a general connection line shared among the plurality of said semiconductor devices; The second test pad is an independent test pad, and a plurality of the independent test pads are arranged sequentially along the arrangement direction of the plurality of semiconductor devices. The common test pad is located between the independent test pads of two adjacent semiconductor devices. The testing method includes: Determine the parasitic resistance information between the semiconductor device and the test pad; the parasitic resistance information includes a first parasitic resistance between the source and the first test pad, a second parasitic resistance between the drain and the second test pad, a third parasitic resistance between the gate and the third test pad, and a fourth parasitic resistance between the bottom of the substrate corresponding to the transistor and the fourth test pad; A first test voltage is applied to the first test pad, a second test voltage is applied to the second test pad, a third test voltage is applied to the third test pad, and a fourth test voltage is applied to the fourth test pad to test the semiconductor structure and obtain the original test results. Based on the parasitic resistance information and the original test results, the target test result is determined.
2. The method for testing semiconductor structures according to claim 1, characterized in that, The testing of the semiconductor structure to obtain the original test results includes: Obtain the test current of the test pad, and use the test voltage and the test current as the original test results.
3. The method for testing semiconductor structures according to claim 2, characterized in that, The determination of the target test result based on the parasitic resistance information and the original test result includes: Based on the test voltage, the test current, and the parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and the test current are used as the target test result.
4. The method for testing semiconductor structures according to claim 3, characterized in that, The step of obtaining the test current of the test pad includes: obtaining the first test current of the first test pad, the second test current of the second test pad, the third test current of the third test pad, and the fourth test current of the fourth test pad, respectively.
5. The method for testing semiconductor structures according to claim 4, characterized in that, Determining the transistor's terminal voltage information based on the test voltage, the test current, and the parasitic resistance information includes: The source terminal voltage Vs' of the transistor is determined according to the formula Vs'=Vs+Is*Rs, where Vs is the first test voltage applied to the source, Is is the first test current, and Rs is the first parasitic resistance; The drain voltage Vd' of the transistor is determined according to the formula Vd'=Vd-Id*Rd, where Vd is the second test voltage applied to the drain, Id is the second test current, and Rd is the second parasitic resistance; The gate voltage Vg' of the transistor is determined according to the formula Vg'=Vg+Ig*Rg, where Vg is the third test voltage applied to the gate, Ig is the third test current, and Rg is the third parasitic resistance; The substrate voltage Vb' of the transistor is determined according to the formula Vb'=Vb+Ib*Rb, where Vb is the fourth test voltage applied to the substrate, Ib is the fourth test current, and Rb is the fourth parasitic resistance. The source terminal voltage, the drain terminal voltage, the gate terminal voltage, and the substrate terminal voltage are used as the terminal voltage information.
6. The method for testing semiconductor structures according to any one of claims 1 to 5, characterized in that, The determination of the parasitic resistance information between the semiconductor device and the test pad includes: Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line; Based on the length information and the unit resistance value, the parasitic resistance information between the semiconductor device and the test pad is determined.
7. The method for testing semiconductor structures according to claim 6, characterized in that, The step of obtaining the length information of the connection line between the semiconductor device and the test pad includes: Obtain the layout information of the semiconductor structure; Extract the pattern information between the semiconductor device and the test pad from the layout information; The length information is determined based on the pattern information.
8. A testing apparatus for a semiconductor structure used to implement the testing method for a semiconductor structure as described in claim 1, wherein the semiconductor structure is located on a dicing track and includes a plurality of semiconductor devices and test pads electrically connected to the semiconductor devices, characterized in that, The semiconductor device and the test pad are located on the dicing track, and the test pad includes: A shared test pad is provided, and several semiconductor devices are connected to at least one of the shared test pads via a connection line, the connection line including a general connection line shared by several semiconductor devices; Independent test pads, a plurality of independent test pads are arranged sequentially along the arrangement direction of a plurality of semiconductor devices, and the common test pad is located between the independent test pads of two adjacent semiconductor devices; The testing apparatus includes: A parasitic resistance information determination module is configured to determine parasitic resistance information between the semiconductor device and the test pad; The raw test result acquisition module is configured to apply a test voltage to the test pad to test the semiconductor structure and obtain raw test results. The target test result determination module is configured to determine the target test result based on the parasitic resistance information and the original test result.
9. The semiconductor structure testing apparatus according to claim 8, characterized in that, The original test result acquisition module is configured to: Obtain the test current of the test pad, and use the test voltage and the test current as the original test results.
10. The semiconductor structure testing apparatus according to claim 9, characterized in that, The target test result determination module is configured to: Based on the test voltage, the test current, and the parasitic resistance information, the terminal voltage information of the semiconductor device is determined, and the terminal voltage information and the test current are used as the target test result.
11. The semiconductor structure testing apparatus according to claim 10, characterized in that, The original test result acquisition module is configured to: The first test current of the first test pad, the second test current of the second test pad, the third test current of the third test pad, and the fourth test current of the fourth test pad are obtained respectively.
12. The semiconductor structure testing apparatus according to claim 11, characterized in that, The target test result determination module is configured to: The source terminal voltage Vs' of the transistor is determined according to the formula Vs'=Vs+Is*Rs, where Vs is the first test voltage applied to the source, Is is the first test current, and Rs is the first parasitic resistance; The drain voltage Vd' of the transistor is determined according to the formula Vd'=Vd-Id*Rd, where Vd is the second test voltage applied to the drain, Id is the second test current, and Rd is the second parasitic resistance; The gate voltage Vg' of the transistor is determined according to the formula Vg'=Vg+Ig*Rg, where Vg is the third test voltage applied to the gate, Ig is the third test current, and Rg is the third parasitic resistance; The substrate voltage Vb' of the transistor is determined according to the formula Vb'=Vb+Ib*Rb, where Vb is the fourth test voltage applied to the substrate, Ib is the fourth test current, and Rb is the fourth parasitic resistance. The source terminal voltage, the drain terminal voltage, the gate terminal voltage, and the substrate terminal voltage are used as the terminal voltage information.
13. The testing apparatus for semiconductor structures according to any one of claims 8 to 12, characterized in that, The parasitic resistance information determination module is configured to: Obtain the length information of the connection line between the semiconductor device and the test pad, as well as the unit resistance value of the connection line; Based on the length information and the unit resistance value, the parasitic resistance information between the semiconductor device and the test pad is determined.
14. The semiconductor structure testing apparatus according to claim 13, characterized in that, The parasitic resistance information determination module is configured to: Obtain the layout information of the semiconductor structure; Extract the pattern information between the semiconductor device and the test pad from the layout information; The length information is determined based on the pattern information.
15. A test apparatus for a semiconductor structure implementing the test method for a semiconductor structure as described in claim 1, characterized in that, The testing equipment includes: processor; Memory used to store processor-executable instructions; The testing equipment further includes several semiconductor devices and test pads electrically connected to the semiconductor devices. The semiconductor devices and the test pads are located on a dicing track. The test pads include: A shared test pad is provided, and several semiconductor devices are connected to at least one of the shared test pads via a connection line, the connection line including a general connection line shared by several semiconductor devices; Independent test pads, a plurality of independent test pads are arranged sequentially along the arrangement direction of a plurality of semiconductor devices, and the common test pad is located between the independent test pads of two adjacent semiconductor devices; The processor is configured to execute: Determine the parasitic resistance information between the semiconductor device and the test pad; A test voltage is applied to the test pad to test the semiconductor structure and obtain the original test results; Based on the parasitic resistance information and the original test results, the target test result is determined.