Storage device and operating method thereof

Abstract

The present invention discloses a memory device and an operating method thereof, wherein the memory device comprises a plurality of memory cell blocks and a plurality of bit lines, each block including a set of word lines and a set of NAND strings. Each of the plurality of memory cell blocks comprises a plurality of sub-blocks, each sub-block including a different subset of a set of NAND strings in a selected block and individual sub-block string select lines. A control circuit is configured to perform a programming operation, which comprises applying a word line voltage and a string select line voltage at a precharge voltage level to precharge a set of NAND strings in the selected block, then lowering the gate voltages of all block string select lines in the block, and then lowering the word line voltages of the set of word lines. The memory cells in the selected sub-block are then programmed.

Description

Technical Field

[0001] The present invention includes a three-dimensional memory device and an operating method thereof, including a programming operation with reduced disturbance of unselected memory cells. Background Art

[0002] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have sought techniques for stacking multiple memory cell planes to achieve greater storage capacity at lower costs per bit.

[0003] However, the high density that allows for high capacity and high throughput may lead to issues with yield and endurance of the memory cells. Therefore, there is a need to provide technologies that can improve yield and endurance while maintaining a high-density memory structure. Summary of the Invention

[0004] This disclosure describes techniques for suppressing unwanted charge trapping in multiple string select gates of a three-dimensional memory device. The techniques can be implemented in a NAND memory device with a block and sub-block architecture, where all NAND strings in a block share a set of word lines, and multiple sub-blocks within the block contain different subsets of NAND strings selected by separate string select lines.

[0005] The present invention describes a memory device comprising a plurality of memory cell blocks and a plurality of bit lines, each memory cell block comprising a set of word lines and a set of NAND strings, each set of NAND strings having a plurality of string select gates for connecting to a plurality of corresponding bit lines among a plurality of bit lines, each NAND string in the set of NAND strings in the memory cell block being connected to the set of word lines. Each memory cell block in the plurality of memory cell blocks has a plurality of sub-blocks, each sub-block comprising a different subset of the set of NAND strings in the memory cell block, and the different subsets of NAND strings in each sub-block being operatively connected to respective sub-block string select lines, and a plurality of gate voltages being applied to the plurality of string select gates of the plurality of NAND strings in the different subsets of NAND strings in the sub-block via the respective sub-block string select lines. A plurality of control circuits are configured to perform a programming operation on the plurality of memory cell blocks. The programming operation comprises:

[0006] Applying a plurality of word line voltages at precharge voltage levels to a group of word lines of a selected memory cell block, applying gate voltages at a first voltage level to all sub-block string select lines in the selected memory cell block to precharge a group of NAND strings in the selected memory cell block, then lowering the gate voltages of all sub-block string select lines in the selected memory cell block, and then lowering the word line voltages of the group of word lines; and

[0007] After lowering the word line voltage of the word line group, a bias sequence is applied to the selected memory cells in the selected sub-block. The bias sequence includes setting the sub-block string selection line to the selected string level or the unselected string level and setting the bit line.

[0008] Embodiments of the technology are applicable to three-dimensional vertical NAND memory.

[0009] Methods of operation are described to suppress unwanted charge trapping as described herein.

[0010] Other aspects and advantages of the present invention will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A perspective view of a three-dimensional semiconductor device is shown;

[0012] Figure 2 Illustration Figure 1 A top view of a portion of the structure;

[0013] Figure 3 shows an alternative arrangement of sub-blocks in a memory cell block;

[0014] Figure 4 is a schematic circuit diagram illustrating a memory cell block in a three-dimensional NAND structure, which can be implemented using a variety of structures, such as those described above;

[0015] Figure 5 The timing diagram of the programming operation on the NAND string is shown. Figure 4 NAND strings in the circuit shown;

[0016] Figure 6 Department is in Figure 5 A heuristic diagram of a NAND string during the precharge phase of a programming operation;

[0017] Figure 7 Department is in Figure 5 The precharge phase of the programming operation ( Figure 6 ) heuristic diagram of the NAND string at the post-processing stage, showing the select gate disturb state;

[0018] Figure 8 The timing diagram of the programming operation on the NAND string is shown. Figure 4 The NAND string in the circuit shown is in a first embodiment of suppressing the select gate disturb state;

[0019] Figure 9 The timing diagram of the programming operation on the NAND string is shown. Figure 4 The NAND string in the circuit shown is in a second embodiment of suppressing the select gate disturb state;

[0020] Figure 10 Department is in Figure 5 The precharge phase of the programming operation ( Figure 6 ) shows a suppressed select gate disturb state;

[0021] Figure 11 is a flow chart of a programming operation for a NAND string with a suppressed select gate disturb state; and

[0022] Figure 12 A simplified block diagram of an integrated circuit memory device including a three-dimensional vertical NAND array and control circuitry for performing a program operation with a suppressed select gate disturb state is shown.

[0023]

Explanation of symbols

[0024] 10: substrate

[0025] 11: Word line layer

[0026] 12: Serial select line

[0027] 13: Lower selection line

[0028] 15, 17: Column

[0029] 18: Common source conductor

[0030] 20: Bit line conductor

[0031] 21, 22: Overlay

[0032] 24: Word line conductor

[0033] 301, 302, 303, 304, 802, 803, 804, 902, 903, 904: Time

[0034] 311, 520, 811, 812, 813, 820, 911, 912, 913, 920: line segments

[0035] 312-1 to 312-5: Serial selection lines

[0036] 315: column

[0037] 320: Bit line conductor

[0038] 401: Dashed Line

[0039] 402: Serial select gate

[0040] 403: bit line

[0041] 601: Common source line

[0042] 602, 702: bit lines

[0043] 605: Ontology

[0044] 610: Lower select gate

[0045] 611: Serial select gate

[0046] 701: Common source line

[0047] 705: Ontology

[0048] 710: Lower select gate

[0049] 711: Serial select gate

[0050] 715: Symbols

[0051] 1001: Common source line

[0052] 1005: Ontology

[0053] 1011: Serial select gate

[0054] 1100, 1101, 1102, 1103, 1104, 1105, 1106: Steps

[0055] 1202: Host

[0056] 1208: Storage device

[0057] 1214, 1216, 1244: Link

[0058] 1218: Input / Output Circuit

[0059] 1226: Bus system

[0060] 1228: Cache circuit

[0061] 1234: Control circuit

[0062] 1238: Page buffer circuit

[0063] 1245, 1246, 1265: Arrows

[0064] 1248: Bit line driver circuit

[0065] 1264: Block

[0066] 1266: bit line

[0067] 1276A: Word Line Decoder

[0068] 1276B: Word line driver circuit

[0069] 1277: Word Line

[0070] 1278: Memory Array

[0071] 1278A: SSL / GSL decoder

[0072] 1278B: SSL / GSL driver circuit

[0073] 1279: SSL and GLS lines

[0074] BL: bit line voltage

[0075] BL0, BL1, BLn: bit lines

[0076] CSL: Common Source Line Voltage

[0077] DWLG: Lower dummy word line

[0078] DWLS: Upper dummy word line

[0079] GSL: Lower select gate

[0080] SEL WL: Selected word line voltage

[0081] SSL, SSL[3:0], SSL0, SSL1, SSLn: Serial select lines

[0082] T0, T1, T2: Time period

[0083] VBL_QPW: voltage

[0084] VCSL PGM: Programming precharge voltage level

[0085] VDDI: voltage

[0086] VDS: drain-source voltage

[0087] VPGM: Programming voltage level

[0088] VSS: voltage

[0089] VSSL: voltage

[0090] VSSL_pre: pre-charge voltage

[0091] VWL_pre: pre-charge voltage

[0092] WL, WLn+k, WLn, WLn-1, WLn-2, ​​WLn-3, WL0: word line DETAILED DESCRIPTION

[0093] Will refer to Figures 1 to 12 A detailed description of various embodiments of the present invention is provided.

[0094] Figure 1 A perspective view of a three-dimensional memory device is shown, comprising multiple blocks and sub-blocks of memory cells arranged in vertical NAND strings. The device comprises a multi-layer stack of wordline layers 11 and a plurality of pillars (e.g., 15 and 17) positioned perpendicular to the substrate. The multi-layer stack of wordline layers 11 is arranged as a first wordline layer 21 and a second wordline layer 22, both of which are parallel to substrate 10. The pillars are arranged along rows and columns. Each pillar comprises a plurality of semiconductor bodies that provide channels for a plurality of series-connected memory cells located at the intersections of the pillars and the wordlines. The wordlines 11 are arranged in a stair-step pattern adjacent to the pillar blocks. Each level includes a contact structure connected to an overlying wordline conductor 24, which is connected to wordline driver circuitry. A plurality of string select lines (SSLs) 12 are positioned parallel to the substrate and above the wordline layer 11. In this example, first and second blocks of memory cells are formed in first and second stacks 21 and 22, respectively. Each string select line intersects a respective different subset of a set of columns (e.g., rows) in the corresponding block, wherein each sub-block of memory cells in the corresponding block is formed in a different subset of columns coupled to a respective string select line.

[0095] The structure also includes a plurality of parallel bitline conductors 20 in a layer parallel to the substrate and above the string select lines. Each bitline conductor is stacked in a separate row of pillars in an array of multiple rows and columns of pillars, with each row containing one pillar from each set of pillars for each string select line.

[0096] Each intersection of a pillar and a string select line defines a select gate of the pillar, which is used to connect to a corresponding bit line. Each pillar is located below and is coupled to one of the bit line conductors through the pillar's select gate.

[0097] A lower select line (lower SG) 13 is formed below the wordline layer 11 to couple the pillars to one or more source lines, such as a common source conductor 18. The common source conductor may be connected to a bias circuit via a vertical connection between blocks or other means.

[0098] Figure 1 The structure of is an example of a memory comprising a plurality of memory cell blocks and a plurality of bit lines, each block comprising a set of word lines (i.e. Figure 1 The invention also provides a memory device comprising a plurality of memory cell blocks (a stack in a block) and a set of NAND strings having string select gates connected to corresponding bit lines of a plurality of bit lines, wherein each NAND string in the set of NAND strings in the block is connected to the set of word lines. Furthermore, in this memory example, each block in the plurality of memory cell blocks has a plurality of subblocks, each subblock including a different subset of the set of NAND strings in the block. Furthermore, in this example, different subsets of NAND strings in each subblock are operatively connected to respective subblock string select lines, with gate voltages applied to the string select gates of the NAND strings in different subsets of the subblock.

[0099] Figure 2 Illustration Figure 1 A top view of an embodiment of a memory cell block in a structure of Figure 1 and Figure 2 It can be seen that the stacks 21 and 22 of the wordline layer 11 intersect at some of the pillars in the overall structure. Thus, to read data from a specific block of memory, the control circuit activates the word line in the stack 21 to select the memory cell block and the specific layer of the stack, and further activates the sub-block string select line 12 to select the specific sub-block. The lower select gate (not shown) is also activated. The memory cells of the selected word line in a set of NAND strings of the selected sub-block can then be read in parallel to the page buffer (not shown) via the bitline conductor 20. (As used herein, "activate" means to apply a specific bias voltage to affect the connected memory cells or switches. The bias voltage may be high or low, depending on the operation or memory design.)

[0100] Figure 3 A top view of an alternative configuration of a set of NAND strings of a sub-block is shown, wherein string select lines 312-1 through 312-5 are coupled to respective different subsets of pillars (eg, 315) arranged in offset rows such that each distinct subset of pillars includes two row pillars. Figure 3 Each point in represents the lateral position of a corresponding pillar 315. Five string select lines 312-1 to 312-5 and eight bit line conductors 320 are shown.

[0101] as Figure 2 structure, Figure 3Each string select line 312 in the array intersects a different subset of pillars 315, with the intersections defining the string select gates. Similarly, each bit line conductor 320 overlies the pillars 315 in a respective row, with each pillar 315 located beneath one of the bit line conductors 320. However, in Figure 3 In this structure, when pillars are formed to be positioned orthogonal to columns of bit lines, the pillars in each such column intersect all other bit lines, and alternate columns are offset to intersect alternate sets of bit lines. Using this configuration, the number of pillars and the density of bit line conductors 320 in a sub-block can be increased, enabling memory operation with higher capacity and increased throughput.

[0102] Figure 4 The diagram shows a block of memory cells in a three-dimensional NAND device. The three-dimensional NAND device may include many blocks, and one of the blocks may include multiple sub-blocks. In the diagram, a plurality of bit lines BL0 to BLn are arranged in rows and columns above an array formed by NAND strings. Each NAND string includes a series of memory cells, such as dielectric charge trapping memory cells, between corresponding bit lines and a reference line, such as a common source line ( Figure 4 In some embodiments, the common source line for the blocks may be implemented as one or more reference lines and may be coupled to a bias circuit that applies an operating voltage other than ground during many operations of the memory.

[0103] In a three-dimensional NAND configuration, for example, Figure 4 The set of NAND strings in the block shown corresponds to Figures 1 to 3 In this example, the NAND strings in the plurality of NAND strings are coupled to corresponding stacks of word lines WL0 to WLn+k. At word line WLn, the planar structure of each word line layer is represented by dashed line 401. Thus, all memory cells in a block of word line layers at a height corresponding to a given word line, such as WLn, are coupled to that given word line.

[0104] Furthermore, each NAND string includes a corresponding sub-block string select gate (e.g., 402) configured to connect the NAND string to a specific bit line (e.g., 403) among a plurality of bit lines. The select gate may be implemented by a transistor including a charge-trapping dielectric layer, such as a gate dielectric. The charge-trapping dielectric layer may be similar to the charge-trapping structure used in the memory cells of the NAND string. Due to the electric field generated during memory operation, the charge-trapping dielectric layer of the string select gate may trap charge, resulting in an undesirable increase in the threshold voltage of the string select gate.

[0105] A plurality of sub-block string select lines SSL0 to SSLn are operatively coupled to respective groups of NAND strings comprising a sub-block of the memory cell block so that gate voltages are applied to the sub-block string select gates.

[0106] Furthermore, each NAND string includes a corresponding lower select gate configured to connect the NAND string to a common source line or one of one or more reference lines used to implement the common source line. In this example, the lower select gate layer GSL is coupled to all lower select gates for the NAND strings in the block. In another example, multiple lower select gate lines can be configured to connect the lower select gates in the block.

[0107] In this example, a lower dummy word line DWLG is located between the lower select gate layer GSL and the lowermost word line layer WL0 , and an upper dummy word line DWLS is located between the string select lines SSL0 to SSLn and the uppermost word line layer WLn+k.

[0108] exist Figure 4 In the circuit, a subblock and wordline layer are selected to select a specific memory cell in the block. A subblock is selected via a subblock string select line, which connects each NAND string in the selected subblock to a respective bitline of a plurality of bitlines. The wordline layer is selected so that the memory cell located at the height of the selected wordline and on each NAND string in the selected subblock is selected. The selected memory cell is selected by selecting the bitline corresponding to the NAND string in which the selected memory cell is located. This configuration enables multiple memory cells, one in each NAND string in the selected subblock, to be activated in parallel via their corresponding bitlines and wordline layers.

[0109] Figure 5 The timing diagram of the bias voltage used for programming operation is shown in FIG. Figure 4 The timing diagram shows the bit line voltage BL, the common source line voltage CSL, the selected word line voltage SEL WL, and the voltages applied to the four sub-block string select lines SSL[3:0] (assuming four sub-blocks). The programming operation can be characterized as including a precharge phase and a programming phase.

[0110] The precharge phase begins at time 301, where the voltage is grounded in this example. After time 301, the common source line voltage increases to the programming precharge voltage level VCSL PGM, the selected word line voltage increases in two stages to the word line precharge voltage level VWL_pre, and all string select lines for the block increase in two stages to the string select line precharge voltage level VSS_pre. These voltage shifts turn on the string select lines and word lines of the NAND strings in the block, and the block's bit lines are then charged in two stages to the precharge voltage VDDI. After period T0, at time 302, the word line voltage decreases to VSS during period T1. At the end of period T1, at time 303, the string select lines for the unselected sub-blocks decrease to VSS, while the string select lines for the selected sub-block remain at the precharge voltage level VSSL_pre. Therefore, in period T2 , after the voltage level of the word line drops to VSS, the voltage of the unselected string selection lines decreases, as indicated by line segment 311 .

[0111] Next, starting at time 304, the bit lines are set to program or inhibit voltage levels according to the data pattern to be programmed into the sub-block. In this example, the bit lines receiving the programming bias are set to VSS, and the bit lines to be biased to inhibit programming are set to VDDI or another inhibit voltage.

[0112] During period T2, the semiconductor bodies in the vertical NAND strings of the columns in the unselected sub-blocks are precharged and maintained at the precharge voltage level by turning off the string select gates for these sub-blocks. For the selected sub-block, the string select gates remain open while the bit line bias is adjusted according to the aforementioned data pattern.

[0113] At the beginning of the programming phase, as indicated by line segment 520, the string select line for the selected sub-block is lowered from the precharge voltage level to the starting voltage level that will be used for the selected sub-block during the programming phase. The string select lines for the unselected sub-blocks are set to VSS or another voltage level to turn off the string select gates. Then, in this example, the selected word line voltage is stepwise increased to the programming voltage level VPGM. The string select gates are controlled to the programming level, and the bit line voltage for the uninhibited column can be controlled in accordance with the word line voltage to achieve the programming operation. For example, in a quick pass program operation, the bit line voltage can be increased to the VBL_QPW level.

[0114] Figure 6The figure shows an exemplary state of the NAND strings in the unselected sub-block near the end of the period T0. In this figure, the NAND strings are shown horizontally, but can be displayed in a similar manner. Figure 4 In the embodiment shown in FIG. , a vertical NAND string is represented. At this point in time, the lower select gate 610 (i.e., the global source line (GSL)) may have a gate voltage of 0V, disconnecting the common source line 601 from the NAND string pillar. The string select gate 611 has a gate voltage VSSL_pre that maintains it in an on state, connecting the pillar to the bit line 602. Because the word line and string select gate are turned on, the semiconductor body of the memory cell in body 605 is precharged to a level close to the bit line voltage (2.3V in this example).

[0115] Figure 7 The figure shows the end of period T1. Figure 6 The state of the NAND string after the word line voltage drops and before the string select voltage drops. At this point in time, the lower select gate 710 (i.e., the global source line (GSL)) continues to have a gate voltage of 0V, the bit line 702 voltage remains at 2.3V, the common source line 701 is disconnected, and the string select gate 711 continues to have a relatively high gate voltage, VSSL_pre. However, in this example, as the word line voltage drops from the precharge voltage, VWL_pre, to 0V, the voltage in the body 705 also capacitively couples downward. Because of this lower voltage, a drain-to-source voltage, VDS, of approximately 1.3V (for example), is established across the string select gate 711. Because the gate voltage remains relatively high, VDS accelerates electrons through the channel of the string select gate, allowing hot electrons to be injected into the gate dielectric of the string select gate 711 (as indicated by symbol 715). As mentioned above, unwanted charge can be trapped by the gate dielectric, which may have a charge-trapping gate dielectric layer, implemented similarly to a memory cell. This unwanted charge can increase the threshold voltage of the string select gate and, in extreme cases, render the corresponding NAND string inoperable.

[0116] Figure 8 Similar Figure 5 The timing diagram is shown in Figure 4 A programming operation is shown in a block of memory cells that has been conditioned to suppress charge trapping in the string select gates. Figure 8 Similar to Figure 5 However, the voltages in time periods T0, T1, and T2 are different.

[0117] At the end of time period T0, at time 802, the word line voltage of the selected word line is maintained at a precharge voltage level, VWL_pre, and the voltage of the string select line is maintained at a precharge voltage level, VSSL_pre. VWL_pre in this example may be approximately 4V, while VSSL_pre in this example may be approximately 6V, or sufficiently high to support the desired precharge voltage level to prevent program disturb of unprogrammed, unselected sub-blocks. At time 802, the voltages of the string select lines of the selected block all decrease from the relatively high VSSL_pre level to an intermediate voltage, as indicated by line segment 811. This intermediate voltage may be equal to or close to the voltage, VSSL, that will be applied to the string select lines of the selected sub-block after time 804. When the word line voltage decreases at time 803, the intermediate voltage is a level that prevents hot electron injection into the gate dielectric of the string select gate. At time 803, after time period T1, after the voltage of the string select line has dropped, the word line voltage of the selected word line drops to VSS (line segment 812). Figure 10 As shown, the falling string select line voltage suppresses charge injection into the string select gate. At time 804, the voltage of the string select line for the unselected sub-blocks drops to VSS (line segment 813), while the voltage of the string select line for the selected sub-block remains at VSSL, which should be higher than the Vth of the string select gate and the programming voltage level to be applied to the bit line to be programmed, in order to pass this programming voltage. Then, precharging of the bit lines according to the data pattern and programming phase is performed. At the beginning of the programming phase, the string select line for the selected sub-block drops from the precharge voltage level to the starting voltage level to be used for the selected sub-block during the programming phase, as indicated at 820.

[0118] Figure 8The timing diagram of FIG. 1 illustrates an example of a programming operation, which includes applying a wordline voltage at a precharge voltage level to a set of subcell lines of a selected block, applying a gate voltage having a first voltage level to all sub-block string select lines in the selected block to precharge a set of NAND strings in the selected block, then lowering the gate voltages of all sub-block string select lines in the block, and then lowering the wordline voltages of the wordlines; and, after lowering the wordline voltages of the wordlines, applying a bias sequence to program selected memory cells in the selected sub-block, the bias sequence including setting the sub-block string select lines to a selected string level or an unselected string level and setting the bitlines. In this example, lowering the gate voltages (line segment 811) of all sub-block string select lines in the block includes setting the gate voltages to a level close to the selected string level (e.g., VSSL), as applied during the programming phase. For purposes of this description, a gate voltage is close to a selected string level if the gate voltage is closer to a selected string level than to an unselected string level.

[0119] Figure 9 Similar Figure 8 The timing diagram is shown in Figure 4 An alternative programming operation is shown in a block of memory cells that are conditioned to suppress charge trapping in the string select gates. Figure 9 Similar to Figure 5 However, the voltage in the time period T1 is different from that in the time period T2.

[0120] At the end of period T0, at time 902, the word line voltage of the selected word line is maintained at the precharge voltage level VWL_pre. At time 902, as indicated by line segment 911, the voltage of the string select lines for all sub-blocks of the selected block drops from the relatively high VSSL_pre level to a low level, which may be equal to or close to the voltage VSS applied to the string select lines of the unselected sub-blocks after time 904. At time 903, after period T1, after the voltage of the string select lines has dropped, the word line voltage of the selected word line drops to VSS (line segment 912). As Figure 10 As shown, the relatively low string select line voltage suppresses charge injection into the string select gates. At time 904, the voltage of the string select lines for the unselected sub-blocks remains at VSS, while the voltage of the string select line for the selected sub-block increases to VSSL (line segment 913). Precharging of the bit lines according to the data pattern and programming stage is then performed.

[0121] Figure 9The timing diagram of FIG1 illustrates another example of a programming operation, the programming operation including applying a word line voltage of a precharge voltage level to a set of word lines of a selected block, applying a gate voltage having a first voltage level to all sub-block string select lines in the selected block to precharge a set of NAND strings in the selected block, then lowering the gate voltages of all sub-block string select lines of the block, and then lowering the word line voltages of the set of word lines; and, after lowering the word line voltages of the set of word lines, applying a bias sequence to program selected memory cells in the selected sub-block, the bias sequence including setting the sub-block string select lines to a selected string level or an unselected string level and setting the bit lines. In this example, lowering the gate voltages (911) of all sub-block string select lines of the block includes setting the gate voltages to a level close to the unselected string level (e.g., VSS), as applied during the programming phase. For purposes of this description, a gate voltage is close to an unselected string level if the gate voltage is closer to an unselected string level than to a selected string level.

[0122] Figure 8 and Figure 9 An embodiment of a programming operation is shown, including:

[0123] First period (until T0): precharging the columns of the plurality of columns of the block to a precharge voltage level, including charging the word lines in the stack to the word line precharge voltage level and precharging the string select lines in the stack to the string select line precharge voltage level;

[0124] Second period (line segments 811, 812, 911, 912): discharging the word lines in the stack, including lowering the voltage of the string select lines in the plurality of string select lines before lowering the voltage of the word lines in the stack;

[0125] The third period (after T2): setting the voltage of the selected string selection line for the selected sub-block and setting the voltage of the unselected string selection lines for the unselected sub-blocks;

[0126] A fourth period (before segment 820 or segment 920): setting the voltage of a bit line among the plurality of bit lines according to the data pattern to be programmed into the selected sub-block; and

[0127] The fifth phase (programming phase): applying a programming voltage to program the data pattern into the memory cells of the selected word line in the selected sub-block.

[0128] Figure 10 The NAND strings in the unselected sub-block are shown (similar to Figure 7 shown) in Figure 8 and Figure 9The state in time period T2, after the word line voltage drops and the string select voltage is low, is shown. At this point in time, lower select gate 1010 (i.e., global source line (GSL)) continues to have a gate voltage of 0V, causing common source line 1001 to be disconnected, and string select gate 1011 to have a reduced gate voltage, VSSL or VSS, in these examples. However, in this example, as the word line voltage drops from the precharge voltage VWL_pre to 0V, the voltage in body 1005 also decreases due to capacitive coupling. Because of this lower voltage, a drain-source voltage, VDS, of approximately 1.3V is established across string select gate 1011. Because the gate voltage is low, while VDS accelerates electrons into the channel of the string select gate, hot electrons are not injected into the gate dielectric of string select gate 1011 (as indicated by the "X" on the electronic symbol). As described above, unwanted charge is trapped by the gate dielectric having a charge-trapping gate dielectric layer, which is implemented similarly to a memory cell. This operation can suppress unwanted electron tunneling into the string select gate and improve the performance and endurance of the memory device.

[0129] Figure 11 is a flow chart of a method of operating a memory device as described herein to perform a programming operation. Figure 11 The present invention is a flow chart of a method for operating a NAND memory comprising a plurality of blocks of memory cells arranged in NAND strings as described herein, wherein each block comprises a plurality of subblocks, each subblock comprising a distinct subset of NAND strings.

[0130] In the described embodiment, the method begins by receiving a page program command on an integrated circuit, wherein the command includes an address and a data pattern to be programmed (step 1100). The address identifies a selected block, a selected word line, and a selected sub-block within the block. Circuitry on the integrated circuit loads the data pattern into a page buffer or other storage structure to be used during programming (step 1101). A controller is operated by on-chip circuitry to precharge the selected block to a precharge voltage level by setting the word line voltage, bit line voltage, string select line voltage, and common source line voltage (step 1102), an example of which is described in Figure 8 and Figure 9 After a period of time, the controller reduces the voltage of the string selection line in the block to a medium level or a low level, such as Figure 8 and Figure 9Each is described separately. The controller circuit then discharges the voltage of the word line of the selected block (step 1103). At this point, the NAND strings in the selected block are precharged to prevent interference with the unselected NAND strings during the application of the programming voltage. The controller then sets the voltages of the selected string select line and one or more unselected string select lines to the selected sub-block level (VSSL) and the unselected sub-block level (VSS) (step 1104). Depending on the data pattern, the bit line voltage is set to the programming or inhibiting voltage level (step 1105). Furthermore, the programming voltage is applied to the selected word line (step 1106).

[0131] Figure 11 This is a flow chart describing the logic executed by the controller on the storage device described herein. The logic may be referenced using Figure 12 . It will be understood that although all processes are shown here, many of these steps can be combined, performed in parallel, or performed in a different order without affecting the functionality achieved. In some cases, as the reader will understand, the reconfiguration of steps can achieve the same result only if certain other changes are made. In other cases, as the reader will understand, the reconfiguration of steps can achieve the same result only if certain conditions are met. Furthermore, it will be understood that the processes herein only illustrate and understand the steps that are relevant to the present invention, and it should be understood that many additional steps to achieve other functionality can be performed before, after, or between the steps shown here.

[0132] Figure 12 1 shows a simplified diagram of a memory system including a flash memory device 1208 implemented on an integrated circuit and a host 1202. The flash memory device 1208 includes logic for issuing commands, such as program commands, with the address and data to be programmed. The memory device can be implemented on a single integrated circuit chip, a multi-chip module, or multiple chips configured to suit specific needs.

[0133] In this example, the memory device 1208 includes a memory array 1278 on an integrated circuit substrate. The memory array 1278 includes multiple blocks as described above, each block having multiple sub-blocks. The memory array 1278 may be a NAND flash memory implemented using two-dimensional or three-dimensional array technology.

[0134] In various embodiments, the memory device 1208 may have single-level cells (SLC) or multiple-level cells (eg, MLC, TLC, or XLC) storing more than one bit per memory cell.

[0135] Storage device 1208 includes a memory array 1278, which may be a NAND flash memory implemented using three-dimensional array technology. In some embodiments, memory array 1278 comprises an array of vertical NAND strings arranged in a dense three-dimensional configuration. In other embodiments, memory array 1278 may comprise a two-dimensional array of NAND strings.

[0136] Word line decoder 1276A is coupled to a plurality of word lines 1277 in memory array 1278 via word line driver circuit 1276B. SSL / GSL decoder 1278A is coupled to the bit line-side (SSL) string select gates and the common source-side (GSL) string select gates in the array via SSL / GSL driver circuit 1278B and SSL and GLS lines 1279. Page buffer circuit 1238 is coupled to bit lines 1266 in memory array 1278 via bit line driver circuit 1248. In some embodiments, column decoder circuits may be included to transfer information from the bit line drivers to the selected bit lines. Page buffer circuit 1238 may store a page of data that defines the data pattern used for page programming operations and may include sensing circuitry for read and verify operations.

[0137] The bit lines for the memory array may include global bit lines (GBLs) and local bit lines. Bit lines generally comprise conductors in a higher patterned layer that traverse multiple blocks of memory cells in the array and are connected to local bit lines within a block through block select transistors or bank select transistors. Local bit lines connect to memory cells to allow current to flow into and out of the bit lines, and are then connected to bit line driver circuitry 1248 and page buffer circuitry 1238. Similarly, word lines may include global word lines and local word lines, with corresponding support circuitry in word line driver 1276B.

[0138] During a sensing operation, sensed data from the page buffer circuits 1238 is supplied to the cache circuits 1228 via a second data line in the bus system 1226. The cache circuits 1228 are then coupled to the input / output circuits 1218 via a link 1216 (e.g., a data path line). In this example, input data is also applied to the cache circuits 1228 on the link 1216 and coupled to the page buffer circuits 1238 on the bus system 1226 to support programming operations.

[0139] Input / output circuitry 1218 is connected via link 1214 (including input / output pads) and provides a communication path for data, addresses, and commands to a destination external to memory device 1208, which in this example includes host 1202. Input / output circuitry 1218 provides a communication path to cache circuitry 1228 via link 1216, which supports memory operations. Cache circuitry 1228 and page buffer circuitry 1238 communicate dataflow (e.g., using bus system 1226).

[0140] Control circuitry 1234 is coupled to input / output circuitry 1218 and includes command decoding logic, address counters, state machines, timing circuits, and other logic circuitry for controlling various memory operations, including programming, reading, and erasing operations for memory array 1278. Required control circuit signals to support these circuit operations are distributed to circuits within the memory device, as indicated by arrows 1245 and 1246. Control circuitry 1234 may include address registers and the like for communicating addresses to various components of memory device 1208 as needed, including to cache circuitry 1228 and, as shown, to page buffer circuitry 1238, wordline decoder 1276A, and SSL / GSL decoder 1278A over link 1244.

[0141] exist Figure 12 In the illustrated example, control circuitry 1234 includes control logic circuitry including modules implementing a bias configuration state machine or multiple bias configuration state machines that control the application of bias voltages generated or provided by voltage supplies in block 1264, such as read, erase, verify, and program voltages, including precharge voltages, pass voltages, and other bias voltages supplied to wordline driver circuitry 1276B and bitline driver circuitry 1248 as described herein, for a set of selectable programming and read operations. Bias voltages are applied to various components of memory device 1208 as needed to support the operations, as indicated by arrows 1265. As described in greater detail herein, control circuitry 1234 includes logic for performing bias configurations that reduce hot electron generation in the channels of unselected NAND strings, such as by applying a "pre-turn-on" bias between a program verify pulse and a program pulse during a programming procedure.

[0142] Control circuitry 1234 may include modules implemented using special-purpose logic circuitry, including state machines, such as those known in the art. In alternative embodiments, control circuitry 1234 may include modules implemented using a general-purpose processor, which may be implemented on the same integrated circuit, and which may execute a computer program to control the operation of storage device 1208. In other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be used to implement the modules in control circuitry 1234.

[0143] The memory array 1278 may include floating gate memory cells or dielectric charge trapping memory cells configured to store multiple bits per memory cell by establishing multiple programming levels corresponding to the amount of charge stored and thereby establishing the memory cell threshold voltage Vt. The present invention may be used with single-bit-per-cell flash memory and with other multiple-bit-per-cell and single-bit cell memory technologies. In other examples, the memory cells may include programmable resistance memory cells, phase change memory cells, and other types of nonvolatile and volatile memory cell technologies.

[0144] In the illustrated example, host 1202 is coupled to link 1214 and other unillustrated control terminals on storage device 1208, such as chip select terminals, and the like, and host 1202 can provide commands or instructions to storage device 1208. In some examples, host 1202 can be coupled to the storage device using serial bus technology, using shared address and data lines. Host 1202 can include a general-purpose processor, a special-purpose processor, a processor configured as a memory controller, or other processor that uses storage device 1208. All or part of host 1202 can be implemented on the same integrated circuit as the memory.

[0145] Host 1202 may include a file system or multiple file systems that store, retrieve, and update data stored in memory based on requests from applications. Generally, host 1202 may include programs that perform memory management functions. For example, such functions may include wear leveling, bad block recovery, power loss recovery, garbage collection, error correction, etc. Host 1202 may also include applications, file systems, flash translation layer programs, and other components that can generate status information about data stored in memory, including issuing commands with addresses and information to be programmed to program information.

[0146] So far, the embodiments of the present invention have been described in detail with reference to the accompanying drawings.

[0147] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A storage device comprising: a memory cell block comprising a word line stack and a plurality of pillars orthogonal to the word line stack, wherein the memory cell block comprises a plurality of memory cells located at a plurality of intersections between a plurality of pillars among the plurality of pillars and a plurality of word lines in the word line stack; a plurality of string select lines, each of the string select lines intersecting a respective sub-block of the memory cell block, each of the sub-blocks having a different subset of pillars formed by a plurality of the plurality of pillars, each of a plurality of intersection points between the pillars and the string select lines defining a respective string select gate of the pillar; a plurality of bit lines orthogonal to the plurality of pillars and connected to the series select gate of a pillar in each different subset of the pillars; One or more reference lines coupled to the plurality of pillars, the memory cells of the memory cell block being arranged in a plurality of NAND strings and between the plurality of bit lines and the one or more reference lines, wherein the memory cell block comprises a plurality of memory cell sub-blocks, each of the memory cell sub-blocks comprising a plurality of memory cells located at a plurality of intersections between a plurality of pillars in respective different subsets of the pillars and the word lines in the word line stack; as well as A plurality of control circuits configured to apply a plurality of bias voltages to a plurality of bit lines of the plurality of bit lines, the word lines of the word line stack, and a plurality of string select lines of the plurality of string select lines to perform a programming operation to program a plurality of memory cells located on a selected word line of the word line stack and in a selected memory cell sub-block of the plurality of memory cell sub-blocks, the programming operation comprising: a first period of precharging the columns of the plurality of columns of the memory cell block to a precharge voltage level, comprising charging the word lines in the word line stack to a plurality of word line precharge voltage levels and precharging the string select lines to a plurality of string select line precharge voltage levels; a second period of discharging the word lines in the word line stack, comprising lowering the voltages of the string select lines in the plurality of string select lines before lowering the voltages of the word lines in the word line stack; a third period, setting the voltage of a selected string selection line of a selected memory cell sub-block and setting the voltage of an unselected string selection line of an unselected memory cell sub-block; a fourth period, setting voltages of the bit lines of the plurality of bit lines according to a data pattern to be programmed into the selected sub-block of memory cells; and In a fifth period, a programming voltage is applied to program the data pattern into the memory cells of the selected word line in the selected memory cell sub-block.

2. The storage device according to claim 1 comprises one or more lower select lines, each of the plurality of pillars intersecting a lower select line among the one or more lower select lines, an intersection point of a pillar and a series select line defining a respective select gate of the pillar, the select gate connecting the pillar to the one or more reference lines.

3. The memory device of claim 1, wherein the step of lowering the voltages of the string select lines during the second period comprises setting the voltages of the string select lines to a level close to a selected string level.

4. The memory device of claim 1, wherein the step of lowering the voltage of the string selection lines during the second period comprises setting the gate voltage to a level close to a level of an unselected string. 5 . The memory device of claim 1 , wherein the series select gates in the memory cell block have a plurality of charge trapping dielectric layers. 6 . The memory device of claim 1 , wherein the memory cells in the memory cell block and the string select gates on the NAND strings in the memory cell block have charge trapping dielectric layers.

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