Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method of operating the semiconductor memory device include an array of memory cells, a peripheral circuit, and control logic. The array of memory cells includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are respectively coupled to corresponding source select lines. The program operation includes a plurality of program loops, each program loop including a pass precharge operation. During the pass precharge operation, the control logic controls the peripheral circuit such that: the common source line is floated, and a voltage of a source select line coupled to an unselected memory block among the memory blocks is increased.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0001137, filed on January 5, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. TECHNICAL FIELD

[0003] Various embodiments of the present disclosure generally relate to electronic devices, and more particularly, to a semiconductor memory device and a method of operating the same. BACKGROUND

[0004] Semiconductor memory devices can have a two-dimensional (2D) structure in which strings are arranged horizontally on a semiconductor substrate. Alternatively, memory devices can have a three-dimensional (3D) structure in which strings are arranged vertically over a semiconductor substrate. As memory devices with 2D structures reach their physical scaling limit (i.e., limit of integration density), 3D memory devices including a plurality of memory cells arranged vertically over a semiconductor substrate have been produced. SUMMARY

[0005] Various embodiments of the present disclosure relate to a semiconductor memory device having enhanced programming characteristics, and a method of operating the same.

[0006] One embodiment of the present disclosure relates to a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and control logic. The memory cell array can include a plurality of memory blocks coupled to a common source line. The peripheral circuit can be configured to perform a program operation on a selected memory block selected from among the plurality of memory blocks included in the memory cell array. The control logic can control the program operation of the peripheral circuit. The plurality of memory blocks can be respectively coupled to corresponding source select lines. The program operation can include a plurality of program loops each including a pass precharge operation. During the pass precharge operation, the control logic can control the peripheral circuit such that the common source line is floated and a voltage of a source select line coupled to an unselected memory block among the plurality of memory blocks is increased.

[0007] In one embodiment, the control logic can be configured to, before the common source line is floated, control the peripheral circuit such that a pass voltage is applied to a source select line coupled to the selected memory block and a voltage of the common source line is increased.

[0008] In one embodiment, the control logic can be configured to control the peripheral circuit such that, after the voltage of the source select line coupled to the unselected memory block has increased, an off voltage is applied to the source select line coupled to the selected memory block.

[0009] In one embodiment, the unselected memory block can be coupled to a plurality of source select lines. The control logic can be configured to control the peripheral circuit such that, during the pass precharge operation, a voltage of a source select line disposed adjacent to the common source line among the plurality of source select lines coupled to the unselected memory block is increased.

[0010] In one embodiment, the control logic can be configured to control the peripheral circuit such that, while the voltage of the source select line disposed adjacent to the common source line among the plurality of source select lines coupled to the unselected memory block is increased, a voltage of an additional source select line among the plurality of source select lines coupled to the unselected memory block that is not disposed adjacent to the common source line is maintained.

[0011] One embodiment of the present disclosure relates to a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and control logic. The memory cell array can include a plurality of memory blocks coupled to a common source line. The peripheral circuit can perform a program operation on a selected memory block selected from among the plurality of memory blocks included in the memory cell array. The control logic can control the program operation of the peripheral circuit. The plurality of memory blocks are respectively coupled to corresponding source select lines. The program operation can include a plurality of program loops, each of which includes a pass precharge operation, a program pulse application operation, and a program verify operation. During the pass precharge operation, the control logic can control the peripheral circuit such that: a first voltage is applied to the common source line; the common source line is floated; and the voltage of the common source line is increased from the first voltage to a coupling voltage by increasing a voltage of a source select line coupled to an unselected memory block among the plurality of memory blocks.

[0012] In one embodiment, the control logic can be configured to control the peripheral circuit such that, before the first voltage is applied to the common source line: a turn-on voltage is applied to the source select line coupled to the selected memory block, and a ground voltage is applied to the common source line.

[0013] In one embodiment, the control logic can be configured to control the peripheral circuit such that, after the voltage of the common source line has increased from the first voltage to the coupling voltage: an off voltage is applied to the source select line coupled to the selected memory block.

[0014] In one embodiment, the unselected memory block can be coupled to a first source select line and a second source select line, the first source select line disposed adjacent to the shared source line, the second source select line not disposed adjacent to the shared source line. The control logic can be configured to control the peripheral circuitry such that a voltage of the first source select line coupled to the unselected memory block is increased during the pass pre-charge operation.

[0015] In one embodiment, the control logic can be configured to control the peripheral circuitry such that a voltage of the second source select line coupled to the unselected memory block is maintained while the voltage of the first source select line coupled to the unselected memory block is increased.

[0016] One embodiment of the present disclosure relates to a method of operating a semiconductor memory device that performs a program operation on a selected memory block from among a plurality of memory blocks coupled to a shared source line. The plurality of memory blocks can be respectively coupled to corresponding source select lines. The method can include floating the shared source line and increasing a voltage of a source select line coupled to an unselected memory block among the plurality of memory blocks.

[0017] In one embodiment, the method can further include, prior to floating the shared source line, applying a turn-on voltage to a source select line coupled to the selected memory block and increasing a voltage of the shared source line.

[0018] In one embodiment, the method can further include, after increasing the voltage of the source select line coupled to the unselected memory block, applying a turn-off voltage to the source select line coupled to the selected memory block.

[0019] In one embodiment, the method can further include, after increasing the voltage of the source select line coupled to the unselected memory block, applying a pass voltage to an unselected word line among a plurality of word lines coupled to the selected memory block and applying a program voltage to a selected word line.

[0020] In one embodiment, the method can further include performing a program verify operation on a memory cell coupled to the selected word line.

[0021] In one embodiment, the unselected memory block can be coupled to a plurality of source select lines. Increasing the voltage of the source select line coupled to the unselected memory block among the plurality of memory blocks can include increasing a voltage of a source select line disposed adjacent to the shared source line among the plurality of source select lines coupled to the unselected memory block.

[0022] In one embodiment, increasing the voltage of the source select line coupled to the unselected memory block among the plurality of memory blocks can further include maintaining the voltage of additional source select lines among the plurality of source select lines coupled to the unselected memory block that are not disposed adjacent to the shared source line while increasing the voltage of the source select line disposed adjacent to the shared source line. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0024] Figure 2 is a block diagram illustrating Figure 1 one embodiment of a memory cell array.

[0025] Figure 3 is a circuit diagram illustrating Figure 2 any one of the memory blocks of

[0026] Figure 4 is a circuit diagram illustrating Figure 2 one example of any one of the memory blocks of

[0027] Figure 5 is a circuit diagram illustrating Figure 1 one example of any one of the memory blocks included in the memory cell array of

[0028] Figure 6 is a graph illustrating a plurality of program loops included in a program operation on a semiconductor memory device.

[0029] Figure 7 is a circuit diagram illustrating a program operation performed on a selected memory block.

[0030] Figure 8 is a graph for describing an increase in a channel potential caused by an unselected memory block.

[0031] Figure 9 is a graph for describing an increase in a channel potential caused by a source select line coupled to an unselected memory block in one example of a string structure.

[0032] Figure 10 is a timing diagram for describing one embodiment of a channel pre-charge step shown in Figure 6

[0033] Figure 11 is a timing diagram for describing one embodiment of a program pulse application step shown in Figure 6

[0034] ​​Figure 12 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0035] Figure 13 is a graph for describing an increase in channel potential caused by coupling to a source select line of a memory block that is not selected in one example of a string structure.

[0036] Figure 14 is a graph for describing Figure 6 one embodiment of a channel precharge step shown in

[0037] Figure 15 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0038] Figure 16 is a block diagram of a memory system having Figure 1 a semiconductor memory device.

[0039] Figure 17 is a block diagram illustrating an application of the memory system of Figure 16 .

[0040] Figure 18 is a block diagram illustrating a computing system including the memory system described with reference to Figure 17 . DETAILED DESCRIPTION

[0041] The specific structure and function descriptions in the embodiments of the present disclosure introduced in the present specification or application are exemplified to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms, and should not be interpreted as being limited to the embodiments described in the specification or application.

[0042] Figure 1 is a block diagram of a semiconductor memory device according to one embodiment of the present disclosure.

[0043] Referring to Figure 1 , the semiconductor memory device 100 can include a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, and a voltage generator 150.

[0044] The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz can be coupled to the address decoder 120 through word lines WL. The memory blocks BLK1 to BLKz can be coupled to the read and write circuit 130 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz can include a plurality of memory cells. In one embodiment, the plurality of memory cells can be non-volatile memory cells, and can be implemented as non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be implemented as a memory cell array having a two-dimensional (2D) structure. In one embodiment, the memory cell array 110 can be implemented as a memory cell array having a three-dimensional (3D) structure. Each of the memory cells included in the memory cell array 110 can store at least one bit of data. In one embodiment, each of the memory cells included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In one embodiment, each of the memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In one embodiment, each of the memory cells included in the memory cell array 110 can be a triple-level cell (TLC) storing three bits of data. In one embodiment, each of the memory cells included in the memory cell array 110 can be a quad-level cell (QLC) storing four bits of data. In various embodiments, the memory cell array 110 can include a plurality of memory cells, each of which stores 5 bits or more of data.

[0045] The address decoder 120, the read and write circuit 130, and the voltage generator 150 operate as a peripheral circuit 160 for driving the memory cell array 110. Here, the peripheral circuit 160 operates under the control of the control logic 140. The address decoder 120 is coupled to the memory cell array 110 through the word lines WL. The address decoder 120 can operate under the control of the control logic 140. The address decoder 120 can receive an address through an input / output buffer (not illustrated) provided in the semiconductor memory device 100.

[0046] The address decoder 120 can decode a block address among the received addresses. The address decoder 120 selects at least one memory block based on the decoded block address. When performing a read voltage application operation during a read operation, the address decoder 120 can apply a read voltage Vread generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines. During a program verify operation, the address decoder 120 can apply a verify voltage generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines.

[0047] The address decoder 120 can decode a column address among the received addresses. The address decoder 120 can transfer the decoded column address to the read and write circuit 130.

[0048] The read and program operations of the semiconductor memory device 100 are performed on a page basis. The addresses received in response to a request for a read and program operation can include a block address, a row address, and a column address. The address decoder 120 can select one memory block and one word line in accordance with the block address and the row address. The column address can be decoded by the address decoder 120 and then can be provided to the read and write circuit 130.

[0049] The address decoder 120 can include a block decoder, a row decoder, a column decoder, an address buffer, etc.

[0050] The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during a read operation on the memory cell array 110, and can operate as a "write circuit" during a write operation thereon. The plurality of page buffers PB1 to PBm are coupled to the memory cell array 110 through bit lines BL1 to BLm. During a read or program verify operation, in order to sense a threshold voltage of a memory cell, the page buffers PB1 to PBm can continuously supply a sensing current to a bit line coupled to the memory cell, while each of the page buffers PB1 to PBm senses a change in an amount of a flowing current (depending on a program state of a corresponding memory cell) through a sensing node, and latches it as a sense data. The read and write circuit 130 operates in response to a page buffer control signal output from the control logic 140.

[0051] During a read operation, the read and write circuit 130 can sense data stored in the memory cells, and temporarily store the read data, and then can output the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read and write circuit 130 can include a column selection circuit, etc., and a page buffer (or page register).

[0052] The control logic 140 is coupled to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 can receive the command CMD and the control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 can control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL. Also, the control logic 140 can output a control signal for controlling the pre-charge potential level of the sensing nodes of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read and write circuit 130 to perform a read operation on the memory cell array 110. The control logic 140 can control the voltage generator 150 so that various voltages to be used for a program operation on the memory cell array 110 are generated. Also, the control logic 140 can control the address decoder 120 so that the voltages generated by the voltage generator 150 are transferred to the local lines of the memory block, which is a target of the operation, through the global line. Meanwhile, the control logic 140 can control the read and write circuit 130 so that, during a read operation, the read and write circuit 130 reads data from the selected page of the memory block through the bit lines BL1 to BLm and stores the read data in the page buffers PB1 to PBm. Further, the control logic 140 can control the read and write circuit 130 so that, during a program operation, the read and write circuit 130 programs the data stored in the page buffers PB1 to PBm to the selected page. The control logic 140 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 can be a control logic circuit operating in accordance with an algorithm, and / or a processor executing control logic code.

[0053] The voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass required for a read operation in response to a control signal output from the control logic 140. The voltage generator 150 can include a plurality of pump capacitors for receiving an internal supply voltage to generate a plurality of voltages having various voltage levels, and the voltage generator 150 can generate the plurality of voltages by selectively enabling the plurality of pump capacitors under the control of the control logic 140.

[0054] The address decoder 120, the read and write circuit 130, and the voltage generator 150 can function as a peripheral circuit 160 that performs read, write, and erase operations on the memory cell array 110. The peripheral circuit 160 can perform the read, write, and erase operations on the memory cell array 110 under the control of the control logic 140.

[0055] Figure 2 is a block diagram illustrating Figure 1 one embodiment of the memory cell array 110.

[0056] Referring to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks has a three-dimensional (3D) structure. Each of the memory blocks can include a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged in +X, +Y, and +Z directions. The structure of each of the memory blocks will be described in more detail below with reference to Figure 3 and Figure 4 .

[0057] Figure 3 is a circuit diagram illustrating Figure 2 any one of the memory blocks BLK1 to BLKz, BLKa.

[0058] Referring to Figure 3 , the memory block BLKa can include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a 'U' shape. In the memory block BLKa, m cell strings can be arranged in a row direction (i.e., a positive (+) X direction). In Figure 3 , two cell strings are illustrated as being arranged in a column direction (i.e., a positive (+) Y direction). However, this illustration is made for convenience of description, and it will be understood that three or more cell strings can be arranged in the column direction.

[0059] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pass transistor PT, and at least one drain select transistor DST.

[0060] The select transistors SST and DST and the memory cells MC1 to MCn can have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a pillar for providing the channel layer can be provided in each cell string. In one embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0061] The source select transistors SST of each cell string are coupled between a common source line CSL and the memory cells MC1 to MCp.

[0062] In one embodiment, the source select transistors of the cell strings arranged in the same row are coupled to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are coupled to different source select lines. In Figure 3 In one embodiment, the source select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second source select line SSL2.

[0063] In one embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m can be commonly coupled to one source select line.

[0064] The first memory cell MC1 to the n-th memory cell MCn in each cell string are coupled between the source select transistor SST and the drain select transistor DST.

[0065] The first memory cell MC1 to the n-th memory cell MCn can be divided into the first memory cell MC1 to the p-th memory cell MCp and the (p+1)-th memory cell MCp+1 to the n-th memory cell MCn. The first memory cell MC1 to the p-th memory cell MCp are arranged in a direction opposite to a positive (+) Z direction in order and are coupled in series between the source select transistor SST and the pipe transistor PT. The (p+1)-th memory cell MCp+1 to the n-th memory cell MCn are arranged in the +Z direction in order and are coupled in series between the pipe transistor PT and the drain select transistor DST. The first memory cell MC1 to the p-th memory cell MCp and the (p+1)-th memory cell MCp+1 to the n-th memory cell MCn are coupled to each other through the pipe transistor PT. The gates of the first memory cell MC1 to the n-th memory cell MCn of each cell string are coupled to the first word line WL1 to the n-th word line WLn, respectively.

[0066] The gate of the pipe transistor PT of each cell string is coupled to the pipe line PL.

[0067] The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MCp+1 to MCn. Cell strings arranged in the row direction are coupled to drain select lines extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second drain select line DSL2.

[0068] Cell strings arranged in the column direction can be coupled to bit lines extending in the column direction. In one embodiment, the cell strings CS11 and CS21 in the first column are coupled to a first bit line BL1. The cell strings CS1m and CS2m in the mthcolumn are coupled to an mthbit line BLm. Figure 3

[0069] Memory cells in the cell strings arranged in the row direction, which are coupled to the same word line, form a single page. For example, memory cells in the cell strings CS11 to CS1m in the first row, which are coupled to the first word line WL1, form a single page. Memory cells in the cell strings CS21 to CS2m in the second row, which are coupled to the first word line WL1, form another single page. Cell strings arranged in the direction of a single row can be selected by selecting any one of the drain select lines DSL1 and DSL2. A page can be selected from the selected cell strings by selecting any one of the word lines WL1 to WLn.

[0070] In one embodiment, even and odd bit lines can be provided instead of the first bit line BL1 to the mthbit line BLm. Cell strings arranged in the row direction, which are numbered even, among the cell strings CS11 to CS1m or CS21 to CS2m can be coupled to respective even bit lines. Cell strings arranged in the row direction, which are numbered odd, among the cell strings CS11 to CS1m or CS21 to CS2m can be coupled to respective odd bit lines.

[0071] ​In one embodiment, one or more memory cells of the first memory cell MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells provided increases, the reliability of the operation of the memory block BLKa can improve, while the size of the memory block BLKa can increase. As the number of dummy memory cells provided decreases, the size of the memory block BLKa can decrease, while the reliability of the operation of the memory block BLKa can deteriorate.

[0072] To efficiently control the one or more dummy memory cells, the respective dummy memory cells can have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKa, a program operation can be performed on all or some of the dummy memory cells. When the erase operation is performed after the program operation has been performed, the respective dummy memory cells can have the desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled with the respective dummy memory cells.

[0073] Figure 4 is a circuit diagram illustrating an example of any one of the memory blocks BLK1 to BLKz of Figure 2 .

[0074] Referring to Figure 4 , the memory block BLKb can include a plurality of cell strings CS11’ to CS1m’ and CS21’ to CS2m’. Each of the plurality of cell strings CS11’ to CS1m’ and CS21’ to CS2m’ extends in a positive Z (+Z) direction. Each of the cell strings CS11’ to CS1m’ and CS21’ to CS2m’ can include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not illustrated) below the memory block BLKb.

[0075] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are coupled to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are coupled to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are coupled to the second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be jointly coupled to a single source select line.

[0076] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively coupled to the first word line WL1 to the nth word line WLn.

[0077] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are coupled to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are coupled to the second drain select line DSL2.

[0078] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb has the same Figure 3 The equivalent circuit of the memory block BLKa is similar to the equivalent circuit.

[0079] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Further, the even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be coupled to the even-numbered bit lines, and the odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be coupled to the odd-numbered bit lines.

[0080] In one embodiment, one or more memory cells of the first memory cell MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKb is improved, but the size of the memory block BLKb is increased. As fewer dummy memory cells are provided, the size of the memory block BLKb is decreased, but the reliability of the operation of the memory block BLKb can deteriorate.

[0081] To efficiently control the one or more dummy memory cells, each of the dummy memory cells can have a required threshold voltage. Before or after performing an erase operation on the memory block BLKb, a program operation can be performed on all or some of the dummy memory cells. When the erase operation is performed after the program operation has been performed, the dummy memory cells can have the required threshold voltage by controlling a voltage to be applied to a dummy word line coupled with the respective dummy memory cell.

[0082] Figure 5 is a circuit diagram illustrating one example of a memory block BLKc of any one of the memory blocks BLK1 to BLKz included in the memory cell array 110. Figure 1

[0083] Referring to Figure 5 , the memory block BLKc can include a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm can be respectively coupled to a plurality of bit lines BL1 to BLm. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0084] The select transistors SST and DST and the memory cells MC1 to MCn can have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a pillar for providing the channel layer can be provided in each cell string. In one embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0085] ​A source select transistor SST of each cell string is coupled between a common source line CSL and the memory cells MC1 to MCn.

[0086] The first memory cell MC1 to the n-th memory cell MCn in each cell string is coupled between the source select transistor SST and the drain select transistor DST.

[0087] The drain select transistor DST of each cell string is coupled between a corresponding bit line and the memory cells MC1 to MCn.

[0088] The memory cells coupled to the same word line can constitute a single page. The cell strings CS1 to CSm can be selected by selecting the drain select line DSL. A page can be selected from the selected cell string by selecting any one of the word lines WL1 to WLn.

[0089] In other embodiments, even and odd bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Among the cell strings CS1 to CSm, the even-numbered cell strings can be respectively coupled to even bit lines, and the odd-numbered cell strings can be respectively coupled to odd bit lines.

[0090] As shown in Figure 2 to Figure 4 , the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array having a 3D structure. Further, as shown in Figure 5 , the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array having a 2D structure.

[0091] Figure 6 is a diagram illustrating a plurality of program loops included in a program operation on a semiconductor memory device.

[0092] Referring to Figure 6 , a program operation on a semiconductor memory device can include a plurality of program loops. As shown in Figure 6 , a first program loop (1 st PGM Loop) can be performed. After the first program loop (1 st PGM Loop) has been performed, a second program loop (2 nd PGM Loop) can be performed unless a program operation performed on the memory cells included in the selected page is completed. After the second program loop (2 nd PGM Loop) has been performed, a third program loop (3 rdthe PGM Loop) until a programming operation performed on the memory cells included in the selected page is completed. In this way, the multiple programming loops can be repeated until the programming operation performed on the memory cells included in the selected page is completed or until the current programming loop reaches the maximum programming loop.

[0093] Meanwhile, a programming operation on a semiconductor memory device can be performed using an incremental step pulse programming (ISPP) scheme. The ISPP scheme can be a scheme for programming memory cells with a gradually increasing programming voltage. The programming voltage applied in each programming loop can be gradually increased as the number of programming loops performed is iterated.

[0094] Meanwhile, as shown in Figure 6 each of the multiple programming loops can include a pass pre-charge step, a program pulse application step, and a program verify step. At the pass pre-charge step, a pass voltage of a cell string included in a memory block selected as a target of a programming operation can be pre-charged. In detail, to increase a pass potential level of a cell string including a program-inhibited cell (or a program-inhibited cell), the pass voltage can be pre-charged in advance. Regarding the increase of the pass potential of the cell string including the program-inhibited cell, a detailed description will be made later with reference to Figure 7 .

[0095] At the program pulse application step, a threshold voltage of a program-allowed cell (or a program-allowed cell) can be increased by applying a program voltage to a selected word line. A detailed description of the program pulse application step will be made later with reference to Figure 11 .

[0096] At the program verify step, it can be verified whether the memory cells selected as a programming target have been programmed to a voltage at a desired level (hereinafter referred to as a'reference voltage') or higher. As a result of the verify operation, the memory cells not programmed to the reference voltage or higher can operate as program-allowed cells in a subsequent programming loop. Here, a program pulse having a voltage level higher than that in the previous programming loop can be applied to the program-allowed cells. Meanwhile, the memory cells programmed to the reference voltage or higher can operate as program-inhibited cells in the subsequent programming loop. The threshold voltage of the program-inhibited cells is not increased even though a program pulse is applied to the selected word line.

[0097] Figure 7 is a circuit diagram illustrating a programming operation performed on a selected memory block. In Figure 7 , only some of the multiple cell strings 111 and 112 among the multiple cell strings included in the selected memory block are illustrated. In Figure 7In the example, cell string 111 includes a programmable cell M14, and cell string 112 includes a programmable cell M11. Semiconductor memory device 100 may include multiple memory blocks, and as shown... Figure 7 As shown, the memory block among the plurality of memory blocks that serves as the target of programming operations may include: cell strings 111 and 112, in which a plurality of memory cells for storing data are coupled in series; a drain selection transistor 113 coupled between cell strings 111 and 112 and a bit line; and a source selection transistor 114 coupled between cell strings 111 and 112 and a common source line CSL. Here, the number of cell strings 111 and 112 configured may be the same as the number of bit lines, and therefore the number of drain selection transistors 113 and source selection transistors 114 configured may also be the same as the number of bit lines. Moreover, in order to perform a predetermined operation on the memory cell, a predetermined bias may be applied to the gate of the memory cell through the word line WL, a predetermined bias may be applied to the drain of the drain selection transistor 113 through the bit line BL, and a predetermined bias may be applied to the source of the source selection transistor 114 through the common source line CSL.

[0098] Programming or erasing operations are performed by injecting electrons into or emitting electrons from the floating gate of each memory cell included in a semiconductor memory device according to an embodiment of the present disclosure using Fowler-Nordheim (FN) tunneling, wherein erasing operations are performed on a block-by-block basis and programming operations are performed on selected cells.

[0099] Each selected page in a semiconductor memory device may include multiple memory cells. Among the multiple memory cells included in each selected page, programmable cells may represent memory cells whose threshold voltage has not yet been increased to the target voltage. When a programming voltage is applied to the selected word line, the threshold voltage of the programmable cells may increase. Among the multiple memory cells included in each selected page, programmable cells may represent memory cells whose threshold voltage has been increased to the target voltage. When a programming voltage is applied to the selected word line, the threshold voltage of the programmable cells does not increase.

[0100] exist Figure 7In the example, memory cell M11 is a programmable cell, and memory cell M14 can be a programmable cell. Meanwhile, memory cells M12 and M13 coupled to unselected word lines can be unselected memory cells. To program the programmable cell M11 included in the selected page, a programming voltage of approximately 18V can be applied to the selected word line Selected WL, a pass voltage of approximately 8V can be applied to the unselected word line Unselected WL, a ground voltage VSS can be applied to the selected bit line Selected BL, and a power supply voltage VCC can be applied to the unselected bit line Unselected BL. Here, the power supply voltage VCC can be applied to the drain select line DSL, the ground voltage VSS can be applied to the source select line SSL, and the power supply voltage VCC can be applied to the common source line CSL.

[0101] With this scheme, a programming voltage is applied to the control gate of the programmable cell M14. However, in the cell string 111 including the programmable cell M14, the channel potential can be increased by a voltage ratio caused by the coupling between the programming voltage, the pass voltage, and the precharge voltage from the bit line. Due to the increased channel potential in this manner, programming disturbances can be mitigated or prevented by preventing FN tunneling of the programmable cell M14 in the cell string 111 coupled to the unselected bit line BL. Simultaneously, in the memory cells included in the cell string 112 coupled to the selected bit line BL, a situation occurs where a memory cell to which a pass voltage is applied is programmed; this situation is referred to as a 'pass disturbance'.

[0102] In a semiconductor memory device 100, programming perturbation characteristics can be a significant factor affecting product performance. To mitigate or prevent programming perturbations in the disabled cell M14, the channel potential level of the cell string 111 coupled to the unselected bit line BL should be sufficiently guaranteed. That is, as the channel potential increases, the channel potential of the cell string 111 coupled to the unselected bit line BL should be sufficiently high. For this operation, in situations such as... Figure 6 In the channel precharge step shown, the channel potential can be increased in advance. However, because the capacitance between the common source line CSL and the source select line SSL is large, the channel potential level may not be increased sufficiently. This could worsen programming perturbations, as the channel length increases with the number of memory cells included in the cell string.

[0103] According to one embodiment of this disclosure, the channel voltage of the cell string in the selected memory block can be increased by increasing the voltage of the source select line coupled to the unselected memory block. Accordingly, as the channel potential increases, the channel voltage of the cell string 111 coupled to the unselected bit line Unselected BL can become sufficiently high. As a result, programming disturbances to the disabled cell M14 can be effectively mitigated or prevented during programming operations.

[0104] Figure 8 This is a graph illustrating the increase in channel potential caused by an unselected memory block.

[0105] refer to Figure 8 The diagram depicts a selected memory block BLK 115 and an unselected memory block BLK 117. The selected memory block 115 can be a memory block targeted by a programming operation and can be a memory block containing memory cells to be programmed. The unselected memory block 117 can be a memory block that is not the target of a programming operation. The selected memory block 115 can be coupled to the selected block drain select line Selblk DSL, the selected block word line Selblk WLs, and the unselected block source select line Selblk SSL. The selected memory block 115 can also be coupled to the common source line CSL. Furthermore, the unselected memory block 117 can be coupled to the unselected block drain select line Unselblk DSL, the unselected block word line Unselblk WLs, and the unselected block source select line Unselblk SSL. The unselected memory block 117 can also be coupled to the common source line CSL.

[0106] Both the selected memory block 115 and the unselected memory block 117 can be coupled to a common source line CSL. According to a semiconductor memory device and method of operating the semiconductor memory device according to an embodiment of this disclosure, the voltage of the source select line (i.e., the unselected block source select line UnselblkSSL) coupled to the unselected memory block 117 is increased. In this case, the common source line CSL can be floated. Accordingly, the voltage of the common source line CSL increases due to coupling. Due to the increase in the voltage of the common source line CSL, the channel voltage of the cell string included in the selected memory block 115 can increase. Accordingly, the channel voltage of the cell string including the disabled cells included in the selected memory block 115 can be sufficiently increased. Therefore, when the channel potential increases, the channel voltage of the cell string including the disabled cells can also become sufficiently high. As a result, programming disturbances of the disabled cells M14 can be effectively mitigated or prevented during programming operations. Reference will now be made to... Figure 9 Provide a detailed description.

[0107] Figure 9 This is a graph used to describe, in one example of a string structure, the increase in channel potential caused by the source select line coupled to an unselected memory block.

[0108] refer to Figure 9 On the common source line CSL, selected strings, unselected strings, and unselected memory block strings are formed. Specifically, pillars are formed on the common source line CSL, on which corresponding channels for the selected strings and unselected strings are configured. The selected block source selection line Selblk SSL, the selected block word lines Selblk WL1 to Selblk WL8, and the selected block drain selection line Selblk DSL are formed around the pillars. Further, pillars are formed on the common source line CSL, on which channels for unselected memory block strings are configured. The unselected block source selection lines Unselblk SSL, the unselected block word lines Unselblk WL1 to Unselblk WL8, and the unselected block drain selection line Unselblk DSL are formed around the pillars.

[0109] Figure 9The selected string and unselected string shown can be included in... Figure 8 The selected memory block 115 shown is a string of cells. Although the selected memory block 115 may include multiple selected strings and multiple unselected strings, this is just one example. Figure 9 The image only shows one selected string and one unselected string.

[0110] at the same time, Figure 9 The unselected memory block string shown can be... Figure 8 The unselected memory block 117 shown includes any one of a plurality of cell strings. Although the unselected memory block 117 may include multiple cell strings, this is only one example. Figure 9 The image only shows one string of cells included in the unselected memory block.

[0111] exist Figure 9 In the diagram, the charge trapping layer, the channel layer, and the insulating layer formed between them are omitted. Meanwhile, in Figure 9 The diagram illustrates one embodiment where each unit string is coupled to eight word lines. That is, Figure 9 Each cell string shown may include eight memory cells. However, it can be seen that the embodiments of this disclosure are not limited to this, and cell strings including various numbers of memory cells can be implemented.

[0112] refer to Figure 9As can be seen, the selected string, the unselected string, and the unselected memory block string are coupled to a common source line CSL. Simultaneously, by using the capacitor between the unselected block source select line UnselblkSSL, which is located adjacent to the common source line CSL, and the common source line CSL, the pre-charge voltage level of the common source line CSL can be increased. That is, in the floating state of the common source line CSL, when the voltage of the unselected block source select line UnselblkSSL increases, the voltage of the common source line CSL can also increase. According to one embodiment of this disclosure, the channel voltage of the cell string in the selected memory block can be increased by increasing the voltage of the source select line coupled to the unselected memory block. Accordingly, when the channel potential increases, the channel voltage of the cell string 111 coupled to the unselected bit line Unselected BL can become sufficiently high. As a result, programming disturbances of the disabled cell M14 can be effectively mitigated or prevented during programming operations.

[0113] Figure 10 It is used to describe Figure 6 The timing diagram shows an embodiment of the channel pre-charging step.

[0114] refer to Figure 10 The diagram illustrates the timing of the voltages on the selected block drain select line (Selblk DSL), the selected block source select line (Selblk SSL), the unselected block source select line (Unselblk SSL), and the common source line (CSL) at the channel pre-charge step. Before time t1, the voltages on the selected block drain select line (Selblk DSL), the selected block source select line (Selblk SSL), the unselected block source select line (Unselblk SSL), and the common source line (CSL) can be ground voltage VSS. However, this is merely exemplary, and any voltage can be applied to the selected block drain select line (Selblk DSL), the selected block source select line (Selblk SSL), the unselected block source select line (Unselblk SSL), and the common source line (CSL).

[0115] At time tl, the voltage of the selected block source select line Selblk SSL can be increased from the ground voltage VSS towards the supply voltage VCC. Accordingly, the source select transistors included in the selected memory block Selected BLK can be turned on. Therefore, the voltage of the common source line CSL can be transferred to the channels of the string included in the selected memory block Selected BLK.

[0116] Simultaneously, at time tl, the voltage of the common source line CSL can increase from the ground voltage VSS towards the first voltage V1. The first voltage V1 can be the voltage directly applied to the common source line CSL from the voltage generator 150. After the voltage of the common source line CSL has increased to the first voltage V1, the common source line CSL can be floated. Because the common source line CSL is floated, its voltage can be maintained at the first voltage V1.

[0117] Subsequently, at time t2, the voltage of the unselblk SSL (Unselected Block Source Select Line) can increase from the ground voltage VSS towards the power supply voltage VCC. Correspondingly, due to coupling, the voltage of the common source line CSL can increase from the first voltage V1 to the coupling voltage Vcp. Because of the increased voltage of the common source line CSL, the channel voltage of the string included in the selected memory block Selected BLK can also be further increased.

[0118] Subsequently, at time t3, the voltage of the selected block source select line Selblk SSL decreases from the supply voltage VCC toward the ground voltage VSS. Accordingly, the source select transistors included in the selected memory block Selected BLK can be turned off. Therefore, the channels of the string included in the selected memory block Selected BLK can be electrically isolated from the common source line CSL.

[0119] Subsequently, at time t4, the voltage of the common source line CSL and the voltage of the unselected block source selection line UnselblkSSL can decrease towards the ground voltage VSS. Accordingly, at time t5, the channel precharge step can be terminated.

[0120] like Figure 10 As shown, during the channel precharge step, the voltage of the selected block drain select line Selblk DSL can be maintained at ground voltage VSS. In this case, during the channel precharge step, the channels of the string included in the selected memory block Selected BLK can be isolated from the bit lines.

[0121] Figure 11 It is used to describe Figure 6 The timing diagram shows an embodiment of the programming pulse application step.

[0122] refer to Figure 11At time t6, a programming enable voltage (e.g., ground voltage VSS) can be applied to the selected bit line Selected BL, which is coupled to a selected string containing programmed cells, and a programming disable voltage Vinh can be applied to the unselected bit line Unselected BL, which is coupled to an unselected string containing disabled cells. Here, the programming disable voltage Vinh can be a voltage greater than the programming enable voltage (i.e., ground voltage VSS).

[0123] At time t7, the power supply voltage VCC can be applied to the selected block drain select line Selblk DSL. Correspondingly, the corresponding cell string included in the selected memory block can be electrically coupled to the corresponding bit line. Simultaneously, the ground voltage VSS can be applied to the selected block source select line Selblk SSL.

[0124] At time t8, a voltage Vpass is applied to the selected block word lines Selblk WLs. Simultaneously, at time t9, the voltage of the selected word line Selected WL within the selected block word lines Selblk WLs increases from the voltage Vpass toward the programming voltage VPGM. The voltage of the unselected word line Unselected WL within the selected block word lines Selblk WLs is maintained at the voltage Vpass.

[0125] Accordingly, in the memory cell coupled to the selected word line Selected WL, the programmable cell coupled to the selected bit line Selected BL is programmed, and a programming enable voltage (i.e., ground voltage VSS) is applied to the selected bit line Selected BL. Simultaneously, in the memory cell coupled to the selected word line Selected WL, the channel potential of the cell string coupled to the unselected bit line Unselected BL (to which a programming disable voltage Vinh is applied) is changed from... Figure 10 The voltage increased during the process (i.e., the voltage of "V1+Vcp") is increased to a potential higher than that voltage. Accordingly, the cells that are not programmable are not programmed.

[0126] Subsequently, at time t10, the voltages of the selected block drain select line Selblk DSL, the selected block word line SelblkWLs, and the unselected bit line Unselected BL can be reduced to the ground voltage VSS. Accordingly, at time t10, the programming pulse application step can be terminated.

[0127] at the same time,Figure 6 The detailed timing diagram for the programming verification shown will be omitted here.

[0128] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. In detail, Figure 12 It is a diagram. Figure 6 The flowchart illustrates one embodiment of the channel pre-charging step. It will be referenced together with the following text. Figure 10 and Figure 12 Describe it.

[0129] refer to Figure 12 In step S110, a conduction voltage can be applied to the source select line coupled to the selected memory block. Figure 10 At time t1, the power supply voltage VCC is applied to the selected block source select line Selblk SSL. At step S110, the source select transistors included in the selected memory block are turned on.

[0130] Subsequently, at step S130, the voltage of the common source line can be increased. Figure 10 At time t1, the voltage of the common source line CSL increases from the ground voltage VSS toward the first voltage V1. Accordingly, the channel voltage of the cell string included in the selected memory block can be increased for the first time. In one embodiment, the first voltage V1 can be the power supply voltage VCC.

[0131] Subsequently, in step S150, the common source line CSL can be floated. For example... Figure 10 As shown, the time point when the common source line CSL is floating can be any time point between the time point when the voltage of the common source line CSL increases to the first voltage and the time point t2. At the time point t2, the voltage of the unselected block source selection line Unselblk SSL increases.

[0132] Subsequently, at step S170, the voltage of the source select line coupled to the unselected memory block can be increased. Figure 10 At time t2, the voltage of the unselected block source selection line Unselblk SSL can be increased from the ground voltage VSS towards the power supply voltage VCC. As step S170 is executed, the voltage of the common source line CSL is increased from the first voltage V1 to the coupling voltage Vcp. As a result, the channel voltage of the cell string included in the selected memory block can be increased a second time.

[0133] Subsequently, at step S190, a turn-off voltage can be applied to the source select line coupled to the selected memory block. Figure 10At time t3, the voltage of the selected block's source select line Selblk SSL decreases from the supply voltage VCC toward the ground voltage VSS. Accordingly, the source select transistors included in the selected memory block are turned off. Therefore, the channels of the cell strings included in the selected memory block can be floated.

[0134] With reference Figure 12 The method of operating a semiconductor memory device according to embodiments of the present disclosure describes a method in which, during a channel pre-charge step in a programming operation, the channel voltage of a string comprising a selected memory block can be sufficiently increased. Therefore, at a subsequent programming voltage application step, the channel potential of a cell string including cells that are disabled for programming can be sufficiently increased. As a result, programming disturbances to the disabled cells M14 can be effectively mitigated or prevented during programming operations.

[0135] Figure 13 This is a graph used to describe, in one example of a string structure, the increase in channel potential caused by the source select line coupled to an unselected memory block.

[0136] refer to Figure 13 On the common source line CSL, selected strings, unselected strings, and unselected memory block strings are formed. Specifically, pillars are formed on the common source line CSL, and corresponding channels for the selected strings and unselected strings are configured on these pillars. The selected block lower source select line Selblk SSLd, the selected block upper source select line Selblk SSLu, the selected block word lines Selblk WL1 to Selblk WL8, the selected block lower drain select line Selblk DSLd, and the selected block upper drain select line Selblk DSLu are formed around these pillars. Further, pillars are formed on the common source line CSL, and channels for the unselected memory block strings are configured on these pillars. The unselected block lower source selection line Unselblk SSLd, the unselected block upper source selection line Unselblk SSLu, the unselected block word lines Unselblk WL1 to Unselblk WL8, the unselected block lower drain selection line Unselblk DSLd, and the unselected block upper drain selection line Unselblk DSLu are formed around the pillar. That is, in Figure 13In the cell string structure shown, two source selection lines and two drain selection lines can be coupled to each cell string in the cell string.

[0137] refer to Figure 13 As can be seen, the selected string, the unselected string, and the unselected memory block string are coupled to a common source line CSL. Simultaneously, using the capacitance between the unselected block lower source selection line Unselblk SSLd and the common source line, which are located adjacent to the common source line CSL, in the unselected block lower source selection line Unselblk SSLd and the unselected block upper source selection line Unselblk SSLu, the pre-charge voltage level of the common source line can be increased. That is, in the floating state of the common source line CSL, when the voltage of the unselected block lower source selection line Unselblk SSLd increases, the voltage of the common source line CSL can also increase. According to one embodiment of this disclosure, the channel voltage of the cell string in the selected memory block can be increased by increasing the voltage of the source selection line coupled to the unselected memory block. Accordingly, as the channel potential increases, the channel voltage coupled to the unselected bit line BL of cell string 111 can become sufficiently high. As a result, programming disturbances to the disabled cell M14 can be effectively mitigated or prevented during programming operations.

[0138] Figure 14 It is used to describe Figure 6 The timing diagram shows an embodiment of the channel pre-charging step.

[0139] refer to Figure 14The diagram illustrates the timing of the voltages of the selected lower block drain select line Selblk DSLd, the selected upper block drain select line Selblk DSLu, the selected lower block source select line Selblk SSLd, the selected upper block source select line Selblk SSLu, the unselected lower block source select line Unselblk SSLd, the unselected upper block source select line Unselblk SSLu, and the common source line CSL at the channel pre-charge step. Before time t11, the voltages of the selected lower block drain select line Selblk DSLd, the selected upper block drain select line Selblk DSLu, the selected lower block source select line Selblk SSLd, the selected upper block source select line Selblk SSLu, the unselected lower block source select line Unselblk SSLd, the unselected upper block source select line Unselblk SSLu, and the common source line CSL can be ground voltage VSS.

[0140] At time t11, the voltages of the selected block's lower source select line Selblk SSLd and the selected block's upper source select line Selblk SSLu can be increased from the ground voltage VSS towards the power supply voltage VCC. Accordingly, the source select transistors included in the selected memory block Selected BLK can be turned on. Therefore, the voltage of the common source line CSL can be transferred to the channels of the string included in the selected memory block Selected BLK.

[0141] Simultaneously, at time t11, the voltage of the common source line CSL can increase from the ground voltage VSS towards the first voltage V1. The first voltage V1 can be the voltage directly applied to the common source line CSL from the voltage generator 150. After the voltage of the common source line CSL has increased to the first voltage V1, the common source line CSL can be floated. Because the common source line CSL is floated, its voltage can be maintained at the first voltage V1.

[0142] Subsequently, at time t12, the voltage of the Unselblk SSLd source selection line under the unselected block can increase from the ground voltage VSS towards the power supply voltage VCC. Correspondingly, due to coupling, the voltage of the common source line CSL can increase from the first voltage V1 to the coupling voltage Vcp. Because of the increase in the voltage of the common source line CSL, the channel voltage of the string included in the selected memory block Selected BLK can also be further increased.

[0143] Subsequently, at time t13, the voltages of the selected block's lower source select line Selblk SSLd and the selected block's upper source select line Selblk SSLu decrease from the supply voltage VCC toward the ground voltage VSS. Accordingly, the source select transistors included in the selected memory block Selected BLK can be turned off. Therefore, the channels of the string included in the selected memory block Selected BLK can be electrically isolated from the common source line CSL.

[0144] Subsequently, at time t14, the voltage of the common source line CSL and the voltage of the unselected block-under source selection line Unselblk SSLd can decrease towards the ground voltage VSS. Accordingly, at time t15, the channel precharge step can be terminated.

[0145] like Figure 14 As shown, during the channel precharge step, the voltages of the selected block lower drain select line Selblk DSLd and the selected block upper drain select line Selblk DSLu can be maintained at ground voltage VSS. In this case, during the channel precharge step, the channels of the string included in the selected memory block Selected BLK can be isolated from the bit lines.

[0146] Figure 15 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0147] In detail, Figure 15 It is a diagram. Figure 6 The flowchart illustrates one embodiment of the channel pre-charging step. It will be referenced together with the following text. Figure 14 and Figure 15 Describe it.

[0148] refer to Figure 15 In step S210, a conduction voltage can be applied to the source select line coupled to the selected memory block. Figure 14 At time t11, the power supply voltage VCC can be applied to the lower source select line Selblk SSLd and the upper source select line Selblk SSLu of the selected block. At step S210, the source select transistors included in the selected memory block are turned on.

[0149] Subsequently, at step S230, the voltage of the common source line can be increased. Figure 14 At time t11, the voltage of the common source line CSL increases from the ground voltage VSS toward the first voltage V1. Accordingly, the channel voltage of the cell string included in the selected memory block can be increased for the first time. In one embodiment, the first voltage V1 can be the power supply voltage VCC.

[0150] Subsequently, at step S250, the common source line CSL can be floated. For example... Figure 14 As shown, the time point when the common source line CSL is floating can be any time point between the time point when the voltage of the common source line CSL increases to the first voltage and the time point t12. At the time point t12, the voltage of the unselected block lower source selection line Unselblk SSLd increases.

[0151] Subsequently, at step S270, the voltage of the upper source select line coupled to the unselected memory block can be maintained, and the voltage of the lower source select line can be increased. Figure 14 At time t12, the voltage of the source select line UnselblkSSLu on the unselected block is maintained at ground voltage VSS, and the voltage of the source select line UnselblkSSLd on the unselected block increases from ground voltage VSS toward power supply voltage VCC. As step S270 is executed, the voltage of the common source line CSL can be increased from the first voltage V1 by the coupling voltage Vcp. As a result, the channel voltage of the cell string included in the selected memory block can be increased a second time.

[0152] Subsequently, at step S290, a turn-off voltage can be applied to the source select line coupled to the selected memory block. Figure 10 At time t14, the voltages of the selected block's lower source select line Selblk SSLd and the selected block's upper source select line Selblk SSLu decrease from the supply voltage VCC toward the ground voltage VSS. Accordingly, the source select transistors included in the selected memory block are turned off. Therefore, the channels of the cell strings included in the selected memory block can be floated.

[0153] With reference Figure 15 The method of operating a semiconductor memory device according to an embodiment of this disclosure describes a process in which, during a channel pre-charge step in a selected memory block, the channel voltage of the string included in the memory block can be sufficiently increased. Therefore, at a subsequent programming voltage application step, the channel potential of the cell string including the programmable cells can be sufficiently increased. As a result, programming disturbances to the programmable cells M14 can be effectively mitigated or prevented during programming operations.

[0154] Figure 16 This is a block diagram of a memory system 1000, which has... Figure 1 Semiconductor memory device 100.

[0155] refer to Figure 16The memory system 1000 may include a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 The semiconductor memory device described. Repeated descriptions will be omitted in the following text.

[0156] Memory controller 1100 is coupled to a host computer and semiconductor memory device 100. Memory controller 1100 can access semiconductor memory device 100 in response to requests from the host computer. For example, memory controller 1100 can control read, write, erase, and background operations on semiconductor memory device 100. Memory controller 1100 can provide an interface between semiconductor memory device 100 and host computer. Memory controller 1100 can run firmware for controlling semiconductor memory device 100.

[0157] The memory controller 1100 includes random access memory (RAM) 1110, a processor 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: working memory for the processor 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processor 1120 can control the overall operation of the memory controller 1100. Additionally, during write operations, the memory controller 1100 can temporarily store programming data provided from the host.

[0158] The host interface 1130 includes protocols for performing data exchange between the host and the memory controller 1100. In one embodiment, the memory controller 1100 can communicate with the host via at least one of a variety of interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0159] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0160] Error correction block 1150 can use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. In one example embodiment, the error correction block can be provided as a component of memory controller 1100.

[0161] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, or Micro MMC), an SD card (SD, Mini SD, Micro SD, or SDHC), or Universal Flash Storage (UFS).

[0162] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). An SSD includes a storage device configured to store data in semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of the host coupled to the memory system 1000 can be significantly improved.

[0163] In one embodiment, the memory system 1000 may be provided as one of a variety of elements of an electronic device, such as a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of a variety of electronic devices for forming a home network, one of a variety of electronic devices for forming a computer network, one of a variety of electronic devices for forming a telematics network, a radio frequency identification (RFID) device, or one of a variety of elements for forming a computing system.

[0164] In one embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in types such as: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processed stacked package (WSP).

[0165] Figure 17 It is a diagram. Figure 16 A block diagram of an example application of a memory system.

[0166] refer to Figure 17 The memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include multiple semiconductor memory chips. The semiconductor memory chips are divided into multiple groups.

[0167] exist Figure 17 The diagram illustrates that multiple groups communicate with the memory controller 2200 via channels CH1 to CHk. Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is configured and operated in the same manner.

[0168] Each group can communicate with the memory controller 2200 through a shared channel. The memory controller 2200 may have a reference... Figure 16 The memory controller 1100 described has the same configuration and can control multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0169] Figure 18 This is a block diagram of a computing system 3000, which includes a reference... Figure 17 The memory system described is 2000.

[0170] The computing system 3000 includes a central processing unit (CPU) 3100, RAM 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0171] The memory system 2000 is electrically coupled to the CPU 3100, RAM 3200, user interface 3300, and power supply 3400 via system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 can be stored in the memory system 2000.

[0172] exist Figure 18 In the diagram, semiconductor memory device 2100 is illustrated as being coupled to system bus 3500 via memory controller 2200. However, semiconductor memory device 2100 may be directly coupled to system bus 3500. Here, the functions of memory controller 2200 may be executed by CPU 3100 and RAM 3200.

[0173] exist Figure 18 In the middle, for reference Figure 17 The memory system 2000 described is illustrated and provided. However, the memory system 2000 can be described using references. Figure 16 The memory system 1000 described herein is used instead. In one embodiment, the computing system 3000 may include a reference... Figure 16 and Figure 17 The memory systems 1000 and 2000 are described.

[0174] This disclosure provides a semiconductor memory device with enhanced programming capabilities and a method for operating the semiconductor memory device.

Claims

1. A semiconductor memory device, comprising: A memory cell array comprising multiple memory blocks coupled to a common source line; Peripheral circuitry is configured to perform programming operations on a selected memory block, which is selected from among the plurality of memory blocks included in the memory cell array; as well as The control logic is configured to control the programming operations of the peripheral circuitry. The plurality of memory blocks are respectively coupled to corresponding source select lines. The programming operation includes multiple programming cycles, each programming cycle including a channel precharge operation and a programming pulse application operation. The control logic is configured to control the peripheral circuitry during the channel precharge operation. Make the shared source line float, and While the common source line is floating, the voltage of the source select line coupled to the unselected memory block among the plurality of memory blocks is increased. The control logic is configured to, after performing the channel precharge operation, control the peripheral circuitry to perform the programming pulse application operation to apply a programming voltage to a selected word line among a plurality of word lines included in the selected memory block.

2. The semiconductor memory device of claim 1, wherein the control logic is configured to control the peripheral circuitry prior to the common source line being floated, such that: A conduction voltage is applied to the source select line coupled to the selected memory block, and The voltage of the shared source line increases.

3. The semiconductor memory device of claim 1, wherein the control logic is configured to: control the peripheral circuitry such that a shutdown voltage is applied to the source select line coupled to the selected memory block after the voltage of the source select line coupled to the unselected memory block has been increased.

4. The semiconductor memory device according to claim 1, wherein: The unselected memory block is coupled to multiple source select lines, and The control logic is configured to control the peripheral circuitry during the channel precharge operation to increase the voltage of the source select line among the plurality of source select lines coupled to the unselected memory block and located adjacent to the common source line.

5. The semiconductor memory device of claim 4, wherein the control logic is configured to control the peripheral circuitry such that, while the voltage of the source select line among the plurality of source select lines coupled to the unselected memory block and disposed adjacent to the common source line increases, the voltage of an additional source select line among the plurality of source select lines coupled to the unselected memory block and disposed not adjacent to the common source line is maintained.

6. A semiconductor memory device, comprising: A memory cell array comprising multiple memory blocks coupled to a common source line; Peripheral circuitry is configured to perform programming operations on a selected memory block, which is selected from among the plurality of memory blocks included in the memory cell array; as well as The control logic is configured to control the programming operations of the peripheral circuitry. The plurality of memory blocks are respectively coupled to corresponding source select lines. The programming operation includes multiple programming cycles, each programming cycle including a channel precharge operation, a programming pulse application operation, and a programming verification operation. The control logic is configured to control the peripheral circuitry during the channel precharge operation. A first voltage is applied to the common source line. Make the shared source line float, and While the common source line is floating, the voltage of the common source line is increased by increasing the voltage of the source select line coupled to the unselected memory block among the plurality of memory blocks, thereby increasing the coupling voltage. The control logic is configured to, after performing the channel precharge operation, control the peripheral circuitry to perform the programming pulse application operation to apply a programming voltage to a selected word line among a plurality of word lines included in the selected memory block.

7. The semiconductor memory device of claim 6, wherein the control logic is configured to control the peripheral circuitry such that, prior to the first voltage being applied to the common source line: A conduction voltage is applied to the source select line coupled to the selected memory block, and A ground voltage is applied to the common source line.

8. The semiconductor memory device of claim 6, wherein the control logic is configured to: after the voltage of the common source line has increased from the first voltage by the coupling voltage, control the peripheral circuitry such that a shutdown voltage is applied to the source select line coupled to the selected memory block.

9. The semiconductor memory device according to claim 6, wherein: The unselected memory block is coupled to a first source select line and a second source select line. The first source select line is adjacent to the common source line, and the second source select line is not adjacent to the common source line. The control logic is configured to control the peripheral circuitry during the channel precharge operation to increase the voltage of the first source select line coupled to the unselected memory block.

10. The semiconductor memory device of claim 9, wherein the control logic is configured to control the peripheral circuitry such that: while the voltage of the first source select line coupled to the unselected memory block increases, the voltage of the second source select line coupled to the unselected memory block is maintained.

11. A method of operating a semiconductor memory device, the semiconductor memory device performing a programming operation on a selected memory block, the selected memory block being selected from a plurality of memory blocks coupled to a common source line, the method comprising: Make the shared source line float; While the common source line is floating, the voltage of the source selection line coupled to the unselected memory block among the plurality of memory blocks is increased; as well as After increasing the voltage of the source select line, a programming voltage is applied to the selected word line among the plurality of word lines included in the selected memory block.

12. The method of claim 11, further comprising, before floating the common source line: Apply a conduction voltage to the source select line coupled to the selected memory block; and Increase the voltage of the common source line.

13. The method of claim 11, further comprising, after increasing the voltage on the source select line coupled to the unselected memory block: A shutdown voltage is applied to the source select line coupled to the selected memory block.

14. The method of claim 11, further comprising, after increasing the voltage on the source select line coupled to the unselected memory block: The unselected word lines are subjected to voltage applied to the plurality of word lines coupled to the selected memory block.

15. The method of claim 14, further comprising: A programming verification operation is performed on the memory cell coupled to the selected word line.

16. The method of claim 11, wherein: The unselected memory block is coupled to multiple source select lines, and Increasing the voltage of the source select line coupled to the unselected memory block includes increasing the voltage of the source select line among the plurality of source select lines coupled to the unselected memory block that is adjacent to the common source line.

17. The method of claim 16, wherein increasing the voltage on the source select line coupled to the unselected memory block further comprises: While increasing the voltage of the source select line that is adjacent to the common source line, the voltage of the additional source select line that is not adjacent to the common source line among the plurality of source select lines coupled to the unselected memory block is maintained.

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