Dynamic Random Access Memory and its Programming Method

Abstract

This invention relates to a dynamic random access memory (DRAM) and its programming method, which consists of two stages. In the first stage, the capacitors of the memory cells of the DRAM are broken down to make the DRAM a one-time programmable memory. In the second stage, the resistance of the broken-down capacitors is reduced to make the state data of the memory cells easier to read. Therefore, this invention provides a small-area one-time programmable memory.

Description

Technical Field

[0001] This invention relates to a dynamic random access memory (DRAM), and more particularly to a dynamic random access memory as a one-time programmable (OTP) memory and a method for programming it. Background Technology

[0002] In today's IC industry, OTP memory is an important type of non-volatile memory. OTP memory is often used to store code or firmware that will not be changed. In the memory industry, OTP memory can also be used to record the addresses of failure columns, rows, or bits, so that redundant columns, rows, or bits can be replaced by these failure columns, rows, or bits.

[0003] Traditional OTP memory uses high voltage to burn out its internal electronic fuse. The electronic fuse requires a large area, so traditional OTP memory occupies a large chip area and requires additional manufacturing processes to produce the electronic fuse, thus increasing die cost. Summary of the Invention

[0004] One of the objectives of this invention is to propose a dynamic random access memory as a one-time programmable memory and a method for programming it.

[0005] One of the objectives of this invention is to propose a programmable method for a two-stage dynamic random access memory.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] A dynamic random access memory (DRAM) includes a character line, a bit line, and a memory cell. The memory cell includes a capacitor and a transistor. The capacitor has a first terminal and a second terminal. The transistor is connected between the bit line and the first terminal of the capacitor, and the gate electrode of the transistor is connected to the character line. The programmed method of the present invention includes: in a first stage, turning on the transistor to connect the first terminal of the capacitor to the bit line, and applying a first voltage and a second voltage to the bit line and the second terminal of the capacitor, respectively, to break down the capacitor; in a second stage, turning off the transistor and applying a ground reference voltage and a third voltage to the second terminal and the base of the transistor, respectively, to generate a first current flowing through the capacitor.

[0008] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: the present invention uses dynamic random access memory as a one-time programmable memory, which does not require the use of electronic fuses, and therefore the present invention can provide a small-area one-time programmable memory. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is an embodiment of the first stage of the programmed method for the dynamic random access memory of the present invention;

[0011] Figure 2 This is an embodiment of the second stage of the programmed method for the dynamic random access memory of the present invention;

[0012] Figure 3 This is a circuit diagram of a memory cell;

[0013] Figure 4 This is another embodiment of the second stage of the programmed method for the dynamic random access memory of the present invention.

[0014] Symbol explanation:

[0015] 10...Dynamic Random Access Memory, 12...Memory Cell, 14...Memory Cell, 16...First Terminal, 18...Second Terminal, 20...Substrate, 22...First Doped Region, 24...Second Doped Region, 26...Gate Electrode, BL1...Bit Line, BL2...Bit Line, C1...Capacitor, GND...Ground Reference Voltage, I1...First Current, I2...Second Current, M1...Transistor, PL...Board Line, V1...First Voltage, V2...Second Voltage, V3...Third Voltage, V4...Fourth Voltage, Vc...Voltage, WL1...Character Line, WL2...Character Line. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] The purpose of this invention is to provide a dynamic random access memory and its programming method. By using dynamic random access memory as a one-time programmable memory, it eliminates the need for electronic fuses. Therefore, this invention can provide a small-area one-time programmable memory.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Figure 1 and Figure 2 This invention provides a method for programming the dynamic random access memory 10. The dynamic random access memory 10 includes multiple memory cells 12 and 14, multiple character lines WL1 and WL2, and multiple bit lines BL1 and BL2. The dynamic random access memory can select the memory cells 12 and 14 to be read or programmed using the multiple character lines WL1 and WL2 and the multiple bit lines BL1 and BL2. Figure 3 This is the circuit diagram for memory unit 12. (Example) Figure 1 and Figure 3 As shown, memory cell 12 includes a transistor M1 and a capacitor C1. Transistor M1 is connected between bit line BL and the first terminal 16 of capacitor C1. The voltage on character line WL1 controls whether transistor M1 is turned on or off. The second terminal 18 of capacitor C1 is connected to a plateline PL. Multiple memory cells 12 and 14 of the DRAM share a single plateline PL. Figure 1 The memory cell 12 has a 1T1C architecture, but the present invention is not limited to this. For example, the memory cell 12 can also be a 2T1C architecture. The circuit of the memory cell 14 is the same as that of the memory cell 12, so it will not be described again.

[0020] like Figure 1 and Figure 2 As shown, transistor M1 includes a substrate 20, a first doped region 22, a second doped region 24, and a gate electrode 26. The first doped region 22 and the second doped region 24 are located within the substrate 20 and are respectively connected to bit line BL1 and the first terminal 16 of capacitor C1. The gate electrode 26 is located between the first doped region 22 and the second doped region 24 and is on the substrate 20. The substrate 20 has a first conductivity type, and the first doped region 22 and the second doped region 24 have a second conductivity type. In this embodiment, transistor M1 is an NPN transistor, therefore the first conductivity type is P-type, and the second conductivity type is N-type.

[0021] The programming method for the dynamic random access memory 10 of this invention is divided into two stages, which will be illustrated here using the programmed memory unit 12 as an example. Figure 1 and Figure 3As shown, in the first stage of the programmed operation, a voltage Vc is applied to the character line WL1 to turn on the transistor M1, while a first voltage V1 and a second voltage V2 are applied to the bit line BL1 and the board line PL, respectively. In other words, the first voltage V1 and the second voltage V2 are applied to the first terminal 16 and the second terminal 18 of the capacitor C1, respectively. The voltage difference between the first voltage V1 and the second voltage V2 can cause the capacitor C1 to break down. The voltage difference between the first voltage V1 and the second voltage V2 is approximately 3V to 6V. The first voltage V1 is greater than the ground reference voltage GND of the dynamic random access memory 10, and the second voltage V2 is less than the ground reference voltage GND, where the ground reference voltage GND is the voltage of the ground terminal of the dynamic random access memory 10. In one embodiment, the ground reference voltage is 0V, the first voltage V1 is 2.5V, and the second voltage V2 is -1.5V. Since the capacitor C1 cannot be recovered after breakdown, the dynamic random access memory 10 can be used as an OTP memory. Before capacitor C1 breaks down, it can be considered a high-resistance component; after capacitor C1 breaks down, it can be considered a low-resistance component. Therefore, the data state of memory cell 12 can be determined by monitoring the resistance of capacitor C1. For example, when the resistance of capacitor C1 is greater than a preset value, the data state of memory cell 12 is determined to be "0"; when the resistance of capacitor C1 is less than the preset value, the data state of memory cell 12 is determined to be "1".

[0022] After capacitor C1 is broken down, the lower its resistance, the faster the data status of memory cell 12 can be determined during read operations. Therefore, the programmed method of this invention, after breaking down capacitor C1 in the first stage, performs a second stage to reduce the resistance of capacitor C1. Figure 2 As shown, after the first stage of the programmed operation ends and the second stage of the programmed operation begins, the voltage applied to the character line WL1 is stopped to turn off the transistor M1 and put the bit line BL1 in a floating state. Next, a ground reference voltage GND is applied to the board line PL, and a third voltage V3 is applied to the substrate 20 of the transistor M1, wherein the third voltage V3 is greater than the ground reference voltage GND. The third voltage V3 can be 1V to 3.5V. In this embodiment, the third voltage V3 is 3V. After the ground reference voltage GND and the third voltage V3 are applied to the second terminal 18 (board line PL) of capacitor C1 and the substrate 20 of transistor M1, respectively, a first current I1 is generated flowing through the substrate 20, the second doped region 24, and capacitor C1 to the board line PL. When the first current I1 passes through capacitor C1, the resistance of capacitor C1 can be further reduced.

[0023] Figure 4 This is another embodiment of the second stage of the programmed method of the present invention. For example... Figure 4As shown, after the first stage of the programmed operation ends and the second stage of the programmed operation begins, the voltage applied to the character line WL1 is stopped to turn off the transistor M1. Next, a ground reference voltage GND is applied to the board line PL, a third voltage V3 is applied to the substrate 20 of the transistor M1, and a fourth voltage V4 is applied to the bit line BL1, wherein the third voltage V3 and the fourth voltage V4 are greater than the ground reference voltage GND. The third voltage V3 and the fourth voltage V4 can be from 1V to 3.5V. In this embodiment, the third voltage V3 is 3V and the fourth voltage V4 is 3.5V. After the ground reference voltage GND, the third voltage V3, and the fourth voltage V4 are applied to the second terminal 18 of capacitor C1 (board line PL), the substrate 20 of transistor M1, and the bit line BL1, respectively, a first current I1 is generated flowing through the substrate 20, the second doped region 24, and capacitor C1 to the board line PL, and a second current I2 is generated flowing through the first doped region 22, the substrate 20, the second doped region 24, and capacitor C1 to the board line PL. When the first current I1 and the second current I2 pass through capacitor C1, the resistance of capacitor C1 can be further reduced. Compared to Figure 2 Implementation examples, Figure 3 The embodiment allows a larger current (I1+I2) to pass through capacitor C1, thus speeding up the programming process.

[0024] The above description is merely an embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A dynamic random access memory, characterized by, The dynamic random access memory comprises: a word line; a bit line; a capacitor having a first terminal and a second terminal; and a transistor connected between the bit line and the first terminal of the capacitor; wherein, in a first phase of a programming operation, the transistor is turned on, and a first voltage and a second voltage are applied to the bit line and the second terminal, respectively, to break down the capacitor; wherein, in a second phase of the programming operation, the transistor is turned off, and a ground reference voltage and a third voltage are applied to the second terminal and a base of the transistor, respectively, to generate a first current through the capacitor; wherein the capacitor and the transistor form a memory cell.

2. The dynamic random access memory of claim 1, wherein, The base has a first conductivity type, and the transistor further comprises: a first doped region in the base having a second conductivity type, wherein the first doped region is electrically connected to the bit line; a second doped region in the base having the second conductivity type, wherein the second doped region is electrically connected to the first terminal; and a gate electrode on the base between the first doped region and the second doped region, wherein the gate electrode is electrically connected to the word line.

3. The dynamic random access memory of claim 1, wherein, The first voltage and the third voltage are greater than the ground reference voltage, and the second voltage is less than the ground reference voltage.

4. The dynamic random access memory of claim 1, wherein, The ground reference voltage is 0 V, the first voltage is 2.5 V, the second voltage is -1.5 V, and the third voltage is 1 V to 3.5 V.

5. The dynamic random access memory of claim 1, wherein, The dynamic random access memory further comprises, in the second phase, a fourth voltage applied to the bit line to generate a second current through the capacitor, the fourth voltage being greater than the ground reference voltage.

6. The dynamic random access memory of claim 5, wherein, The fourth voltage is 1 V to 3.5 V.

7. The dynamic random access memory of claim 1, wherein, In the first phase, a voltage difference between the first terminal and the second terminal is 3 V to 6 V.

8. A method of programming a dynamic random access memory, characterized by, The dynamic random access memory comprises a memory cell and a bit line, the memory cell having a capacitor and a transistor connected between a first terminal of the capacitor and the bit line, and the programming method comprises: in a first phase, performing the following steps: turning on the transistor to connect the first terminal of the capacitor to the bit line of the dynamic random access memory; and applying a first voltage and a second voltage to the bit line and a second terminal of the capacitor, respectively, to break down the capacitor; and in a second phase, performing the following steps: turning off the transistor; and applying a ground reference voltage and a third voltage to the second terminal and a base of the transistor, respectively, to generate a first current through the capacitor.

9. The method of programming a dynamic random access memory of claim 8, wherein, The first voltage and the third voltage are greater than the ground reference voltage, and the second voltage is less than the ground reference voltage.

10. The method of programming a dynamic random access memory of claim 8, wherein, The ground reference voltage is 0 V, the first voltage is 2.5 V, the second voltage is -1.5 V, and the third voltage is 1 V to 3.5 V.

11. The method of programming a dynamic random access memory of claim 8, wherein, The programming method of the dynamic random access memory further comprises, in the second phase, applying a fourth voltage to the bit line to generate a second current through the capacitor, the fourth voltage being greater than the ground reference voltage.

12. The method of programming a dynamic random access memory of claim 11, wherein, The fourth voltage is 1 V to 3.5 V.

13. The method of programming of claim 8, wherein, In the first phase, a voltage difference between the first terminal and the second terminal is 3 V to 6 V.

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