A hundred-nanometer gate and its preparation method and application

Abstract

The present invention relates to a 100-nanometer-scale gate electrode and its preparation method and application. The preparation method comprises sputtering a thin layer of conductive metal on a semiconductor epitaxial wafer, then spin-coating a photoresist. After the conductive metal thin layer / photoresist is formed on the semiconductor epitaxial wafer, electron beam exposure is performed according to the exposure area of ​​the required width of the design layout, the cross-section of the photoresist is observed, the width difference between the upper and lower surfaces of the gate groove region cross-section is calculated, and the width difference is subtracted from the required gate width of the design layout to form a new design layout; the photolithography steps are repeated, electron beam exposure is performed according to the exposure area of ​​the new design layout, and then etching is performed to form a gate groove. The photoresist is stripped and the conductive metal thin layer is etched. A gate metal electrode is formed by electron beam lithography, evaporation, and stripping. The present invention adopts a line width compensation design method to make the final gate width as close to the required gate width as possible, thereby improving the accuracy of preparing 100-nanometer-scale gratings using electron beam exposure.

Description

Technical Field

[0001] The present invention relates to the technical field of high-frequency semiconductor device preparation, and in particular to a hundred-nanometer-level gate and a preparation method and application thereof. Background Art

[0002] High electron mobility transistors, represented by AlGaN / GaN and GaAs / AlGaAs heterojunction structures, feature high frequency, high speed, high voltage resistance, and high power, and are widely used in the RF microwave field. As device frequency characteristics continue to improve, the gate length of the device is gradually decreasing. Therefore, in the production of high-frequency devices, in order to achieve higher frequency characteristics, the gate length is generally limited to less than 200nm. However, this exceeds the exposure size limit of traditional optical lithography process equipment, necessitating the use of electron beam lithography to achieve the fabrication of devices with gates in the hundreds of nanometers.

[0003] Currently, the mainstream method for etching gate grooves on the order of hundreds of nanometers is to spin-coat electron beam photoresist onto the epitaxial structure, perform electron beam exposure, develop the gate trench region, and then etch this region to form the gate groove. However, the exposed region formed after exposure and development has an inverted trapezoidal cross-section, with the upper cross-section wider than the lower cross-section, which affects the precision of the resulting gate. Furthermore, during the electron beam lithography process, the electron beam undergoes forward and backscattering on different substrates, causing the electron exposure trajectory to extend into adjacent areas. Substrates with lower atomic numbers have a larger backscattering range, extending as far as 5-10μm, but with relatively weaker intensity. On the other hand, substrates with higher atomic numbers have a smaller backscattering range but significantly higher intensity. Backscattering is the primary factor causing cross-exchange between adjacent exposure regions, resulting in dense pattern adhesion, and severe distortion of large-area patterns. Furthermore, the varying backscattering effects across different substrates further impact the gap between the designed and actual linewidths, making it difficult to achieve high-precision fabrication of semiconductor gates on the order of hundreds of nanometers.

[0004] Therefore, it is of great significance to improve the gate preparation process and enhance the preparation accuracy of the hundred-nanometer gate. Summary of the Invention

[0005] In light of this, it is necessary to address the aforementioned issues by providing a 100-nanometer gate, its preparation method, and its application. By employing a linewidth compensation design to achieve a more precise gate area exposure width and sputtering a thin layer of conductive metal at the bottom of the photoresist, the electron proximity effect and backscattering effect during electron beam lithography are suppressed, significantly improving the lithography and etching accuracy of the 100-nanometer gate. Furthermore, the application of this prepared 100-nanometer gate in high-electron-mobility transistors can impart excellent radio frequency performance to the transistors.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a method for preparing a hundred-nanometer-scale gate, which comprises sputtering a conductive metal thin layer on a semiconductor epitaxial wafer, and then spin-coating a photoresist. After forming a conductive metal thin layer / photoresist structure on the semiconductor epitaxial wafer, electron beam exposure is performed according to an exposure area of ​​the required width of the design layout, the cross-section of the photoresist is observed, the width difference between the upper and lower surfaces of the gate groove area cross-section is calculated, and the required gate width of the design layout is subtracted from the width difference to form a new design layout; the photolithography steps are repeated, electron beam exposure is performed according to the exposure area of ​​the new design layout, and then etching is performed to form a gate groove, the photoresist is stripped off and the conductive metal thin layer is etched, and a gate metal electrode is formed by electron beam lithography, vapor deposition and stripping.

[0008] Furthermore, the method for preparing the hundred-nanometer-scale gate includes the following steps:

[0009] Step 1: After cleaning and drying the semiconductor epitaxial wafer, a thin layer of conductive metal is evaporated;

[0010] Step 2: Spin-coating photoresist on the conductive metal thin layer in step 1 and performing post-baking treatment;

[0011] Step 3: Electron beam exposure is performed on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to the exposure area of ​​the design layout required width, and post-exposure baking is performed;

[0012] Step 4: Develop and fix the film, and expose the gate groove area after drying;

[0013] Step 5: Prepare a sample of the semiconductor epitaxial wafer photoresist cross section, observe its cross-sectional morphology, and calculate the width difference between the upper and lower surfaces of the gate groove region cross section;

[0014] Step 6: Modify the design layout. Subtract the width difference between the upper and lower surfaces in step 5 from the required width of the design layout to form a new design layout.

[0015] Step 7: Repeat steps 1-2, and use the new design layout to perform electron beam exposure on the exposure area of ​​the semiconductor epitaxial wafer with the formed conductive metal thin layer / photoresist structure, and perform post-exposure baking;

[0016] Step 8: Develop and fix the film, and expose the gate groove area after drying;

[0017] Step 9: Use dry etching to etch out the gate groove area in step 8;

[0018] Step 10: After stripping the photoresist, wet etching the conductive metal thin layer;

[0019] Step 11: Form a gate metal electrode by electron beam lithography, evaporation and lift-off.

[0020] Furthermore, before evaporating the conductive metal thin layer in step 1, a passivation layer is first grown on the semiconductor epitaxial wafer.

[0021] Preferably, the passivation layer is SiN, SiO2 or Al2O3, and has a thickness not greater than 500 nm.

[0022] Furthermore, the metal in the conductive metal thin layer in step 1 includes but is not limited to Au, Ti, Cu, Al, Cr, Au-Pd metal or their alloys, and the evaporation method includes but is not limited to sputtering, electroplating and thermal evaporation.

[0023] Furthermore, the thickness of the conductive metal thin layer in step 1 is less than or equal to 10 nm.

[0024] Furthermore, the photoresist includes but is not limited to PMMA, PMMA-MAA, ZEP520, EBR-9, HSQ, and AR-N7520.

[0025] Furthermore, the developer for the development corresponds to the photoresist, including but not limited to MIBK:IPA, xylene:p-dioxane, TMAH, and AR 300-47.

[0026] Furthermore, the observation methods of the cross-sectional morphology in step 5 include but are not limited to SEM, TEM and AFM.

[0027] Furthermore, the dry etching in step 9 is inductively coupled plasma etching.

[0028] Furthermore, the wet etching in step 10 is performed using a corrosive solution for 8 to 10 seconds.

[0029] Preferably, the etching solution is BOE solution.

[0030] In a second aspect, the present invention provides a hundred-nanometer-scale gate, which is prepared using the above-mentioned preparation method.

[0031] In a third aspect, the present invention provides an application of a hundred-nanometer-scale gate in a high electron mobility transistor.

[0032] The beneficial effects of the present invention are:

[0033] (1) The present invention obtains the width difference between the upper and lower surfaces of the gate groove region after preparing a sample of the semiconductor epitaxial wafer photoresist cross section, and adjusts the design layout by adopting a line width compensation design method, so that the final prepared gate width is as close to the required gate width as possible, thereby improving the accuracy of preparing the hundred-nanometer grating by the electron beam exposure method.

[0034] (2) The conductive metal thin layer introduced in the present invention effectively suppresses the electron proximity effect and backscattering effect, thus avoiding the problems of adjacent exposure areas spreading each other, dense pattern adhesion, and severe distortion of large-area patterns. Furthermore, the conductive metal thin layer introduced in the present invention is not affected by the type of semiconductor epitaxial wafer substrate and is universally applicable to all types of semiconductor epitaxial wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the cross section of the photoresist on the semiconductor epitaxial wafer in step 5 of Example 1 of the present invention;

[0036] Figure 2 The SEM characterization morphology image of the semiconductor epitaxial wafer photoresist cross section in step 5 of Example 1 of the present invention is observed;

[0037] Figure 3 This is a SEM characterization morphology image of the gate metal electrode prepared in Example 1 of the present invention;

[0038] Figure 4 This is a small signal characteristic diagram measured by the device prepared in Example 3 of the present invention;

[0039] Figure 5 This is a SEM characterization morphology image of the gate metal electrode prepared in Comparative Example 1 of the present invention.

[0040] In the figure: 1-semiconductor epitaxial wafer; 2-passivation layer; 3-conductive metal thin layer; 4-photoresist; 5-exposure area; DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be further clearly and completely described below in conjunction with the embodiments of the present invention. It should be noted that the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0042] Example 1

[0043] A method for preparing a 140nm gate comprises the following steps:

[0044] Step 1: Clean and dry the GaAs semiconductor epitaxial wafer 1, grow a SiN passivation layer 2 by PECVD, and then evaporate Ti on the SiN passivation layer 2 by magnetron sputtering to form a conductive metal thin layer 3. The thickness of the conductive metal thin layer 3 is 7 nm.

[0045] Step 2: Spin-coat photoresist ZEP520 4 on the conductive metal thin layer in step 1 and perform post-baking treatment;

[0046] Step 3: Electron beam exposure is performed on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to the exposure area 5 with a width of 140 nm, and post-exposure baking is performed;

[0047] Step 4: Develop and fix the film, and expose the gate groove area after drying;

[0048] Step 5: Prepare a sample of the semiconductor epitaxial wafer photoresist cross section, observe its cross-sectional morphology and calculate the width difference between the upper and lower surfaces of the gate groove region cross section; the cross-sectional schematic diagram and SEM characterization morphology of the semiconductor epitaxial wafer photoresist cross section are as follows: Figure 1 and Figure 2 As shown;

[0049] Step 6: Modify the design layout. Subtract the upper and lower surface width difference in step 5 from 140nm to form a new design layout. The exposure area width in the new design layout is 102nm.

[0050] Step 7: Repeat steps 1-2 to perform electron beam exposure on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to the exposure area of ​​102 nm, and perform post-exposure baking;

[0051] Step 8: Develop and fix the film, and expose the gate groove area after drying;

[0052] Step 9: Use dry etching to etch out the gate groove area in step 8; the dry etching is inductively coupled plasma etching (ICP), the etching reaction gas is SF6, the pressure is 5mTorr, the upper RF power is 300W, the lower RF power is 50W, and the etching time is 150s and 80s respectively;

[0053] Step 10: After stripping the photoresist, wet-etching the conductive metal thin layer; the wet etching is performed using a BOE solution for 8 seconds;

[0054] Step 11: Form a gate metal electrode by electron beam lithography, evaporation and lift-off.

[0055] In this embodiment, the gate electrode with a required width of 140 nm is prepared on a GaAs semiconductor epitaxial wafer, and the actual width is 142.3 nm. Figure 3 As shown, the error is only 1.6% and the morphology is good.

[0056] Example 2

[0057] A method for preparing a 100nm gate comprises the following steps:

[0058] Step 1: Clean and dry the semiconductor epitaxial wafer with SiC as the substrate, grow a SiN passivation layer by PECVD, and then evaporate metal Ti on the SiN passivation layer by magnetron sputtering to form a conductive metal thin layer with a thickness of 7 nm;

[0059] Step 2: Spin-coat photoresist ZEP520 on the conductive metal thin layer in step 1 and perform post-baking treatment;

[0060] Step 3: Electron beam exposure is performed on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to an exposure area with a width of 100 nm, and post-exposure baking is performed;

[0061] Step 4: Develop and fix the film, and expose the gate groove area after drying;

[0062] Step 5: Prepare a sample of the semiconductor epitaxial wafer photoresist cross section, observe its cross-sectional morphology, and calculate the width difference between the upper and lower surfaces of the gate groove region cross section;

[0063] Step 6: Modify the design layout. Subtract the upper and lower surface width difference in step 5 from 140nm to form a new design layout. The exposure area width in the new design layout is 76nm.

[0064] Step 7: Repeat steps 1-2 to perform electron beam exposure on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to the exposure area of ​​76 nm, and perform post-exposure baking;

[0065] Step 8: Develop and fix the film, and expose the gate groove area after drying;

[0066] Step 9: Use dry etching to etch out the gate groove area in step 8; the dry etching is inductively coupled plasma etching (ICP), the etching reaction gas is SF6, the pressure is 5mTorr, the upper RF power is 300W, the lower RF power is 50W, and the etching time is 150s and 80s respectively;

[0067] Step 10: After stripping the photoresist, wet-etching the conductive metal thin layer; the wet etching is performed using a BOE solution for 8 seconds;

[0068] Step 11: Form a gate metal electrode by electron beam lithography, evaporation and lift-off.

[0069] In this embodiment, the gate electrode with a required width of 100 nm prepared on the SiC semiconductor epitaxial wafer has an actual width of 101.46 nm, with an error of only 1.46%, and a good morphology.

[0070] Example 3

[0071] A T-gate AlGaN / GaN HEMT device is prepared by the following method:

[0072] Step 1: Grow an AlGaN / GaN HEMT epitaxial wafer on a silicon substrate, then clean and dry it. Use PECVD to grow a SiN passivation layer on the AlGaN / GaN HEMT epitaxial wafer. Then, use magnetron sputtering to evaporate Ti on the SiN passivation layer to form a thin conductive metal layer with a thickness of 6 nm.

[0073] Step 2: Spin-coat photoresist ZEP520 on the conductive metal thin layer in step 1 and perform post-baking treatment;

[0074] Step 3: Electron beam exposure is performed on the AlGaN / GaN HEMT epitaxial wafer with a conductive metal thin layer / photoresist structure according to an exposure area with a width of 100 nm, and post-exposure baking is performed;

[0075] Step 4: Develop and fix the film, and expose the gate groove area after drying;

[0076] Step 5: Prepare a sample of the semiconductor epitaxial wafer photoresist cross section, observe its cross-sectional morphology, and calculate that the width difference between the upper and lower surfaces of the gate groove region cross section is 30 nm;

[0077] Step 6: Modify the design layout. Subtract the 30nm difference in width between the upper and lower surfaces in step 5 from 100nm to form a new design layout. The width of the exposure area in the new design layout is 70nm.

[0078] Step 7: Formal tape-out: Photolithography and etching are performed on the AlGaN / GaN HEMT epitaxial wafer grown on the silicon substrate to mark the points. Align the marked points, perform photolithography, and then use etching to isolate the mesa of the epitaxial wafer. The source and drain metal electrodes are formed by photolithography, evaporation, stripping, and annealing. The source and drain metal electrodes are alloys formed by Ti, Al, Ni, and Au. The annealing atmosphere is N2, the annealing temperature is 850°C, the holding time is 30 seconds, and the heating rate is 15°C / s.

[0079] Step 8: A SiN passivation layer is grown using a PECVD method, and then Ti is evaporated on the SiN passivation layer using a magnetron sputtering method to form a conductive metal thin layer with a thickness of 6 nm; a photoresist ZEP520 is spin-coated on the conductive metal thin layer, and a post-baking hardening process is performed;

[0080] Step 9: Electron beam exposure is performed on the AlGaN / GaN HEMT epitaxial wafer with the formed conductive metal thin layer / photoresist structure according to the exposure area of ​​70nm, and post-exposure baking is performed;

[0081] Step 10: Perform development and fixing treatments, and expose the gate groove area after drying;

[0082] Step 11: using dry etching to etch out the gate groove area in step 8; the dry etching is inductively coupled plasma etching (ICP), the etching reaction gas is SF6, the pressure is 5mTorr, the upper RF power is 300W, the lower RF power is 50W, and the etching time is 150s and 80s respectively;

[0083] Step 12: After stripping the photoresist, wet-etching the conductive metal thin layer; the wet etching is performed using a BOE solution for 10 seconds;

[0084] Step 13: forming a gate cap region and a gate metal electrode by electron beam lithography, evaporation, and lift-off, wherein the gate metal electrode is composed of Ni and Au;

[0085] Step 14: After removing the photoresist on the epitaxial wafer with acetone, photolithography and evaporation are performed to form gate-source-drain metal electrodes, which are composed of Ni and Au.

[0086] The small signal characteristics of the T-gate AlGaN / GaN HEMT in Example 3 were tested, and the test results were as follows: Figure 4 As shown, the device cutoff frequency f T With the highest oscillation frequency f max They are 97GHz and 121GHz respectively, with excellent RF characteristics.

[0087] Comparative Example 1

[0088] A method for preparing a common 100nm gate comprises the following steps:

[0089] Step 1: Clean and dry the semiconductor epitaxial wafer with Si as the substrate, and grow a SiN passivation layer using the PECVD method;

[0090] Step 2: Spin-coat photoresist ZEP520 on the passivation layer of step 1 and perform post-baking treatment;

[0091] Step 3: Electron beam exposure is performed on the semiconductor epitaxial wafer on which the photoresist is spin-coated in Step 2 according to an exposure area with a width of 100 nm, and post-exposure baking is performed;

[0092] Step 4: Develop and fix the film, and expose the gate groove area after drying;

[0093] Step 5: Use dry etching to etch out the gate groove area in step 8; the dry etching is inductively coupled plasma etching (ICP), the etching reaction gas is SF6, the pressure is 5mTorr, the upper RF power is 300W, the lower RF power is 50W, and the etching time is 150s and 80s respectively;

[0094] Step 6: stripping the photoresist with acetone solution;

[0095] Step 7: Form a gate metal electrode by electron beam lithography, evaporation and lift-off.

[0096] In this comparative example, the gate electrode with a required width of 100 nm prepared on the SiC semiconductor epitaxial wafer has an actual width of 155.26 nm. Figure 5 As shown in the figure, the error is as high as 55.26%, the edges of the morphology are not smooth, and the graphics are severely distorted.

[0097] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for preparing a hundred-nanometer gate, characterized in that: Sputtering a thin layer of conductive metal on a semiconductor epitaxial wafer, followed by spin coating of photoresist. After the conductive metal thin layer / photoresist is formed on the semiconductor epitaxial wafer, electron beam exposure is performed according to the exposure area of ​​the required width of the design layout. The cross section of the photoresist is observed, and the width difference between the upper and lower surfaces of the gate groove area cross section is calculated. The required gate width of the design layout is subtracted from the width difference to form a new design layout. Repeat the photolithography steps, perform electron beam exposure according to the exposure area of ​​the new design layout, then etch to form the gate groove, strip the photoresist and etch the conductive metal thin layer, and form the gate metal electrode through electron beam lithography, evaporation and stripping; The specific steps include: Step 1: After cleaning and drying the semiconductor epitaxial wafer, a thin layer of conductive metal is evaporated; Step 2: Spin-coating photoresist on the conductive metal thin layer in step 1 and performing post-baking treatment; Step 3: Electron beam exposure is performed on the semiconductor epitaxial wafer with the conductive metal thin layer / photoresist structure according to the exposure area of ​​the design layout required width, and post-exposure baking is performed; Step 4: Develop and fix the film, and expose the gate groove area after drying; Step 5: Prepare a sample of the semiconductor epitaxial wafer photoresist cross section, observe its cross-sectional morphology, and calculate the width difference between the upper and lower surfaces of the gate groove region cross section; Step 6: Modify the design layout. Subtract the width difference between the upper and lower surfaces in step 5 from the required width of the design layout to form a new design layout. Step 7: Repeat steps 1-2, and use the new design layout to perform electron beam exposure on the exposure area of ​​the semiconductor epitaxial wafer with the formed conductive metal thin layer / photoresist structure, and perform post-exposure baking; Step 8: Develop and fix the film, and expose the gate groove area after drying; Step 9: Use dry etching to etch out the gate groove area in step 8; Step 10: After stripping the photoresist, wet etching the conductive metal thin layer; Step 11: Form a gate metal electrode by electron beam lithography, evaporation and lift-off.

2. The method for preparing a hundred-nanometer gate according to claim 1, characterized in that: Before evaporating the conductive metal thin layer in step 1, a passivation layer is first grown on the semiconductor epitaxial wafer; the passivation layer is SiN, SiO2 or Al2O3, and has a thickness of no more than 500 nm.

3. The method for preparing a hundred-nanometer gate according to claim 1, wherein: The metal in the conductive metal thin layer in step 1 includes Au, Ti, Cu, Al, Cr, Au-Pd metal or their alloys, and the evaporation method includes sputtering, electroplating and thermal evaporation; the thickness of the conductive metal thin layer is less than or equal to 10nm.

4. The method for preparing a hundred-nanometer gate according to claim 1, wherein: The photoresist includes PMMA, PMMA-MAA, ZEP520, EBR-9, HSQ, and AR-N 7520.

5. The method for preparing a hundred-nanometer gate according to claim 1, wherein: The developer for the development corresponds to the photoresist, including MIBK:IPA, xylene:p-dioxane, TMAH, and AR 300-47.

6. The method for preparing a hundred-nanometer gate according to claim 1, wherein: The observation methods of the cross-sectional morphology in step 5 include SEM, TEM and AFM.

7. The method for preparing a hundred-nanometer gate according to claim 1, wherein: The dry etching in step 9 is inductively coupled plasma etching.

8. A hundred-nanometer gate, characterized in that: The method is prepared by any one of claims 1 to 7.

9. Use of the preparation method according to any one of claims 1 to 7 or the hundred-nanometer gate according to claim 8 in a high electron mobility transistor.

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