An apparatus and method of manufacturing an interconnect structure

Abstract

This invention provides an apparatus for manufacturing a semiconductor device. The apparatus may include a chamber, a clamp located within the chamber, and a bias power supply physically connected to the clamp. The apparatus may include a target assembly located above the clamp and the bias power supply, and a magnetron assembly located above the target assembly. The magnetron assembly may include a plurality of external magnetrons and a plurality of internal magnetrons, and the spacing between each adjacent magnetron in the plurality of external magnetrons may be different from the spacing between each adjacent magnetron in the plurality of internal magnetrons.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an apparatus and method for manufacturing interconnect structures. Background Technology

[0002] Back-end of line (BEOL) processes are part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., metallization layers) on a semiconductor wafer. Common metals used in BEOL processes include copper, tantalum, titanium, tungsten, aluminum, and / or combinations thereof. BEOL typically begins when the first metal layer is deposited on the semiconductor wafer. BEOL includes insulating layers (e.g., dielectric layers, passivation layers, etc.), metal layers, bonding sites, etc., for chip-to-package connections. Summary of the Invention

[0003] Embodiments of this disclosure include an apparatus for manufacturing a semiconductor device. The apparatus may include a chamber, a chuck located within the chamber, and a bias power supply physically connected to the chuck. The apparatus may include a target assembly located above the chuck and the bias power supply, and a magnetron assembly located above the target assembly. The magnetron assembly may include a plurality of external magnetrons and a plurality of internal magnetrons, and the spacing between each adjacent magnetron in the plurality of external magnetrons may be different from the spacing between each adjacent magnetron in the plurality of internal magnetrons.

[0004] Embodiments of this disclosure include a method for manufacturing a semiconductor device. The method may include depositing a first insulating layer on top of a metal layer of the semiconductor device, and removing a portion of the first insulating layer to define a via in the first insulating layer. The method may include depositing an aluminum-copper layer on top of the first insulating layer and in the via, wherein the deposition of the aluminum-copper layer may be performed at a temperature in the range of about 300 degrees Celsius to about 400 degrees Celsius and at a magnetic flux in the range of about 200 gauss to about 2000 gauss.

[0005] Embodiments of this disclosure include a semiconductor device. The semiconductor device includes a metal layer and a first insulating layer on top of the metal layer, wherein a plurality of vias are formed in the first insulating layer. The semiconductor device may include an aluminum-copper layer on top of the first insulating layer and within the plurality of vias. The aluminum-copper layer may be provided at a temperature in the range of about 300 degrees Celsius to about 400 degrees Celsius to prevent the formation of voids in the aluminum-copper layer, and the temperature may be generated by a chuck assembly of a tool, the chuck assembly being powered by bias power. The semiconductor device may include a second insulating layer on top of the aluminum-copper layer and a raised chemical layer on top of the second insulating layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this disclosure are best understood in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1E It is one or more of the semiconductor processing tools described in this article located in the figure.

[0008] Figures 2A to 2H It is a diagram of an example semiconductor device and one or more operations involved in the manufacture of an example semiconductor device.

[0009] Figure 3 yes Figure 1A A diagram of one or more device instance components.

[0010] Figure 4 This is a flowchart of an example process for manufacturing an example semiconductor device based on biased aluminum-copper processing technology.

[0011] Explanation of icon numbers

[0012] 1D-1D, 2A-2A: Lines;

[0013] 100: Example;

[0014] 105: Physical vapor deposition chamber;

[0015] 110: Radio frequency bias power supply;

[0016] 115: Clamping plate assembly;

[0017] 120: Cap ring;

[0018] 121: Main body;

[0019] 122: First leg section;

[0020] 123: Second leg section;

[0021] 125: Target assembly;

[0022] 130: Magnetron;

[0023] 135, 160, 165, 170, 175, 180, 240, 245, 255, 265, 270: Reference numbers;

[0024] 140: Upper magnetron;

[0025] 145: Lower magnetron;

[0026] 150: External magnetron;

[0027] 155: Internal magnetron;

[0028] 171: Internal starting point;

[0029] 172: External starting point;

[0030] 200: Semiconductor devices;

[0031] 205: Padding area;

[0032] 210: Rewire via area;

[0033] 215: Intermetallic dielectric layer;

[0034] 220: Padding;

[0035] 225: Aluminum-copper gasket;

[0036] 230: First insulating layer;

[0037] 235: Second insulating layer;

[0038] 250: Through hole;

[0039] 260: Aluminum-copper layer;

[0040] 275: Raised chemical layer;

[0041] 300: Device;

[0042] 310: Bus;

[0043] 320: Processor;

[0044] 330: Memory;

[0045] 340: Storage component;

[0046] 350: Input component;

[0047] 360: Output component;

[0048] 370: Communication interface;

[0049] 400: Process;

[0050] 410, 420, 430: Frames. Detailed Implementation

[0051] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0052] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein shall be interpreted accordingly.

[0053] In some cases, deposition apparatuses may deposit an aluminum-copper layer on a semiconductor device during a BEOL process. In such cases, the physical vapor deposition (PVD) apparatus may not bias the power available for heating the semiconductor device's chuck before the aluminum-copper layer is deposited on the semiconductor device. For example, the semiconductor device includes a metal layer having a first insulating layer (e.g., a first passivation layer) located on top of a metal layer. An opening (e.g., a via) is located in the first insulating layer to expose a portion of the metal layer. The PVD chamber deposits an aluminum-copper layer on the first insulating layer and within the opening located in the first insulating layer. Thus, the aluminum-copper layer is located on top of the exposed portion of the metal layer. A second insulating layer (e.g., a second passivation layer) is located on top of the aluminum-copper layer, and a raised chemical layer is located on top of the second insulating layer. However, because the PVD chamber fails to bias the power available for heating the semiconductor device's chuck before depositing the aluminum-copper layer, voids or pinholes are formed in the aluminum-copper layer deposited within the opening located in the first insulating layer. Such voids prevent the second insulating layer from completely covering the aluminum-copper layer at specific portions. The protruding chemical layer contacts and damages the aluminum-copper layer at specific locations.

[0054] According to some embodiments described herein, a device for manufacturing a semiconductor device (e.g., a PVD chamber) includes a bias power supply for a clamp assembly that prevents voids in the aluminum-copper layer of the semiconductor device and improves the performance of the semiconductor device. In some embodiments, the device for manufacturing a semiconductor device includes a clamp assembly to support the semiconductor device and provide heat to the semiconductor device, and the bias power supply provides bias power to the clamp assembly. The device may include a target assembly to provide an aluminum-copper layer on a metal layer and an insulating layer of the semiconductor device. The insulating layer may be located on the metal layer and include vias, and the aluminum-copper layer on the metal layer may fill the vias included in the insulating layer. The device may include a magnetron to generate a magnetic field that causes the target assembly to provide an aluminum-copper layer on the metal layer and the insulating layer of the semiconductor device. A rotatable magnetron can also generate a magnetic field that causes the target assembly to provide an aluminum-copper layer on the metal layer and the insulating layer of the semiconductor device.

[0055] In this way, the PVD chamber prevents the formation of voids in the aluminum-copper layer of the semiconductor device and improves the performance of the semiconductor device. Without voids in the aluminum-copper layer, the second insulating layer of the semiconductor device can completely cover the aluminum-copper layer. Therefore, the raised chemical layer located on top of the second insulating layer cannot contact the aluminum-copper layer and / or damage it.

[0056] Figures 1A to 1E This is a diagram of one or more embodiments 100 of the semiconductor processing apparatus described herein. (See diagram for example.) Figure 1A As illustrated, the padding tooling configuration may include one or more degassing chambers, one or more reactive pre-clean (RPC) chambers, one or more tantalum nitride (TaN) chambers, one or more PVD chambers 105, etc. Semiconductor devices can be provided to one or more of the aforementioned chambers via a processor device (e.g., a robotic arm, multiple robotic arms, etc.). In some embodiments, the padding tooling configuration is used to produce the following combination. Figures 2A to 2H The described semiconductor device. In some embodiments, the semiconductor device is first provided to a degassing chamber, and the degassing chamber processes the semiconductor device. The degassing chamber provides the semiconductor device to an RPC chamber, and the RPC chamber processes the semiconductor device. The RPC chamber provides the semiconductor device to a TaN chamber, and the TaN chamber processes the semiconductor device. The TaN chamber provides the semiconductor device to a PVD chamber 105, and the PVD chamber 105 processes the semiconductor device.

[0057] The degassing chamber may contain a device that activates and removes gaseous and / or liquid substances (e.g., moisture and oxygen) by heating. Without removing these substances, they can prevent thin films from forming on semiconductor devices or alter the properties of the thin films when they are formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In some embodiments, the degassing chamber comprises a chamber capable of removing gases and / or liquids. The chamber may be filled with argon gas (Ar) maintained at a specific temperature (e.g., 200°C, 230°C, etc.) and a specific pressure (e.g., 5 Torr, 6 Torr, 7 Torr, etc.).

[0058] RPC chambers may include tools for removing oxides (e.g., silicon oxide, aluminum oxide, copper oxide, etc.) from the bottom of vias without redepositing material onto the sidewalls of the vias, removing contaminants from the sidewalls, etc. RPC chambers may perform reactive pre-cleaning processes based on helium (He) and hydrogen (H2) plasma. RPC chambers may include chambers capable of achieving optimized hydrogen plasma and active wafer temperature control to ensure copper oxide reduction and via cleaning. The chambers may be filled with a specific amount (e.g., 95%) of helium and a specific amount (e.g., 5%) of hydrogen supplied at a specific flow rate (e.g., 70 standard cubic centimeters per minute (sccm), 80 standard cubic centimeters per minute, 90 standard cubic centimeters per minute, etc.). RPC chambers can apply radio frequency (RF) bias power to semiconductor devices in the range of about 10 watts (W) to about 750 watts.

[0059] TaN chambers can include tools for depositing an insulating layer (e.g., a tantalum nitride layer) on a semiconductor device. The TaN chamber can deposit tantalum nitride via physical vapor deposition (PVD) in a process called reactive sputtering. This allows the sputtering target material to remain within the deposited tantalum nitride layer and provides a more controllable process than chemical vapor deposition (CVD). In some embodiments, the TaN chamber includes a chamber capable of depositing an insulating layer on the semiconductor device. The chamber can be filled with argon (Ar) and nitrogen gas maintained at specific temperatures (e.g., 100°C, 110°C, etc.). Argon gas can be supplied at specific flow rates (e.g., 80 standard cubic centimeters per minute, 90 standard cubic centimeters per minute, 100 standard cubic centimeters per minute, etc.), and nitrogen gas can be supplied at another specific flow rate (e.g., 25 standard cubic centimeters per minute, 30 standard cubic centimeters per minute, 35 standard cubic centimeters per minute, etc.). The TaN chamber can be powered by a specific DC power (e.g., 4 kW, 5 kW, 6 kW, etc.).

[0060] PVD chamber 105 may include tools for depositing an aluminum-copper layer on a semiconductor device. In some embodiments, PVD chamber 105 includes a chamber capable of depositing an aluminum-copper layer on a semiconductor device. The chamber may be filled with argon (Ar) gas maintained at a specific temperature (e.g., 310°C, 330°C, etc.) and supplied at a specific flow rate (e.g., 20 standard cubic centimeters per minute, 25 standard cubic centimeters per minute, 30 standard cubic centimeters per minute, etc.). PVD chamber 105 may be powered using DC power in the range of about 20 kW to about 60 kW and AC power in the range of about 100 watts to about 1200 watts. The AC power may be biased using a frequency in the range of about 2 MHz to about 81.36 MHz. Other ranges of DC and AC power are available for PVD chamber 105. The following is combined with… Figures 1B to 1E Further details are provided for PVD chamber 105.

[0061] like Figure 1B As illustrated, the PVD chamber 105 may include a radio frequency (RF) bias power supply 110, a clamp assembly 115, a cover ring 120, a target assembly 125, and a magnetron 130. The clamp assembly 115, the cover ring 120, the target assembly 125, and the magnetron 130 may be located inside the PVD chamber 105, and the RF bias power supply 110 may be located outside the chamber.

[0062] The RF bias power supply 110 includes devices for supplying power to the clamp assembly 115. The power supplied by the RF bias power supply 110 may include direct current (DC) power in the range of approximately 20 kW to approximately 60 kW and alternating current (AC) power in the range of approximately 100 watts to approximately 1200 watts. The AC power can be biased using frequencies in the range of approximately 2 MHz to approximately 81.36 MHz.

[0063] The clamp assembly 115 includes a support pad sized and shaped to support a semiconductor device. The support pad may include one or more heating elements that receive DC power from an RF bias power supply 110 and AC power for frequency bias, generating heat for the clamp assembly 115. The heat generated by the clamp assembly 115 can be transferred to the semiconductor device based on the semiconductor device in contact with the support pad of the clamp assembly 115. In some embodiments, the temperature of the heat generated by the clamp assembly 115 is in the range of about 300°C to about 400°C to prevent voids in the aluminum-copper layer of the semiconductor device and to improve the performance of the semiconductor device, as described herein. The clamp assembly 115 may also generate temperatures in other ranges.

[0064] The cover ring 120 includes components sized and shaped to prevent plasma (e.g., aluminum-copper plasma, argon plasma, etc.) from leaking from the chamber of the PVD chamber 105. In some embodiments, the cover ring 120 includes an extension (e.g., relative to cover rings used in conventional PVD chambers) to prevent plasma leakage from the PVD chamber 105. (The following is in conjunction with...) Figure 1C Further details for the cap ring 120 are provided.

[0065] The target assembly 125 contains materials for forming a thin film on a semiconductor device via a technique called thin film deposition. For example, the target assembly 125 may contain aluminum, copper, aluminum-copper, etc. In some embodiments, the target assembly 125 contains a specific percentage of aluminum (e.g., 99.5% Al) and a specific percentage of copper (e.g., 0.5% copper). In some embodiments, the PVD chamber 105 may contain multiple target assemblies 125 (e.g., a first target assembly 125 made of aluminum and a second target assembly 125 made of copper). Figure 1B Further illustration shows that the spacing between the target assembly 125 and the clamp assembly 115 can be in the range of about 60 mm to about 80 mm, but other ranges of spacing can still be provided to prevent the formation of voids in the aluminum-copper layer of the semiconductor device and improve the performance of the semiconductor device, as described herein. The spacing can be larger than that used in previous PVD chambers and can provide improved gap filling and film uniformity (e.g., relative to previous PVD chambers) of the aluminum-copper layer applied to the semiconductor device.

[0066] The magnetron 130 includes a plurality of magnetic pillars that generate a magnetic field when the magnetron 130 is rotated. In some embodiments, one or more of the plurality of magnetic pillars include first-type magnetic pillars, second-type magnetic pillars, and so on. The first-type magnetic pillars may include pillar diameters ranging from about 15 mm to about 18 mm and pillar lengths ranging from about 30 mm to about 35 mm to prevent voids in the aluminum-copper layer of the semiconductor device and improve the performance of the semiconductor device, as described herein. Other pillar diameters and pillar lengths may also be used. The second-type magnetic pillars may include standard magnetic pillars previously used in PVD chambers. The first-type magnetic pillars can provide a greater magnetic flux than the second-type magnetic pillars. Therefore, the first-type magnetic pillars can provide a greater aluminum and argon ion density than the second-type magnetic pillars. By providing discontinuous magnetic pillars, the magnetron 130 can be redesigned to improve the film uniformity of the deposited film. Film uniformity is in the range of about 0.5% to about 1.7% compared to other approaches. The following is combined with... Figure 1D and Figure 1E Further details about the magnetron 130 are provided.

[0067] During operation, because the magnetron 130 is located behind the target assembly 125, the plasma generated from the target assembly 125 can be confined to the target surface of the semiconductor device. Rotation of the magnetron 130 generates a magnetic field that forms a closed-loop annular path acting as an electron trap, reshaping the trajectory of secondary electrons emitted from the target assembly 125 into a cycloidal path. This increases the ionization probability of the sputtering gas within the chamber. An inert gas (e.g., argon) can be used as the sputtering gas because inert gases do not tend to react with the target assembly 125 or combine with any process gas, and because inert gases, due to their high molecular weight, produce higher sputtering and deposition rates. Positively charged argon ions from the plasma can be accelerated toward the negatively biased target assembly 125, causing material to displace from the surface of the target assembly 125 and onto the semiconductor device. Figure 1B The diagram further illustrates that the design of the PVD chamber 105 ensures the presence of aluminum ions (Al). + The path to the semiconductor device is more directional than the aluminum ion trajectory generated by the previous PVD chamber (e.g., the non-directional aluminum ion trajectory that makes the voids form).

[0068] Figure 1C yes Figure 1B An enlarged view of the cap ring 120 depicted in the image. (See image for reference.) Figure 1C As illustrated, the cover ring 120 of the PVD chamber 105 may include a body portion 121 integrally formed with a first leg portion 122 and a second leg portion 123. The body portion 121 is positioned and coupled to the edge of the clamp 115, and the first leg portion 122 is located further away from the clamp 115 than the second leg portion 123. In some embodiments, the size and shape of the cover ring 120 are determined based on the size and shape of the PVD chamber 105, the size and shape of the semiconductor device processed by the PVD chamber 105, etc. Figure 1C Further illustrated, and by reference numeral 135, the second leg portion 123 may be extended (e.g., relative to a cover ring previously used in the PVD chamber) to prevent plasma leakage from the PVD chamber 105. In some embodiments, the second leg portion 123 extends a specific length (e.g., greater than or equal to 15 mm) relative to the cover ring previously used in the PVD chamber. If the extension length is less than 15 mm, plasma leakage increases, resulting in an undesirable film distribution in some cases.

[0069] Figure 1D It is a 1D-1D section along the line. Figure 1B The image depicts a cross-sectional view of the magnetron 130. (See image for details.) Figure 1DAs illustrated, magnetron 130 may be divided into different portions, such as upper magnetron 140, lower magnetron 145, outer magnetron 150, inner magnetron 155, etc. In some embodiments, each of the plurality of outer magnetrons and the plurality of inner magnetrons exhibits a closed curve. In some instances, the distribution of at least one of the outer magnetrons 150 and the inner magnetrons 155 has a heart-shaped shape (also referred to as a heart curve, heart surface, or rotating heart). The different portions of magnetron 130 may contain different features. For example, upper magnetron 140 may include a portion of outer magnetron 150 and a portion of inner magnetron 155, and may include a first type of continuous set of magnetic columns, as indicated by reference numeral 160. Lower magnetron 145 may include the remaining portion of outer magnetron 150 and the remaining portion of inner magnetron 155, and may include a second type of discontinuous set of magnetic columns, as indicated by reference numeral 165. The second type of magnetic pillar group is discontinuous because one or more pillars are absent (e.g., removed) between two or more discontinuous magnetic pillar groups, as indicated by reference numeral 170. For example, starting from... Figure 1D The internal starting point 171 shown in the diagram allows for the removal of at least one magnetic column from the internal magnetron 155 to adjust the magnetic flux. Therefore, in some embodiments, the distribution of the right-hand portion of the internal magnetron 155 is symmetrical to the distribution of the left-hand portion; in other embodiments, the right-hand portion is asymmetrical to the left-hand portion. Figure 1D The external starting point 172 shown can be used to adjust the magnetic flux by removing at least one magnetic post and a second magnetic post from the left side of the external magnetron 150. Similarly, the distribution of the right side of the external magnetron 150 can be symmetrical or asymmetrical with the distribution of the left side of the external magnetron 150.

[0070] like Figure 1D Further illustrated, the external magnetron 150 includes a set of external magnetic pillars (e.g., 36 external magnetic pillars). In some embodiments, more than about 64 percent (e.g., >64%) of the external magnetic pillar set is of the first type, and more than about 20 percent (e.g., >20%) of the external magnetic pillar set is of the second type. As further illustrated, the internal magnetron 155 may include a set of internal magnetic pillars (e.g., 24 internal magnetic pillars). In some embodiments, more than about 67 percent (e.g., >67%) of the internal magnetic pillar set is of the first type, and more than about 22 percent (e.g., >22%) of the internal magnetic pillar set is of the second type. The distribution of the first and second types of magnetic pillars described above can prevent the formation of voids in the conductive layer of the semiconductor device and can improve the performance of the semiconductor device. In some embodiments, the conductive layer comprises copper, aluminum, tantalum, and / or combinations thereof.

[0071] Figure 1E This is a graph depicting the magnetic flux generated by the magnetron 130. For example... Figure 1E As illustrated, and via reference numeral 175, the external magnetron 150 can generate an external magnetic flux in the range of about one hundred (100) Gauss to about eight hundred and fifty (850) Gauss. In some embodiments, the external magnetron 150 can generate an external magnetic flux in the range of about one hundred (100) Gauss to about one thousand (1,000) Gauss. Figure 1E As further illustrated, and by reference numeral 180, the internal magnetron 155 can generate an internal magnetic flux in the range of about 200 (200) Gauss to about 950 (950) Gauss. In some embodiments, the internal magnetron 155 can generate an internal magnetic flux in the range of about 100 (100) Gauss to about 1,000 (1,000) Gauss. Other ranges of magnetic flux are possible for the external magnetron 150 and / or the internal magnetron 155.

[0072] In this way, the PVD chamber 105 prevents the formation of voids in the aluminum-copper layer of the semiconductor device and improves the performance of the semiconductor device. Without voids forming in the aluminum-copper layer, the second insulating layer of the semiconductor device can completely cover the aluminum-copper layer. Therefore, the raised chemical layer located on top of the insulating layer cannot contact the aluminum-copper layer and / or damage it.

[0073] As indicated above, Figures 1A to 1E Only one or more instances are provided. Other instances can be found in the documentation. Figures 1A to 1E The instances described are different.

[0074] Figures 2A to 2H This is a diagram illustrating an example semiconductor device 200 (e.g., a logic device, a memory device, a micro-electro-mechanical system (MEMS) device, etc.) and one or more operations involved in manufacturing the example semiconductor device 200. For example... Figure 2A As illustrated, semiconductor device 200 may include pad region 205, redistribution via (RV) region 210, and one or more other components (e.g., circuitry, contacts, metal layers, etc.). In some embodiments, pad region 205 comprises at least one of aluminum, copper, gold, and combinations thereof. Pad region 205 comprises a region of semiconductor device 200, wherein the aluminum-copper pad is formed by PVD chamber 105. The following is in conjunction with... Figures 2B to 2HFurther details describe the aluminum-copper pad. RV region 210 encompasses a region of semiconductor device 200, where RV is provided within semiconductor device 200. Any via failures in the interconnects of semiconductor device 200 (e.g., caused by electromigration, thermal stress, random defects, etc.) can be problematic for semiconductor device 200. Without violating any design for manufacturability (DFM) design rules and while improving via reliability, the RV of RV region 210 can provide an alternative path for the failed via.

[0075] Figure 2B It is along Figure 2A The image shows a cross-sectional view of an embodiment of semiconductor device 200 taken along line 2A-2A. As illustrated, semiconductor device 200 may include an inter-metal dielectric (IMD) layer 215 and a pad 220 formed within the IMD layer 215. In some embodiments, the pad 220 comprises at least one of copper (Cu) or aluminum (Al). The IMD layer 215 may comprise a metallization layer of semiconductor device 200 and may comprise various materials (e.g., aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum, etc.). In some embodiments, the pad 220 is omitted from semiconductor device 200.

[0076] like Figure 2B Further illustration shows that the semiconductor device 200 may include an aluminum-copper (AlCu) pad 225 formed in an opening (e.g., a via) in the first insulating layer 230. The aluminum-copper pad 225 and the first insulating layer 230 may be located on top of the IMD layer 215, and the aluminum-copper pad 225 may contact the IMD layer 215 and / or the pad 220. The aluminum-copper pad 225 may contain a conductive material (e.g., aluminum and copper) that electrically interconnects the IMD layer 215 and / or the pad 220 to other conductive layers of the semiconductor device 200. The first insulating layer 230 may contain a material that insulates a portion of the aluminum-copper pad 225 from other components of the semiconductor device 200 (e.g., other than the IMD layer 215 and / or the pad 220). For example, the first insulating layer 230 may contain tantalum nitride, silicon oxide, silicate glass, silicon carbide, etc.

[0077] like Figure 2B The diagram further illustrates that the semiconductor device 200 may include a second insulating layer 235 located on top of the aluminum-copper pad 225 and on the first insulating layer 230. The second insulating layer 235 may contain a material that insulates a portion of the aluminum-copper pad 225 from other components of the semiconductor device 200 (e.g., other than the IMD layer 215 and / or the pad 220). For example, the second insulating layer 235 may comprise tantalum nitride, silicon oxide, silicate glass, silicon carbide, etc.

[0078] Figures 2C to 2G This is a diagram illustrating the processing operations involved in another embodiment of generating the semiconductor device 200. In some embodiments, the above is combined with... Figure 1A The described pad tool configuration includes one or more chambers for generating another location of the semiconductor device 200. (As...) Figure 2C As illustrated, and via reference numeral 240, the first insulating layer 230 may be located on top of the IMD layer 215. The IMD layer 215 and the first insulating layer 230 may include the elements described above. Figure 2B The described features. In some implementations, the above is combined with... Figure 1A The described liner tool configuration of the TaN chamber can be used to provide a first insulating layer 230 on top of the IMD layer 215.

[0079] like Figure 2D As illustrated, and via reference numeral 245, the first insulating layer 230 can be etched to define a via 250 within the first insulating layer 230. In some embodiments, the etching chamber may utilize liquid chemicals, reactive gases, ionic chemical reactions, etc., to define the via 250 within the first insulating layer 230. Alternatively or additionally, other tools may be used to define the via 250 within the first insulating layer 230.

[0080] like Figure 2E As illustrated herein, and by reference numeral 255, an aluminum-copper (AlCu) layer 260 may be located on top of the first insulating layer 230 and in the via 250 to contact the top surface of the IMD layer 215. The aluminum-copper layer 260 may contain conductive materials (e.g., aluminum and copper) that electrically interconnect the IMD layer 215 to other conductive layers of the semiconductor device 200. The aluminum-copper layer 260 may contain an aspect ratio ranging from about 0.15 to about 1.1, a thickness ranging from about 0.7 micrometers to about 1.3 micrometers, and a diameter ranging from about 1.2 micrometers to about 4 micrometers (e.g., where the aspect ratio is equal to the thickness divided by the diameter) to prevent voids in the aluminum-copper layer 260 of the semiconductor device and to improve the performance of the semiconductor device, as described herein. Other aspect ratios, thicknesses, and diameter ranges may be provided for the aluminum-copper layer 260. In some embodiments, the above-described... Figure 1A The PVD chamber 105 configured as described in the pad tool can be used to provide an aluminum-copper layer 260 on top of the first insulating layer 230 and in the via 250. The PVD chamber 105 prevents the formation of voids in the aluminum-copper layer 260 of the semiconductor device 200, which improves the performance of the semiconductor device 200.

[0081] like Figure 2F As illustrated herein, and by reference numeral 265, a second insulating layer 235 may be located on top of the aluminum-copper layer 260. The second insulating layer 235 may include the elements described above. Figure 2B The described features. In some implementations, the above is combined with... Figure 1AThe TaN chamber of the described liner tool configuration can be used to provide a second insulating layer 235 on top of the aluminum-copper layer 260.

[0082] like Figure 2G As illustrated, and by reference numeral 270, a raised chemical layer 275 may be located on top of the second insulating layer 235. The raised chemical layer 275 may contain an acidic material that can etch one or more portions of the second insulating layer 235, one or more portions of the aluminum-copper layer 260, etc.

[0083] Figure 2H This is a graph depicting an example of Kikuchi band contrast associated with the grain area of ​​the aluminum-copper layer 260, and a graph identifying an example of the number of grains associated with the grain area of ​​the aluminum-copper layer 260. Compared to other manufacturing methods, over 90% of the grain area in the aluminum-copper layer 260 is less than six square micrometers (e.g., <6 square micrometers (μm)). 2 Improving the grain area of ​​the aluminum-copper layer 260 can prevent the formation of voids in the aluminum-copper layer 260.

[0084] In this way, the semiconductor device 200 does not contain voids in the aluminum-copper layer 260, which improves the performance of the semiconductor device 200. With no voids formed in the aluminum-copper layer 260, the second insulating layer 235 of the semiconductor device 200 can completely cover the aluminum-copper layer 260. Therefore, the raised chemical layer 275 located on top of the second insulating layer 235 cannot contact the aluminum-copper layer 260 and / or damage it. Some embodiments described herein can also be used with resistive random access memory devices for ruthenium deposition gap filling improvement.

[0085] As indicated above, Figures 2A to 2H Only one or more instances are provided. Other instances can be found in the documentation. Figures 2A to 2H The instances described are different.

[0086] Figure 3 This is a diagram of an example assembly of device 300. Device 300 may correspond to a degassing chamber, an RPC chamber, a TaN chamber, and / or a PVD chamber 105. In some embodiments, the degassing chamber, RPC chamber, TaN chamber, and / or PVD chamber 105 may contain one or more devices 300 and / or one or more components of device 300. Figure 3 As illustrated, device 300 may include bus 310, processor 320, memory 330, storage component 340, input component 350, output component 360, and communication interface 370.

[0087] Bus 310 includes components that allow communication between components of device 300. Processor 320 is implemented in hardware, firmware, and / or a combination of hardware and software. Processor 320 is a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or another type of processing component. In some embodiments, processor 320 includes one or more processors that can be programmed to perform functions. Memory 330 includes random access memory (RAM), read-only memory (ROM), and / or another type of dynamic or static storage device (e.g., flash memory, magnetic memory, and / or optical memory) that stores information and / or instructions for use by processor 320.

[0088] Storage component 340 stores information and / or software related to the operation and use of device 300. For example, storage component 340 may include a hard disk (e.g., magnetic disk, optical disk, magneto-optical disk, and / or solid-state disk), a compact disc (CD), a digital versatile disc (DVD), a floppy disk, a cassette tape, a magnetic tape, and / or another type of non-transitory computer-readable media, and a corresponding drive.

[0089] Input component 350 includes components that allow device 300 to receive information, for example, via user input (e.g., a touchscreen display, keyboard, keypad, mouse, button, switch, and / or microphone). Alternatively, input component 350 may include sensors for sensing information (e.g., a global positioning system (GPS) component, accelerometer, gyroscope, and / or actuator). Output component 360 includes components that provide output information from device 300 (e.g., a display, speaker, and / or one or more LEDs).

[0090] Communication interface 370 includes transceiver components (e.g., transceivers and / or separate receivers and transmitters) that enable device 300 to communicate with other devices (e.g., via wired, wireless, or a combination of wired and wireless connections). Communication interface 370 allows device 300 to receive information from and / or provide information to another device. For example, communication interface 370 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, an RF interface, a universal serial bus (USB) interface, a wireless LAN interface, a cellular network interface, and so on.

[0091] Device 300 may perform one or more processes described herein. Device 300 may perform these processes based on processor 320 that executes software instructions stored in a non-transitory computer-readable medium, such as memory 330 and / or storage component 340. Computer-readable medium is defined herein as a non-transitory memory device. A memory device is contained within a memory space in a single physical memory device or a memory space distributed across multiple physical memory devices.

[0092] Software instructions may be read into memory 330 and / or storage component 340 via communication interface 370 from another computer-readable medium or from another device. When the software instructions stored in memory 330 and / or storage component 340 are executed, the software instructions may cause processor 320 to perform one or more of the processes described herein. Alternatively or additionally, hard-wired circuitry may be used in place of or in combination with the software instructions to perform one or more of the processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0093] Figure 3 The number and arrangement of components shown are provided as examples. In practice, device 300 may include additional components, fewer components, different components, or components with... Figure 3 The components shown are arranged differently. Alternatively, a group of components of device 300 (e.g., one or more components) may perform one or more functions described as being performed by another group of components of device 300.

[0094] Figure 4 This is a flowchart of an example process 400 for manufacturing an example semiconductor device based on biased aluminum-copper processing technology. In some implementations, Figure 4 One or more process blocks can be performed by a device (e.g., one or more components of the PVD chamber 105). In some embodiments, Figure 4One or more process blocks may be performed by another device or a group of devices that are separate from or contain the device, such as a degassing chamber, a reactive pre-cleaning chamber, a tantalum nitride chamber, etc., and / or one or more other components of the PVD chamber 105.

[0095] like Figure 4 As illustrated, process 400 may include depositing a first insulating layer (box 410) on top of a metal layer of a semiconductor device. For example, a device (e.g., a TaN chamber) may have a first insulating layer 230 deposited on top of a metal layer of semiconductor device 215, as described above.

[0096] like Figure 4 As further illustrated, process 400 may include removing a portion of the first insulating layer to define a via in the first insulating layer (box 420). For example, a device (e.g., an etching chamber) may remove a portion of the first insulating layer 230 to define a via 250 in the first insulating layer 230, as described above.

[0097] like Figure 4 Further illustration shows that process 400 may include depositing an aluminum-copper layer on top of the first insulating layer and in a via, wherein the deposition of the aluminum-copper layer is performed at a temperature ranging from about 300 degrees Celsius to about 400 degrees Celsius and at a magnetic flux ranging from about 200 gauss to about 2000 gauss (box 430). For example, a device (e.g., using RF bias power supply 110, chuck 115, target assembly 125, magnetron 130, etc.) may deposit an aluminum-copper layer 260 on top of the first insulating layer 230 and in a via 250, as described above. In some embodiments, the deposition of the aluminum-copper layer 260 is performed at a temperature ranging from about 300 degrees Celsius to about 400 degrees Celsius and at a magnetic flux ranging from about 200 gauss to about 2000 gauss.

[0098] Process 400 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes described below and / or in combination with those described elsewhere in this document.

[0099] In a first embodiment, the device includes a chamber, a clamp 115 located within the chamber, and a bias power supply 110 physically connected to the clamp 115. A target assembly 125 may be located above the clamp 115 and the bias power supply 110, and a magnetron assembly 130 may be located above the target assembly 125. The magnetron assembly 130 may include a plurality of external magnetrons 150 and a plurality of internal magnetrons 155, and the spacing between each adjacent magnetron in the plurality of external magnetrons 150 may be different from the spacing between each adjacent magnetron in the plurality of internal magnetrons 155.

[0100] In a second embodiment, either alone or in combination with the first embodiment, the plurality of external magnetrons 150 include a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion.

[0101] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, the spacing between the clamp 115 and the target assembly 125 ranges from about sixty millimeters to about eighty millimeters.

[0102] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the device includes a cover ring 120 coupled to the edge of the clamp 115, wherein the cover ring 120 includes a first leg portion 122 that is shorter than the second leg portion 123.

[0103] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the bias power supply 110 will be in the range of DC power from about 20 kilowatts to about 60 kilowatts and AC power from about 100 watts to about 1,200 watts.

[0104] In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the bias power supply 110 provides AC bias power with a frequency in the range of approximately two MHz to approximately eighty-one MHz.

[0105] In a seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, the plurality of internal magnetrons 155 include a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion.

[0106] In the eighth embodiment, either alone or in combination with one or more of the first to seventh embodiments, the spacing between each adjacent magnetron in the first portion is consistent, while the spacing between each adjacent magnetron in the second portion is inconsistent.

[0107] In a ninth embodiment, either alone or in combination with one or more of the first to eighth embodiments, the magnetron assembly 130 includes a plurality of magnetic pillars, wherein a portion of the plurality of magnetic pillars includes a pillar diameter ranging from about fifteen millimeters to about eighteen millimeters and a pillar length ranging from about thirty millimeters to about thirty-five millimeters.

[0108] In the tenth embodiment, either alone or in combination with one or more of the first to ninth embodiments, at least one of the first plurality of magnetrons or the second plurality of magnetrons has a heart shape.

[0109] In the eleventh embodiment, either alone or in combination with one or more of the first to tenth embodiments, a portion of the aluminum-copper layer 260 located in the via 250 contacts the metal layer 215 without voids, and more than ninety percent of the grain area of ​​the aluminum-copper layer 260 is less than six square micrometers.

[0110] In the twelfth embodiment, alone or in combination with one or more of the first to eleventh embodiments, the thickness of the aluminum-copper layer 260 is in the range of about seven thousand angstroms to about twenty-eight thousand angstroms.

[0111] In the thirteenth embodiment, alone or in combination with one or more of the first to twelfth embodiments, the semiconductor device includes at least one of a logic device, a memory device, a microelectromechanical system device, and a high-voltage device.

[0112] In the fourteenth embodiment, either alone or in combination with one or more of the first to thirteenth embodiments, the deposition of the aluminum-copper layer 260 is performed to achieve a uniformity of the aluminum-copper layer 260 in the range of about 0.5% to about 1.7%.

[0113] In the fifteenth embodiment, either alone or in combination with one or more of the first to fourteenth embodiments, an aluminum-copper layer 260 is provided on top of the first insulating layer 230 and in the through-hole 250, comprising providing the aluminum-copper layer 260 based on the magnetic field generated by the magnetron 130 of the device.

[0114] although Figure 4 The drawing process 400 is an instance frame, but in some implementations, it is different from... Figure 4 Compared to the boxes depicted, process 400 may contain additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes of process 400 may be executed in parallel.

[0115] In this way, the PVD chamber 105 prevents the formation of voids in the aluminum-copper layer 260 of the semiconductor device 200 and improves the performance of the semiconductor device 200. When no voids are formed in the aluminum-copper layer 260, the second insulating layer 235 of the semiconductor device 200 can completely cover the aluminum-copper layer 260. Therefore, the raised chemical layer 275 located on top of the second insulating layer 235 cannot contact the aluminum-copper layer 260 and / or damage it.

[0116] As described in more detail above, some embodiments described herein provide an apparatus for manufacturing semiconductor devices. The apparatus may include a chamber, a chuck located within the chamber, and a bias power supply physically connected to the chuck. The apparatus may include a target assembly located above the chuck and the bias power supply, and a magnetron assembly located above the target assembly. The magnetron assembly may include a plurality of external magnetrons and a plurality of internal magnetrons, and the spacing between each adjacent magnetron in the plurality of external magnetrons may be different from the spacing between each adjacent magnetron in the plurality of internal magnetrons. In some embodiments, the plurality of external magnetrons includes a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion. In some embodiments, the spacing between the chuck and the target assembly is in the range of about sixty millimeters to about eighty millimeters. In some embodiments, the apparatus further includes a cover ring coupled to an edge of the chuck, wherein the cover ring includes a first leg portion shorter than a second leg portion. In some embodiments, the bias power supply will be in the range of DC power in the range of about 20 kW to about 60 kW and AC power in the range of about 100 kW to about 1200 kW. In some embodiments, the bias power supply will provide AC bias power in the range of about 2 MHz to about 81 MHz. In some embodiments, the plurality of internal magnetrons includes a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion. In some embodiments, the spacing between each adjacent magnetron in the first portion is uniform, while the spacing between each adjacent magnetron in the second portion is non-uniform. In some embodiments, the magnetron assembly includes a plurality of magnetic pillars, wherein a portion of the plurality of magnetic pillars includes a pillar diameter in the range of about 15 mm to about 18 mm and a pillar length in the range of about 30 mm to about 35 mm. In some embodiments, at least one of the first plurality of magnetrons or the second plurality of magnetrons has a heart shape. As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method may include depositing a first insulating layer on top of a metal layer of the semiconductor device and removing a portion of the first insulating layer to define a via in the first insulating layer. The method may include depositing an aluminum-copper layer on top of a first insulating layer and in a via, wherein the deposition of the aluminum-copper layer is performed at a temperature ranging from about 300 degrees Celsius to about 400 degrees Celsius and at a magnetic flux ranging from about 200 gauss to about 2000 gauss. In some embodiments, a portion of the aluminum-copper layer located in the via contacts the metal layer without voids, and wherein more than 90 percent of the grain area of ​​the aluminum-copper layer is less than six square micrometers. In some embodiments, the deposition of the aluminum-copper layer is performed by a bias power comprising an AC bias power with a frequency ranging from about 2 MHz to about 81 MHz.In some embodiments, the thickness of the aluminum-copper layer is in the range of about 7,000 angstroms to about 28,000 angstroms. In some embodiments, the semiconductor device includes at least one of the following: a logic device, a memory device, a microelectromechanical system (MEMS) device, and a high-voltage device. In some embodiments, depositing the aluminum-copper layer is performed to achieve a uniformity of the aluminum-copper layer in the range of about 0.5% to about 1.7%. In some embodiments, providing the aluminum-copper layer on top of the first insulating layer and in the via comprises: providing the aluminum-copper layer based on a magnetic field generated by a magnetron of a tool.

[0117] As described in more detail above, some embodiments described herein provide a semiconductor device comprising a metal layer and a first insulating layer on top of the metal layer, wherein a plurality of vias are formed in the first insulating layer. The semiconductor device may include an aluminum-copper layer on top of the first insulating layer and within the plurality of vias. The aluminum-copper layer may be provided at a temperature in the range of about 300 degrees Celsius to about 400 degrees Celsius to prevent the formation of voids in the aluminum-copper layer, and the temperature may be generated by a chuck assembly of a tool, the chuck assembly being powered by bias power. The semiconductor device may include a second insulating layer on top of the aluminum-copper layer and a raised chemical layer on top of the second insulating layer. In some embodiments, about 91 percent of the grain area of ​​the aluminum-copper layer is less than about six square micrometers. In some embodiments, the thickness of the aluminum-copper layer is in the range of about 7,000 angstroms to about 28,000 angstroms.

[0118] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An apparatus for manufacturing a semiconductor device, the apparatus comprising: Chamber; The clamping plate is located in the chamber; A bias power supply is physically connected to the clamp. The target assembly is located above the clamp and the bias power supply; as well as The magnetron assembly is located above the target assembly. The magnetron assembly comprises a plurality of external magnetrons and a plurality of internal magnetrons, wherein the spacing between each adjacent magnetron in the plurality of external magnetrons is different from the spacing between each adjacent magnetron in the plurality of internal magnetrons. The internal magnetron comprises multiple continuous magnetic column groups of a first type and multiple discontinuous magnetic column groups of a second type.

2. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the plurality of external magnetrons comprises a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion.

3. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the distance between the clamp and the target assembly is in the range of sixty to eighty millimeters.

4. The apparatus for manufacturing a semiconductor device according to claim 1, further comprising: A cover ring, coupled to the edge of the clamp, wherein the cover ring includes a first leg portion that is shorter than the second leg portion.

5. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the bias power supply provides DC power in the range of 20 kW to 60 kW and AC power in the range of 100 kW to 1200 kW.

6. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the bias power supply provides AC bias power in the frequency range of 2 MHz to 81 MHz.

7. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the plurality of internal magnetrons comprises a first portion and a second portion, wherein the spacing between each adjacent magnetron in the first portion is different from the spacing between each adjacent magnetron in the second portion.

8. The apparatus for manufacturing a semiconductor device according to claim 7, wherein the spacing between each adjacent magnetron in the first portion is uniform, while the spacing between each adjacent magnetron in the second portion is non-uniform.

9. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the magnetron assembly comprises: Multiple magnetic pillars, A portion of the plurality of magnetic pillars comprises a pillar diameter ranging from 15 mm to 18 mm and a pillar length ranging from 30 mm to 35 mm.

10. The apparatus for manufacturing a semiconductor device according to claim 1, wherein at least one of the plurality of external magnetrons or the plurality of internal magnetrons has a heart shape.

11. A method for manufacturing a semiconductor device, the method comprising: A first insulating layer is deposited on top of the metal layer of the semiconductor device; A portion of the first insulating layer is removed to define a via in the first insulating layer; as well as Based on the magnetic field generated by the magnetron assembly of the device, an aluminum-copper layer is deposited on top of the first insulating layer and in the through-hole. The deposition of the aluminum-copper layer is performed at a temperature ranging from 300 to 400 degrees Celsius and at a magnetic flux ranging from 200 to 2000 gauss. The internal magnetron of the magnetron assembly includes multiple first-type continuous magnetic column groups and multiple second-type discontinuous magnetic column groups.

12. The method of manufacturing a semiconductor device according to claim 11, wherein a portion of the aluminum-copper layer located in the via contacts the metal layer and has no voids, and wherein more than 90 percent of the grain area of ​​the aluminum-copper layer is less than six square micrometers.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the deposition of the aluminum-copper layer is performed by a bias power comprising an AC bias power in the frequency range of 2 MHz to 81 MHz.

14. The method for manufacturing a semiconductor device according to claim 11, wherein the thickness of the aluminum-copper layer is in the range of 7,000 angstroms to 28,000 angstroms.

15. The method for manufacturing a semiconductor device according to claim 11, wherein the semiconductor device comprises at least one of the following: Logic devices Memory devices, Microelectromechanical systems (MEMS) devices, and High voltage devices.

16. The method for manufacturing a semiconductor device according to claim 11, wherein the deposition of the aluminum-copper layer is performed to achieve a uniformity of the aluminum-copper layer in the range of 0.5% to 1.7%.

17. A semiconductor device, comprising: Metal layer; The first insulating layer is located on top of the metal layer. Multiple through-holes are formed in the first insulating layer; An aluminum-copper layer is located on top of the first insulating layer and within the plurality of through-holes. The aluminum-copper layer is provided at a temperature ranging from 300 to 400 degrees Celsius based on the magnetic field generated by the magnetron assembly of the device to prevent the formation of voids in the aluminum-copper layer. The internal magnetron of the magnetron assembly includes multiple continuous magnetic column groups of the first type and multiple discontinuous magnetic column groups of the second type, wherein the temperature is generated by the clamp assembly of the device and the clamp assembly is powered by bias power. The second insulating layer is located on top of the aluminum-copper layer; as well as A raised chemical layer is located on top of the second insulating layer.

18. The semiconductor device of claim 17, wherein 91 percent of the grain area of ​​the aluminum-copper layer is less than six square micrometers.

19. The semiconductor device of claim 17, wherein the thickness of the aluminum-copper layer is in the range of 7,000 angstroms to 28,000 angstroms.

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