Semiconductor device structure and packaging components

Abstract

This invention provides a semiconductor device structure and a packaging assembly. The semiconductor device structure includes: a semiconductor substrate having a first surface and a second surface opposite thereto; a gallium nitride-based device layer formed on the first surface of the semiconductor substrate, and having source, drain, and gate contact regions; first, second, and third via electrodes penetrating the semiconductor substrate and electrically connected to the source, drain, and gate contact regions, respectively; and an insulating liner formed on the second surface of the semiconductor substrate, extending within the semiconductor substrate, and separating the second and third via electrodes from the semiconductor substrate. This embodiment also provides a packaging assembly having the above-described semiconductor device structure. This simplifies the manufacturing process and avoids the use of costly bonding wires.

Description

Technical Field

[0001] This invention relates to a semiconductor technology, and more particularly to a gallium nitride-based semiconductor device structure having a through-substrate via (TSV) electrode. Background Technology

[0002] Group III nitride semiconductors are semiconductors formed using nitrogen as a group V element in the group III-V semiconductor category, such as gallium nitride (GaN), aluminum nitride (AlN), or indium nitride (InN). Because the physical properties of group III nitride semiconductors are suitable for use in high-temperature, high-power, and high-frequency devices, some semiconductor devices (e.g., high electron mobility transistors (HEMTs)) utilize group III nitride semiconductors.

[0003] To reduce production costs, group III nitride semiconductor devices are widely used in power switches. For example, GaN transistors (GaN-on-Si wafers) are fabricated on a lower-cost silicon substrate. GaN power transistors offer low on-resistance (R0) per unit effective area of ​​the device. on High current. However, in order to benefit from the characteristics of group III nitride semiconductor devices, there is a current need to improve the electrical connections and packaging of group III nitride semiconductor devices to achieve low-inductance packaging and effective thermal management.

[0004] Therefore, it is necessary to seek a novel packaging method to solve or improve the above problems. Summary of the Invention

[0005] This invention provides a semiconductor device structure, comprising: a semiconductor substrate having a first surface and a second surface opposite thereto; a gallium nitride-based device layer formed on the first surface of the semiconductor substrate, having a source contact region, a drain contact region, and a gate contact region; a first via electrode, a second via electrode, and a third via electrode penetrating the semiconductor substrate and electrically connected to the source contact region, the drain contact region, and the gate contact region, respectively; and an insulating liner formed on the second surface of the semiconductor substrate, extending within the semiconductor substrate and separating the second via electrode and the third via electrode from the semiconductor substrate.

[0006] This invention provides a packaging component, including: a circuit substrate and a wafer assembled on the circuit substrate. The wafer includes: a semiconductor substrate having an active surface and a non-active surface opposite to the active surface; a gallium nitride (GaN)-based device layer formed on the active surface of the semiconductor substrate; a source electrode structure, a drain electrode structure, and a gate electrode structure extending from the active surface of the semiconductor substrate and protruding from the GaN-based device layer; and a first redistribution layer, a second redistribution layer, and a third redistribution layer extending from the non-active surface of the semiconductor substrate and electrically connected to the source electrode structure, the drain electrode structure, and the gate electrode structure, respectively. A portion of the first redistribution layer, a portion of the second redistribution layer, and a portion of the third redistribution layer on the non-active surface of the semiconductor substrate each have a first area, a second area, and a third area, respectively, and the first area is larger than the second area and the third area.

[0007] This invention provides a semiconductor device structure, comprising: a semiconductor substrate having an active surface and a non-active surface relative to the active surface; a gallium nitride-based device layer formed on the active surface of the semiconductor substrate, having a first electrode contact region and a second electrode contact region; a first via electrode and a second via electrode extending through the semiconductor substrate and electrically connected to the first electrode contact region and the second electrode contact region, respectively; and a first conductive layer and a second conductive layer extending from the first via electrode and the second via electrode above the non-active surface of the semiconductor substrate, wherein the first conductive layer and the second conductive layer have a first area and a second area, and the first area is different from the second area. Attached Figure Description

[0008] Figure 1 A cross-sectional schematic diagram of a semiconductor packaging assembly according to some embodiments of the present invention is shown.

[0009] Figure 2 A cross-sectional schematic diagram of a semiconductor packaging assembly according to some embodiments of the present invention is shown.

[0010] Figure 3 A bottom plan view of a semiconductor device structure according to some embodiments of the present invention is shown.

[0011] The symbols in the attached diagram are briefly explained as follows:

[0012] 10, 20: Package components; 100: Semiconductor substrate; 100a: First surface; 100b: Second surface; 110: Group III nitride semiconductor device layer; 111D: Drain contact region; 111G: Gate contact region; 111S: Source contact region; 120: Internal interconnect structure; 120D: Drain pad; 120G: Gate pad; 120S: Source pad; 121: Bottom metal layer; 122: Insulating layer; 123: Metal plug; 125D: Drain electrode structure; 125G: Gate electrode structure; 125S: Source electrode structure; 128: Insulating liner; 130, 140, 150: Redistribution layers; 130a, 140a, 150a: Through-hole electrodes; 130b, 140b, 150b: Conductive layers; 200: Circuit substrate; 201: Ground pad. Detailed Implementation

[0013] The following will describe in detail the manufacturing and usage methods of embodiments of the present invention. However, it should be noted that the present invention provides many applicable inventive concepts, which can be implemented in various specific forms. The specific embodiments discussed and illustrated herein are merely specific ways of manufacturing and using the present invention and are not intended to limit the scope of the invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are merely for the purpose of clearly and simply describing the present invention and do not represent any association between the different embodiments and / or structures discussed. Moreover, when referring to a first material layer located on or above a second material layer, this includes situations where the first material layer and the second material layer are in direct contact or spaced apart by one or more other material layers.

[0014] One embodiment of the present invention provides a semiconductor packaging assembly for packaging a semiconductor wafer having a GaN device. Specifically, a wafer-level packaging (WSP) process can be used to package the semiconductor wafer. The aforementioned wafer-level packaging process primarily refers to dicing the wafer into individual packages after the packaging steps are completed at the wafer stage. However, in a specific embodiment, for example, redistributing the separated semiconductor wafers onto a carrier wafer before performing the packaging process can also be referred to as a wafer-level packaging process.

[0015] The embodiments described below may discuss specific content, such as the application of the semiconductor packaging assembly and its manufacturing method to group III nitride semiconductor device technology. However, those skilled in the art will understand from the disclosure that various other applications may be considered in other embodiments. It should be noted that the embodiments discussed herein may not necessarily describe every component that may be present in the structure; for example, components may be omitted from the drawings when a discussion of the components is sufficient to convey the various aspects of the embodiments.

[0016] The following combinations Figures 1 to 3This invention describes semiconductor packaging components according to some embodiments of the present invention, wherein... Figure 1 and 2 Cross-sectional schematic diagrams of semiconductor packaging components 10 and 20 according to some embodiments of the present invention are shown respectively. Figure 3 A bottom plan view of a semiconductor device structure according to some embodiments of the present invention is shown.

[0017] Please refer to Figure 1 The semiconductor packaging assembly 10 includes a circuit substrate 200 and a semiconductor device structure assembled on the circuit substrate 200. In some embodiments, the semiconductor device structure may be implemented as a semiconductor wafer and includes a semiconductor substrate 100. The semiconductor substrate 100 has a first surface 100a and a second surface 100b opposite thereto. In some embodiments, the first surface 100a may be an active surface (sometimes referred to as the front surface) of the semiconductor substrate 100. In the above cases, the second surface 100b opposite to the first surface 100a may be a non-active surface (sometimes referred to as the back surface) of the semiconductor substrate 100. The semiconductor substrate 100 may be a silicon substrate, which may be a portion of a silicon wafer. The semiconductor substrate 100 may also be made of other semiconductor materials. For example, the semiconductor substrate 100 may include elemental (single-element) semiconductors (e.g., silicon, germanium, and / or other suitable materials), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials), and alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials). In some other embodiments, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, having a silicon layer formed on a silicon oxide layer.

[0018] In some embodiments, the semiconductor device structure further includes a group III nitride semiconductor device layer 110 formed on a first surface 100a of the semiconductor substrate 100. In some embodiments, the group III nitride semiconductor device layer 110 may be a gallium nitride-based device layer (i.e., a GaN device layer) for defining one or more GaN devices (not shown), such as GaN power transistors. In the above context, the semiconductor device structure is also referred to as a GaN wafer.

[0019] In some embodiments, the group III nitride semiconductor device layer 110 for defining one or more transistors has multiple electrode contact regions, including one or more source contact regions, one or more drain contact regions, and one or more gate contact regions. For simplicity, only one source contact region 111S, one drain contact region 111D, and one gate contact region 111G are shown here. Furthermore, it is understood that the arrangement of the source contact region 111S, drain contact region 111D, and gate contact region 111G is not limited to... Figure 1 The illustrated embodiment. For example, the gate contact region 111G may be located between the source contact region 111S and the drain contact region 111D.

[0020] In some embodiments, the group III nitride semiconductor device layer 110 has a lower surface that contacts a first surface 100a of the semiconductor substrate 100 and an upper surface opposite to the first surface 100a. Source contact region 111S, drain contact region 111D, and gate contact region 111G extend from the upper surface of the group III nitride semiconductor device layer 110 to the lower surface of the group III nitride semiconductor device layer 110 and pass through the group III nitride semiconductor device layer 110. In some embodiments, only the source contact region 111S passes through the group III nitride semiconductor device layer 110. The drain contact region 111D and the gate contact region 111G are formed on the upper surface of the group III nitride semiconductor device layer 110.

[0021] In some embodiments, the semiconductor device structure further includes an internal connection structure 120 formed on the group III nitride semiconductor device layer 110. The internal connection structure 120 may include an insulating layer 122 and a plurality of electrode structures formed within the insulating layer 122.

[0022] In some embodiments, the insulating layer 122 surrounds each electrode structure and includes a dielectric material. For example, the insulating layer 122 may be formed of an oxygen-containing dielectric material, such as tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like.

[0023] In some embodiments, the electrode structure includes a corresponding electrode contact region located within the group III nitride semiconductor device layer 110, such that the electrode structure extends through and protrudes from the first surface 100a (i.e., the active surface) of the semiconductor substrate 100 and extends beyond the group III nitride semiconductor device layer 110. For the sake of simplicity, only a source electrode structure 125S, a drain electrode structure 125D, and a gate electrode structure 125G are shown here.

[0024] In some embodiments, each electrode structure further includes multiple stacked metal layers located at different positions within the insulating layer 122 and multiple metal plugs connecting the different metal layers. For simplicity, only a top metal layer serving as a pad, a bottom metal layer electrically connected to the corresponding electrode contact area, and two metal plugs electrically connecting the top and bottom metal layers are shown for each electrode structure. For example, the source electrode structure 125S includes a source pad 120S (also called the source electrode), a corresponding metal plug 123, a corresponding bottom metal layer 121, and a corresponding source contact area 111S. The drain electrode structure 125D includes a drain pad 120D (also called the drain electrode), a corresponding metal plug 123, a corresponding bottom metal layer 121, and a corresponding drain contact area 111D. The gate electrode structure 125G includes a gate pad 120G (also called the gate electrode), a corresponding metal plug 123, a corresponding bottom metal layer 121, and a corresponding gate contact area 111G.

[0025] In some embodiments, the semiconductor device structure further includes a plurality of through-via electrodes corresponding to the electrode contact regions of the group III nitride semiconductor device layer 110 formed within the semiconductor substrate 100. For simplicity, only one through-via electrode 130a corresponding to the source contact region 111S, one through-via electrode 140a corresponding to the drain contact region 111D, and one through-via electrode 150a corresponding to the gate contact region 111G are shown here. In some embodiments, through-via electrode 130a extends from the second surface 100b of the semiconductor substrate 100 to the first surface 100a of the semiconductor substrate 100 and is electrically connected to the source contact region 111S of the group III nitride semiconductor device layer 110. Similarly, through-via electrode 140a extends from the second surface 100b of the semiconductor substrate 100 to the first surface 100a of the semiconductor substrate 100 and is electrically connected to the drain contact region 111D of the group III nitride semiconductor device layer 110. The via electrode 150a extends from the second surface 100b of the semiconductor substrate 100 to the first surface 100a of the semiconductor substrate 100 and is electrically connected to the gate contact region 111G of the group III nitride semiconductor device layer 110. In some other embodiments, the drain contact region 111D and the gate contact region 111G are formed on the upper surface of the group III nitride semiconductor device layer 110, and the via electrodes 140a and 150a further penetrate the group III nitride semiconductor device layer 110 and are electrically connected to the corresponding drain contact region 111D and gate contact region 111G.

[0026] In some embodiments, the through-hole electrodes 130a, 140a and 150a comprise a metallic material, such as aluminum, copper, titanium, tungsten, tantalum, nickel, alloys thereof or combinations thereof or other suitable metallic materials.

[0027] In some embodiments, the semiconductor device structure further includes a plurality of conductive layers corresponding to via electrodes 130a, 140a, and 150a, such as conductive layer 130b corresponding to via electrode 130a, conductive layer 140b corresponding to via electrode 140a, and conductive layer 150b corresponding to via electrode 150a. Conductive layers 130b, 140b, and 150b extend from one end of via electrodes 130a, 140a, and 150a adjacent to the second surface 100b of the semiconductor substrate 100 and over the second surface 100b of the semiconductor substrate 100.

[0028] In some embodiments, the combination of via electrodes 130a, 140a, and 150a with corresponding conductive layers 130b, 140b, and 150b is also referred to as a redistribution layer (RDL). In this case, the combination of via electrode 130a and conductive layer 130b constitutes redistribution layer 130. That is, redistribution layer 130 has a first portion (i.e., via electrode 130a) located within semiconductor substrate 100 and a second portion (i.e., conductive layer 130b) located on the second surface (i.e., non-active surface) 100b of semiconductor substrate 100. Similarly, the combination of via electrode 140a and conductive layer 140b constitutes redistribution layer 140. That is, redistribution layer 140 has a first portion (i.e., via electrode 140a) located within semiconductor substrate 100 and a second portion (i.e., conductive layer 140b) located on the second surface 100b of semiconductor substrate 100. Furthermore, the combination of the via electrode 150a and the conductive layer 150b constitutes the redistribution layer 150. The redistribution layer 150 has a first portion (i.e., the via electrode 150a) located within the semiconductor substrate 100 and a second portion (i.e., the conductive layer 150b) located on the second surface 100b of the semiconductor substrate 100. In some embodiments, the respective conductive layers 130b, 140b, and 150b of the redistribution layers 130, 140, and 150 have pad regions (not shown) as junction regions with the circuit substrate 200 (e.g., source pad region, drain pad region, and gate pad region).

[0029] In some embodiments, the through-hole electrodes 130a, 140a, and 150a and the corresponding conductive layers 130b, 140b, and 150b are composed of the same metal material layer. In some other embodiments, the metal material constituting the through-hole electrodes 130a, 140a, and 150a is different from the metal material constituting the conductive layers 130b, 140b, and 150b.

[0030] In some embodiments, conductive layers 130b, 140b, and 150b each have a first area, a second area, and a third area, respectively, and the first area is different from the second and third areas. Here, the first area, second area, and third area represent the areas of conductive layers 130b, 140b, and 150b projected onto the second surface 100b of the semiconductor substrate 100. In some embodiments, the first area is larger than the second and third areas, such as... Figure 3 As shown. Furthermore, the second area may be the same as or different from the third area.

[0031] Please refer to again Figure 3 This diagram shows a bottom plan view of a semiconductor device structure having multiple source pads 120S, multiple drain pads 120D, and multiple gate pads 120G. For clarity, Figure 3The insulating liner 128 formed on the second surface 100b of the semiconductor substrate 100 is not shown in the diagram of the semiconductor device structure. In some embodiments, multiple or all of the source pads 120S are electrically connected to each other via corresponding via electrodes 130a (as shown by dashed circles) and a single conductive layer 130b (also referred to as a common conductive layer) extending from the via electrodes. Furthermore, multiple drain pads 120D are electrically connected to corresponding redistribution layers 140 but not electrically connected to each other. Similarly, multiple gate pads 120G are electrically connected to corresponding redistribution layers 150 but not electrically connected to each other. In this way, the area of ​​the common conductive layer 130b is larger than the area of ​​the conductive layer of each redistribution layer 140 and the area of ​​the conductive layer of each redistribution layer 150.

[0032] In some embodiments, a large-area common conductive layer 130b serves as a heat dissipation layer to effectively conduct heat generated by the semiconductor device structure to the circuit substrate 200 and / or the external environment. This effectively improves the thermal management of the package assembly 10. It is understood that the shape and size of the common conductive layer 130b can be adjusted according to design requirements and are not limited to... Figure 3 The example shown.

[0033] In some embodiments, the semiconductor device structure further includes an insulating liner 128 formed on a second surface 100b of the semiconductor substrate 100. The insulating liner 128 also extends within the semiconductor substrate 100, electrically isolating the redistribution layers 140 and 150 (i.e., via electrodes 140a and 150a and their corresponding conductive layers 140b and 150b) from the semiconductor substrate 100. In this case, the insulating liner 128 surrounds the via electrodes 140a and 150a located within the semiconductor substrate 100. In some embodiments, the insulating liner 128 comprises an oxide (e.g., silicon oxide) or other suitable inorganic material (e.g., silicon nitride, silicon oxynitride, metal oxide, or a combination thereof).

[0034] In some embodiments, the semiconductor substrate 100 separates the insulating liner 128 from the redistribution layer 130 (i.e., the via electrode 130a and the corresponding conductive layer 130b), allowing the redistribution layer 130 to be in direct contact with the semiconductor substrate 100. In this way, the redistribution layer 130 can serve as a ground layer, allowing the source contact region 111S to be grounded via the semiconductor substrate 100, thereby reducing noise in the semiconductor device structure.

[0035] In some embodiments, the circuit substrate 200 (e.g., a package substrate) has a grounding pad 201 electrically connected to the conductive layer 130b of the redistribution layer 130. In this way, the source contact region 111S is also grounded via the grounding pad 201 of the circuit substrate 200, thereby further reducing noise in the semiconductor device structure.

[0036] Furthermore, the circuit substrate 200 also has signal pads (not shown) for bonding the conductive layers 140b of the redistribution layer 140 and 150b of the redistribution layer 150, so that the semiconductor device structure is assembled on the circuit substrate 200 to form the package assembly 10. That is, in the package assembly 10, the drain contact region 111D and the gate contact region 111G in the group III nitride semiconductor device layer 110 can be electrically connected to the circuit substrate 200 through the redistribution layers 140 and 150.

[0037] Please refer to Figure 2 It illustrates a cross-sectional schematic diagram of a packaging component 20 according to some embodiments of the present invention, wherein the same as Figure 1 The components in the document use the same reference numerals and their descriptions may be omitted. In some embodiments, the structure of the encapsulation component 20 is similar to... Figure 1 The difference in the structure of the packaging component 10 lies in that the insulating liner 128 extends further between the redistribution layer 130 (i.e., the via electrode 130a and the corresponding conductive layer 130b) and the semiconductor substrate 100 to separate them and electrically isolate the redistribution layer 130 from the semiconductor substrate 100. In this case, the insulating liner 128 surrounds the via electrode 130a located within the semiconductor substrate 100.

[0038] According to the above embodiments, since the source contact region, drain contact region, and gate contact region within the group III nitride semiconductor device layer of the package assembly are electrically connected to the circuit substrate through corresponding via electrodes, it is not necessary to use wiring to bond the semiconductor device structure (e.g., a wafer) to the circuit substrate. This simplifies the manufacturing process and avoids the use of costly bonding wires (e.g., gold wires).

[0039] According to the above embodiments, since through-hole electrodes are used instead of bonding wires, the internal connection path can be shortened to achieve low-inductance packaging and reduce the size (e.g., height) of the package assembly.

[0040] According to the above embodiments, since the via electrode connected to the source contact area can directly contact the semiconductor substrate, device noise can be reduced and effective thermal management can be achieved.

[0041] According to the above embodiments, multiple or all source contact regions located within the group III nitride semiconductor device layer can be electrically connected to a common conductive layer with a large area via corresponding via electrodes. This common conductive layer with a large area can serve as a heat dissipation layer to effectively conduct heat generated by the semiconductor device structure to the circuit substrate and / or the external environment. This further improves the thermal management of the packaged assembly.

[0042] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. A semiconductor device structure, comprising: A semiconductor substrate having a first surface and a second surface opposite thereto; A gallium nitride-based device layer has a lower surface adjacent to the first surface of the semiconductor substrate, such that the upper surface of the gallium nitride-based device layer is higher than the first surface, and has a source contact region, a drain contact region and a gate contact region. The first through-hole electrode, the second through-hole electrode, and the third through-hole electrode penetrate the semiconductor substrate and are electrically connected to the source contact region, the drain contact region, and the gate contact region, respectively; and An insulating liner is formed on the second surface of the semiconductor substrate and extends through the semiconductor substrate, having an end adjacent to the first surface, and separating the second via electrode and the third via electrode from the semiconductor substrate.

2. The semiconductor device structure of claim 1, wherein the semiconductor substrate separates the insulating liner from the first via electrode.

3. The semiconductor device structure as claimed in claim 2, wherein the first through-hole electrode is in direct contact with the semiconductor substrate.

4. The semiconductor device structure of claim 1, wherein the insulating liner separates the first via electrode from the semiconductor substrate.

5. The semiconductor device structure as described in claim 1, further comprising: An internal connection structure is formed on the gallium nitride-based device layer, wherein the internal connection structure has a source pad, a drain pad and a gate pad, which are electrically connected to the source contact region, the drain contact region and the gate contact region, respectively.

6. The semiconductor device structure as claimed in claim 1, further comprising: The first conductive layer, the second conductive layer, and the third conductive layer extend from the first through-hole electrode, the second through-hole electrode, and the third through-hole electrode, respectively, above the second surface on the semiconductor substrate.

7. The semiconductor device structure of claim 6, wherein the first conductive layer, the second conductive layer and the third conductive layer have a first area, a second area and a third area respectively, and the first area is different from the second area and the third area.

8. The semiconductor device structure of claim 7, wherein the first area is larger than the second area and the third area.

9. A semiconductor packaging assembly, comprising: Circuit substrate; as well as A chip, assembled on the circuit substrate, includes: A semiconductor substrate having an active surface and a non-active surface relative to the active surface; A gallium nitride-based device layer has a lower surface adjacent to the active surface of the semiconductor substrate, such that the upper surface of the gallium nitride-based device layer is higher than the active surface; The source electrode structure, drain electrode structure, and gate electrode structure each have a lower surface adjacent to the active surface of the semiconductor substrate, and the source electrode structure, drain electrode structure, and gate electrode structure extend through and protrude from the gallium nitride-based device layer; and The first, second, and third wiring layers extend from the non-active surface of the semiconductor substrate, pass through the semiconductor substrate, and are electrically connected to the lower surface of the source electrode structure, the lower surface of the drain electrode structure, and the lower surface of the gate electrode structure, respectively. The portions of the first redistribution layer, the second redistribution layer, and the third redistribution layer located on the non-active surface of the semiconductor substrate have a first area, a second area, and a third area, respectively, and the first area is larger than the second area and the third area.

10. The semiconductor packaging assembly of claim 9, wherein the wafer further comprises: An insulating liner extends within the semiconductor substrate and surrounds portions of the second and third wiring layers located within the semiconductor substrate, wherein the insulating liner is spaced apart from the first wiring layer.

11. The semiconductor package assembly of claim 10, wherein the semiconductor substrate is in direct contact with the first redistribution layer.

12. The semiconductor packaging assembly of claim 9, wherein the wafer further comprises: An insulating liner is formed between the semiconductor substrate and the first, second, and third wiring layers.

13. The semiconductor packaging assembly of claim 9, wherein the wafer further comprises: An insulating layer is formed on the gallium nitride-based device layer and surrounds the source electrode structure, the drain electrode structure and the gate electrode structure.

14. The semiconductor package assembly of claim 9, wherein the circuit substrate has a grounding pad electrically connected to the first rewiring layer.

15. A semiconductor device structure, comprising: A semiconductor substrate having an active surface and a non-active surface relative to the active surface; A gallium nitride-based device layer has a lower surface adjacent to the active surface of the semiconductor substrate, such that the upper surface of the gallium nitride-based device layer is higher than the active surface, and has a first electrode contact area and a second electrode contact area, wherein the lower surfaces of the first electrode contact area and the second electrode contact area are adjacent to the active surface of the semiconductor substrate. The first through-hole electrode and the second through-hole electrode extend through the semiconductor substrate and are respectively electrically connected to the lower surface of the first electrode contact area and the top surface of the lower surface of the second electrode contact area. as well as A first conductive layer and a second conductive layer extend from the first via electrode and the second via electrode above the non-active surface of the semiconductor substrate, respectively. The first conductive layer and the second conductive layer have a first area and a second area, respectively, and the first area is different from the second area.

16. The semiconductor device structure of claim 15, wherein the first electrode contact region is a source electrode contact region, and the second electrode contact region is a drain electrode contact region or a gate electrode contact region.

17. The semiconductor device structure of claim 16, wherein the first area is larger than the second area.

18. The semiconductor device structure of claim 16, further comprising: An insulating liner is formed between the semiconductor substrate and the second via electrode and between the semiconductor substrate and the second conductive layer, and is separated from the first via electrode and the first conductive layer, wherein the first via electrode and the first conductive layer are in direct contact with the semiconductor substrate.

19. The semiconductor device structure of claim 15, further comprising: An insulating liner is formed between the semiconductor substrate and the first via electrode and the second via electrode, and between the semiconductor substrate and the first conductive layer and the second conductive layer.

20. The semiconductor device structure of claim 15, further comprising: The source electrode is formed on the gallium nitride-based device layer and is electrically connected to the first electrode contact region; as well as The drain electrode or gate electrode is formed on the gallium nitride-based device layer and is electrically connected to the second electrode contact area.

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